TWI456661B - 積體電路結構的形成方法 - Google Patents

積體電路結構的形成方法 Download PDF

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TWI456661B
TWI456661B TW099125729A TW99125729A TWI456661B TW I456661 B TWI456661 B TW I456661B TW 099125729 A TW099125729 A TW 099125729A TW 99125729 A TW99125729 A TW 99125729A TW I456661 B TWI456661 B TW I456661B
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Taiwan
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forming
region
type region
germanium substrate
integrated circuit
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TW099125729A
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TW201133631A (en
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Ru Shang Hsiao
Chung Te Lin
Nai Wen Cheng
Yin Kai Liao
Wei Chuang Wu
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Taiwan Semiconductor Mfg
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)

Claims (10)

  1. 一種積體電路結構的形成方法,包括:提供一矽基底;於該矽基底中佈植一p型摻雜物以形成一p型區;將氧共佈植進該矽基底中以形成一氧佈植區,其中該p型區之該較上部分與該氧佈植區重疊;以及在該佈植步驟及該共佈植步驟之後,進行一退火以形成一氧化矽區,其中部分的該p型區轉變為該氧化矽區。
  2. 如申請專利範圍第1項所述之積體電路結構的形成方法,更包括:在佈植該p型摻雜物之步驟之前,於該矽基底上形成一遮罩層,具有一開口形成於該遮罩層之中,其中該p型區係透過該開口而佈植形成;以及在進行該退火步驟之後,移除該遮罩層。
  3. 如申請專利範圍第1項所述之積體電路結構的形成方法,其中轉變為該氧化矽區之該部分的該p型區為該p型區之一較上部分,而該p型區之一較下部分不轉變成該氧化矽區。
  4. 如申請專利範圍第1項所述之積體電路結構的形成方法,更包括於該矽基底中形成一光二極體,該光二極體之一n型區橫向接觸該p型區。
  5. 如申請專利範圍第1項所述之積體電路結構的形成方法,其中該退火係於一反應室中進行,該反應室中之氧分壓介於約1E(-2)torrs與約5E2 torrs之間。
  6. 一種積體電路結構的形成方法,包括:提供一矽基底;於該矽基底上形成一遮罩層;圖案化該遮罩層以形成一開口;進行一共佈植,包括:透過該開口將一p型摻雜物佈植進入該矽基底以形成一p型區;以及透過該開口將一含氧材料佈植進入該矽基底以形成一氧佈植區;在進行該共佈植步驟之後,進行一退火以將該氧佈植區轉變為一氧化矽區;以及在該退火步驟之後,移除該遮罩層。
  7. 如申請專利範圍第6項所述之積體電路結構的形成方法,更包括於該矽基底中形成一光二極體,該光二極體之一n型區橫向接觸該p型區。
  8. 一種積體電路結構的形成方法,包括:提供一矽基底;對該矽基底之一表面部分進行一氧化製程以形成一氧化矽區;在該矽基底中形成包括一p型摻雜物之一p型區,該p型區直接位於該氧化矽區之下;以及於該矽基底中形成一光二極體,該光二極體之一n型區橫向接觸該p型區。
  9. 如申請專利範圍第8項所述之積體電路結構的形成方法,其中大抵整個該氧化矽區包括該p型摻雜物。
  10. 如申請專利範圍第8項所述之積體電路結構的形成方法,更包括在進行該氧化製程之步驟之前,將氧佈植進入該矽基底之直接位於該p型區之上的一部分之中,其中形成該p型區之步驟係使用佈植以佈植該p型摻雜物,其中一相同的遮罩層用以進行該佈植氧的步驟與佈植形成該p型區的步驟。
TW099125729A 2010-03-17 2010-08-03 積體電路結構的形成方法 TWI456661B (zh)

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US12/726,215 US8778717B2 (en) 2010-03-17 2010-03-17 Local oxidation of silicon processes with reduced lateral oxidation

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049966A (en) * 1990-11-15 1991-09-17 Micron Technology, Inc. Lateral transistor beta reduction by incorporation of electrically active material
TW518710B (en) * 2001-02-08 2003-01-21 Hitachi Ltd Semiconductor integrated circuit device and its manufacture method
TW200905792A (en) * 2007-07-20 2009-02-01 Tien-Hsi Lee Method for producing a thin film
TW200908208A (en) * 2007-08-08 2009-02-16 Promos Technologies Inc Method of fabricating silicon on insulator and silicon on insulator structure

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6245638B1 (en) * 1998-08-03 2001-06-12 Advanced Micro Devices Trench and gate dielectric formation for semiconductor devices
US6335562B1 (en) * 1999-12-09 2002-01-01 The United States Of America As Represented By The Secretary Of The Navy Method and design for the suppression of single event upset failures in digital circuits made from GaAs and related compounds
US6440805B1 (en) * 2000-02-29 2002-08-27 Mototrola, Inc. Method of forming a semiconductor device with isolation and well regions
US6465846B1 (en) * 2000-03-22 2002-10-15 Seiko Instruments Inc. Semiconductor integrated circuit device having trench-type photodiode
US6300218B1 (en) * 2000-05-08 2001-10-09 International Business Machines Corporation Method for patterning a buried oxide thickness for a separation by implanted oxygen (simox) process
US6341093B1 (en) * 2000-06-07 2002-01-22 International Business Machines Corporation SOI array sense and write margin qualification
US6632728B2 (en) * 2001-07-16 2003-10-14 Agere Systems Inc. Increasing the electrical activation of ion-implanted dopants
KR100428768B1 (ko) * 2001-08-29 2004-04-30 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성 방법
US6822292B2 (en) * 2001-11-21 2004-11-23 Intersil Americas Inc. Lateral MOSFET structure of an integrated circuit having separated device regions
JP3840203B2 (ja) * 2002-06-27 2006-11-01 キヤノン株式会社 固体撮像装置及び固体撮像装置を用いたカメラシステム
US7078745B2 (en) * 2003-03-05 2006-07-18 Micron Technology, Inc. CMOS imager with enhanced transfer of charge and low voltage operation
US6936505B2 (en) * 2003-05-20 2005-08-30 Intel Corporation Method of forming a shallow junction
US7122408B2 (en) * 2003-06-16 2006-10-17 Micron Technology, Inc. Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
JP4369885B2 (ja) * 2005-03-15 2009-11-25 セイコーインスツル株式会社 イメージセンサ
US7585694B2 (en) * 2005-03-31 2009-09-08 Panasonic Corporation Manufacturing method of solid-state imaging device
KR100752182B1 (ko) * 2005-10-12 2007-08-24 동부일렉트로닉스 주식회사 씨모스 이미지 센서 및 그 제조방법
US7276768B2 (en) * 2006-01-26 2007-10-02 International Business Machines Corporation Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
JP5157075B2 (ja) 2006-03-27 2013-03-06 株式会社Sumco Simoxウェーハの製造方法
US7741190B2 (en) * 2007-08-09 2010-06-22 National Semiconductor Corporation Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049966A (en) * 1990-11-15 1991-09-17 Micron Technology, Inc. Lateral transistor beta reduction by incorporation of electrically active material
TW518710B (en) * 2001-02-08 2003-01-21 Hitachi Ltd Semiconductor integrated circuit device and its manufacture method
TW200905792A (en) * 2007-07-20 2009-02-01 Tien-Hsi Lee Method for producing a thin film
TW200908208A (en) * 2007-08-08 2009-02-16 Promos Technologies Inc Method of fabricating silicon on insulator and silicon on insulator structure

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US8778717B2 (en) 2014-07-15
US20110230002A1 (en) 2011-09-22

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