TWI447895B - Semiconductor circuit - Google Patents

Semiconductor circuit Download PDF

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TWI447895B
TWI447895B TW098111821A TW98111821A TWI447895B TW I447895 B TWI447895 B TW I447895B TW 098111821 A TW098111821 A TW 098111821A TW 98111821 A TW98111821 A TW 98111821A TW I447895 B TWI447895 B TW I447895B
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region
doping
voltage source
voltage
semiconductor circuit
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TW098111821A
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TW201037814A (en
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Yao Sheng Huang
Ching Jung Yang
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Raydium Semiconductor Corp
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Description

半導體電路 Semiconductor circuit

本發明係關於一種半導體電路,特別是關於一種具有電壓源線之穩壓功能的半導體電路。 The present invention relates to a semiconductor circuit, and more particularly to a semiconductor circuit having a voltage stabilizing function of a voltage source line.

隨著半導體技術的發展,積體電路的製作不斷引進更先進的製程技術。藉此,現今的微型電子電路,其可以在微小的電位差下,以微小的電流驅動,即可執行各種應用功能。消費者因此享受到更輕薄、更高效能且更低電耗的高科技產品。 With the development of semiconductor technology, the production of integrated circuits continues to introduce more advanced process technology. Thereby, today's microelectronic circuits can be driven with a small current at a small potential difference to perform various application functions. Consumers are therefore enjoying high-tech products that are thinner, more efficient and less power-hungry.

為了可以精確控制半導體電路的運作狀態,對各種電子訊號便有極高的精確度(preciseness)要求。在現今的積體電路應用中,以運算放大器(operational amplifier)為例,通常運算放大器除了接收欲放大之輸入訊號之後,運算放大器本身另需耦接電壓源線。電壓源線用以供給各種電子元件所需的電能,以驅動電子元件正常運作。 In order to accurately control the operation state of the semiconductor circuit, there is a very high precision requirement for various electronic signals. In today's integrated circuit applications, an operational amplifier is taken as an example. In addition to the input signal to be amplified, the operational amplifier itself needs to be coupled to the voltage source line. The voltage source line is used to supply the electrical energy required by various electronic components to drive the electronic components to operate normally.

通常這些電壓源線為半導體電路中的全域線(global line),單一電壓源線需要對應到許多電子元件(例如放大器、轉換器、負載等)。電壓源線需能持續地供應穩定的額定電壓。若是電壓源線提供的電壓偏移,則可能造成各種元件的工作狀態大亂,導致電子裝置故障或毀損。 Typically these voltage source lines are global lines in a semiconductor circuit, and a single voltage source line needs to correspond to many electronic components (eg, amplifiers, converters, loads, etc.). The voltage source line must be continuously supplied with a stable rated voltage. If the voltage provided by the voltage source line is offset, the working conditions of various components may be disordered, resulting in malfunction or damage of the electronic device.

一般而言,電壓源線通常電性連接相對應的穩壓電容, 穩壓電容可以穩定電壓源線的電壓供給,提高整體電路的穩定性。一般電容器元件體積過大,並不適用,通常採用半導體電容作為電壓源線的穩壓電容。 Generally, the voltage source line is usually electrically connected to a corresponding voltage stabilizing capacitor. The voltage stabilizing capacitor can stabilize the voltage supply of the voltage source line and improve the stability of the overall circuit. Generally, the capacitor component is too large and is not suitable. Generally, a semiconductor capacitor is used as a voltage stabilizing capacitor of the voltage source line.

請參閱圖一。圖一繪示先前技術中半導體電路1的示意圖。如圖一所示,半導體電路1包含基材10(substrate)、薄氧化層12(thin oxide layer)、多晶矽層14(polysilicon layer)以及電壓源線16(voltage source rail)。透過設置於基材10上的薄氧化層12以及進一步設置於薄氧化層12上的多晶矽層14,可形成的一個半導體電容結構。此半導體電容可作為通過多晶矽層14上方之電壓源線16的穩壓電容。 Please refer to Figure 1. 1 is a schematic view of a prior art semiconductor circuit 1. As shown in FIG. 1, the semiconductor circuit 1 includes a substrate 10, a thin oxide layer 12, a polysilicon layer, and a voltage source rail. A semiconductor capacitor structure can be formed by a thin oxide layer 12 disposed on the substrate 10 and a polysilicon layer 14 further disposed on the thin oxide layer 12. This semiconductor capacitor acts as a stabilizing capacitor through the voltage source line 16 above the polysilicon layer 14.

然而,上述先前技術中的穩壓電容因利用基材提供電容器效果,電壓源線的電壓訊號將對基材上其它的電子元件造成干擾。 However, the above-mentioned prior art voltage stabilizing capacitors provide a capacitor effect by using a substrate, and the voltage signal of the voltage source line will interfere with other electronic components on the substrate.

此外,電子裝置在製造、搬運甚至是正常操作的情況下,皆有可能在電子裝置內部累積靜電。當不可預期的靜電放電現象發生時,產生的靜電放電電流可能在電子裝置的內部工作電路四處流竄,這些靜電放電電流對電子裝置的內部工作電路造成不可回復的損壞。 In addition, in the case of manufacturing, handling, or even normal operation of an electronic device, it is possible to accumulate static electricity inside the electronic device. When an unexpected electrostatic discharge phenomenon occurs, the generated electrostatic discharge current may flow around the internal working circuit of the electronic device, and these electrostatic discharge currents cause irreparable damage to the internal working circuit of the electronic device.

先前技術中,電子裝置為了避免靜電放電電流對內部工作電路可能造成的損壞,通常需具有靜電放電防護功能的半導體電路。靜電放電防護電路用以將可能造成危害的靜電放電電流導入特定的靜電放電路徑,避免損壞精密的內部工作電路。 In the prior art, in order to avoid damage that the electrostatic discharge current may cause to the internal working circuit, an electronic circuit having an electrostatic discharge protection function is generally required. The ESD protection circuit is used to introduce a possible electrostatic discharge current into a specific ESD path to avoid damage to the delicate internal working circuit.

請參閱圖二以及圖三。圖二繪示先前技術中具有靜電放電防護用的半導體電路20的電子裝置2的示意圖。圖三繪示圖二中半導體電路20的電路結構示意圖。如圖二所示,電子裝置2中的訊號輸入端Vin到內部工作電路22之間通常耦接有靜電放電防護用的二極體電路結構(半導體電路20)。如圖三所示,半導體電路20包含基材200以及二極體電路結構202。但二極體電路結構202因設置在基材200中,亦會對基材200中鄰近的其他元件造成干擾。 Please refer to Figure 2 and Figure 3. 2 is a schematic diagram of an electronic device 2 having a semiconductor circuit 20 for electrostatic discharge protection in the prior art. FIG. 3 is a schematic diagram showing the circuit structure of the semiconductor circuit 20 in FIG. As shown in FIG. 2, a diode circuit structure (semiconductor circuit 20) for electrostatic discharge protection is generally coupled between the signal input terminal Vin and the internal working circuit 22 in the electronic device 2. As shown in FIG. 3, the semiconductor circuit 20 includes a substrate 200 and a diode circuit structure 202. However, because the diode circuit structure 202 is disposed in the substrate 200, it also interferes with other components in the substrate 200.

本發明提出一種半導體電路,其具有電壓源線之穩壓功能亦可作為靜電放電防護電路,以解決上述問題。 The invention provides a semiconductor circuit having a voltage source function of a voltage source line or an electrostatic discharge protection circuit to solve the above problems.

本發明之一範疇在於提供一種半導體電路,其具有穩定電壓源線的電壓訊號之功能。 One aspect of the present invention is to provide a semiconductor circuit having the function of stabilizing a voltage signal of a voltage source line.

根據一具體實施例,該半導體電路包含基材、介電層、多晶矽層以及電壓源線。介電層設置於基材上。多晶矽層設置於介電層上。多晶矽層其具有第一摻雜區、第二摻雜區以及介於第一摻雜區與第二摻雜區之間的本質區。電壓源線通過多晶矽層上方。多晶矽層透過第一摻雜區、第二摻雜區以及本質區形成穩壓電容,穩壓電容用以對應穩定該電壓源線之通過電壓,進而提高半導體電路的穩定性。 According to a specific embodiment, the semiconductor circuit includes a substrate, a dielectric layer, a polysilicon layer, and a voltage source line. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. The polysilicon layer has a first doped region, a second doped region, and an intrinsic region between the first doped region and the second doped region. The voltage source line passes over the polysilicon layer. The polysilicon layer forms a voltage stabilizing capacitor through the first doping region, the second doping region and the intrinsic region, and the stabilizing capacitor is used to stabilize the pass voltage of the voltage source line, thereby improving the stability of the semiconductor circuit.

本發明之另一範疇在於提供一種半導體電路,其具有靜電放電防護電路之功能。 Another aspect of the present invention is to provide a semiconductor circuit having the function of an electrostatic discharge protection circuit.

根據一具體實施例,該半導體電路包含基材、介電層以及多晶矽層。介電層設置於基材上。多晶矽層設置於介電層上。多晶矽層其具有第一摻雜區、第二摻雜區以及介於第一摻雜區與第二摻雜區之間的本質區。多晶矽層之第一摻雜區與第二摻雜區形成二極體結構,該二極體可用以作為靜電放電防護的放電路徑。 According to a specific embodiment, the semiconductor circuit includes a substrate, a dielectric layer, and a polysilicon layer. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. The polysilicon layer has a first doped region, a second doped region, and an intrinsic region between the first doped region and the second doped region. The first doped region and the second doped region of the polysilicon layer form a diode structure, and the diode can be used as a discharge path for electrostatic discharge protection.

相較於先前技術,本發明提出的半導體電路,可作為電壓源線的穩壓電容,於另一應用中,亦可作為靜電放電電流的放電路徑,因本發明之半導體電路係利用多晶矽層本身的摻雜設計,以形成穩壓電容或靜電放電防護之效果,其結構簡單、製作方便、體積小且不易對電路基材上其他元件造成干擾。 Compared with the prior art, the semiconductor circuit proposed by the present invention can be used as a voltage stabilizing capacitor of a voltage source line. In another application, it can also serve as a discharge path of an electrostatic discharge current. The semiconductor circuit of the present invention utilizes the polysilicon layer itself. The doping design is to form a stabilizing capacitor or an electrostatic discharge protection effect, and has a simple structure, convenient fabrication, small volume, and difficulty in causing interference to other components on the circuit substrate.

關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

請參閱圖四以及圖五。圖四繪示根據本發明之一具體實施例中半導體電路3的示意圖。圖五繪示圖四中半導體電路3的側面示意圖。如圖四及圖五所示,半導體電路3包含基材30、介電層32、多晶矽層34以及電壓源線36。 Please refer to Figure 4 and Figure 5. 4 is a schematic diagram of a semiconductor circuit 3 in accordance with an embodiment of the present invention. FIG. 5 is a schematic side view of the semiconductor circuit 3 of FIG. As shown in FIGS. 4 and 5, the semiconductor circuit 3 includes a substrate 30, a dielectric layer 32, a polysilicon layer 34, and a voltage source line 36.

介電層32設置於基材30上。多晶矽層34進一步設置於介電層32上。介電層32可為薄氧化層或場氧化層。一般來說,場氧化層的氧化層厚度較薄氧化層為厚。實際應用中,場氧化層通常設置於電路板上電路較不密集之處,可提供較 好的靜電隔離效果,避免基材30受到雜訊干擾,影響設置於基材30上的其它元件。圖四中介電層32以場氧化層為例,但本發明之應用中介電層32亦可為不同厚度之氧化層達到相似效果,不以場氧化層為限。 The dielectric layer 32 is disposed on the substrate 30. The polysilicon layer 34 is further disposed on the dielectric layer 32. Dielectric layer 32 can be a thin oxide layer or a field oxide layer. Generally, the oxide layer of the field oxide layer is thicker than the thin oxide layer. In practical applications, the field oxide layer is usually placed on the circuit board where the circuit is less dense, which can provide A good electrostatic isolation effect prevents the substrate 30 from being disturbed by noise and affects other components disposed on the substrate 30. The dielectric layer 32 is exemplified by the field oxide layer. However, the dielectric layer 32 of the present invention can also achieve similar effects for the oxide layers of different thicknesses, and is not limited to the field oxide layer.

多晶矽層34為一多晶矽材料,利用目前積體電路普遍採用的多晶矽閘極製程設置於介電層32上方。於此實施例中,本發明的多晶矽層34中另以摻雜方式形成第一摻雜區340以及第二摻雜區342。介於第一摻雜區340與第二摻雜區342之間為多晶矽層34的本質區344。 The polysilicon layer 34 is a polysilicon material which is disposed over the dielectric layer 32 by a polysilicon gate process commonly employed in current integrated circuits. In this embodiment, the first doped region 340 and the second doped region 342 are formed by doping in the polysilicon layer 34 of the present invention. Between the first doped region 340 and the second doped region 342 is an intrinsic region 344 of the polysilicon layer 34.

電壓源線36通過多晶矽層34上方。電壓源線36為半導體電路3的電能來源,用以電性驅動半導體電路3中的其他電子元件(未繪示)。 The voltage source line 36 passes over the polysilicon layer 34. The voltage source line 36 is a source of electrical energy for the semiconductor circuit 3 for electrically driving other electronic components (not shown) in the semiconductor circuit 3.

於此實施例中,電壓源線36可為高壓源線(電子電路中的Vdd線)、低壓源線(Vss線)或接地線(GND線)。其中此處之接地線並非限定於實質的大地接地(earth-ground),此處的接地線可為電子電路採用的數位接地(digital-ground),用以作為電子電路中的基準電壓零點之用。電壓源線36具有一通過電壓。一般來說,目前的半導體電路元件對訊號具有極高的靈敏度,尤其是類比或高頻元件更是需要高品質且穩定的電源供給。 In this embodiment, the voltage source line 36 can be a high voltage source line (Vdd line in an electronic circuit), a low voltage source line (Vss line), or a ground line (GND line). The grounding wire here is not limited to a substantial earth-ground. The grounding wire here can be a digital-ground used in an electronic circuit for use as a reference voltage zero point in an electronic circuit. . Voltage source line 36 has a pass voltage. In general, current semiconductor circuit components have extremely high sensitivity to signals, and in particular analog or high frequency components require a high quality and stable power supply.

多晶矽層34的第一摻雜區340具有第一摻雜型,第二摻雜區342具有第二摻雜型,第一摻雜區340與第二摻雜區342的摻雜型相反。舉例來說,第一摻雜區340為電洞型(P型)摻雜,則第二摻雜區342即為電子型(N型)摻雜。藉 此,多晶矽層34的兩個摻雜區可形成二極體的電路結構。於此同時,二極體也產生寄生電容(parasitic capacitor)的效果。也就是說,多晶矽層34透過第一摻雜區340、第二摻雜區342以及本質區344形成二極體寄生電容,作為穩定該電壓源線36之通過電壓的穩壓電容。 The first doped region 340 of the polysilicon layer 34 has a first doping type, and the second doping region 342 has a second doping type, and the first doping region 340 is opposite to the doping type of the second doping region 342. For example, the first doping region 340 is a hole type (P type) doping, and the second doping region 342 is an electron type (N type) doping. borrow Thus, the two doped regions of the polysilicon layer 34 can form a circuit structure of the diode. At the same time, the diode also produces a parasitic capacitor effect. That is, the polysilicon layer 34 forms a diode parasitic capacitance through the first doping region 340, the second doping region 342, and the intrinsic region 344 as a stabilizing capacitor that stabilizes the pass voltage of the voltage source line 36.

綜上所述,本發明的半導體電路結構係在多晶矽層中形成不同的摻雜區域以達成穩壓電容之效果,而多晶矽層係設置於介電層上,多晶矽層不直接與基材連接,並以此介電層提供多晶矽層與基材之間的絕緣效果。因此,以此多晶矽層形成之二極體作為電壓源線之穩壓電容,可減低對基材上其他電子元件之干擾。 In summary, the semiconductor circuit structure of the present invention forms different doped regions in the polysilicon layer to achieve the effect of stabilizing capacitance, and the polysilicon layer is disposed on the dielectric layer, and the polysilicon layer is not directly connected to the substrate. And the dielectric layer provides an insulating effect between the polysilicon layer and the substrate. Therefore, the diode formed by the polysilicon layer serves as a voltage stabilizing capacitor of the voltage source line, which can reduce interference with other electronic components on the substrate.

請參閱圖六。圖六繪示根據本發明之一具體實施例中半導體電路5的側面示意圖。如圖六所示,半導體電路5包含基材50、介電層52以及多晶矽層54。介電層52設置於基材50上。介電層52可為薄氧化層或場氧化層。 Please refer to Figure 6. Figure 6 is a side elevational view of a semiconductor circuit 5 in accordance with an embodiment of the present invention. As shown in FIG. 6, the semiconductor circuit 5 includes a substrate 50, a dielectric layer 52, and a polysilicon layer 54. The dielectric layer 52 is disposed on the substrate 50. Dielectric layer 52 can be a thin oxide layer or a field oxide layer.

多晶矽層54設置於介電層52上。多晶矽層54其具有第一摻雜區540、第二摻雜區542以及介於第一摻雜區與第二摻雜區之間的本質區544。多晶矽層54的第一摻雜區540具有第一摻雜型,第二摻雜區542具有第二摻雜型,第一摻雜區540與第二摻雜區542的摻雜型相反。於此實施例中,第一摻雜區540為電洞型(P型)摻雜,則第二摻雜區542即為電子型(N型)摻雜。多晶矽層54之第一摻雜區540與第二摻雜區542形成二極體結構,該二極體可用以作為靜電放電防護的放電路徑。 A polysilicon layer 54 is disposed on the dielectric layer 52. The polysilicon layer 54 has a first doped region 540, a second doped region 542, and an intrinsic region 544 between the first doped region and the second doped region. The first doped region 540 of the polysilicon layer 54 has a first doping type, and the second doping region 542 has a second doping type, and the first doping region 540 is opposite to the doping type of the second doping region 542. In this embodiment, the first doping region 540 is a hole type (P type) doping, and the second doping region 542 is an electron type (N type) doping. The first doped region 540 and the second doped region 542 of the polysilicon layer 54 form a diode structure, which can be used as a discharge path for electrostatic discharge protection.

於此實施例中,第一摻雜區540其為P型摻雜,故與第一摻雜區540電性連接的端點56a可視為二極體陽極,另一方面與第一摻雜區542電性連接的端點56b可視為二極體陰極。 In this embodiment, the first doping region 540 is P-type doped, so the terminal end 56a electrically connected to the first doping region 540 can be regarded as a diode anode, and on the other hand, the first doping region. The end point 56b of the 542 electrical connection can be considered a diode cathode.

請一併參閱圖七。圖七繪示圖六半導體電路5用於靜電防護功能時的電路示意圖。如圖七所示,半導體電路5可耦接於高壓源線Vdd與訊號輸入端Vin之間。若是訊號輸入端Vin發生異常的靜電放電現象,使訊號輸入端的電壓瞬間高過系統正常的額定高電壓(即Vdd)加上二極體的啟動電壓(通常為0.7伏特)時,則半導體電路5形成的二極體即順向偏壓並將訊號輸入端Vin的過高電壓導引至高壓源線Vdd,以達成靜電放電保護功能,避免傷害內部工作電路6。 Please refer to Figure 7 together. FIG. 7 is a schematic circuit diagram of the semiconductor circuit 5 of FIG. 6 when it is used for an electrostatic protection function. As shown in FIG. 7, the semiconductor circuit 5 can be coupled between the high voltage source line Vdd and the signal input terminal Vin. If an abnormal electrostatic discharge occurs in the signal input terminal Vin, the voltage at the signal input terminal is instantaneously higher than the normal rated high voltage of the system (ie, Vdd) plus the startup voltage of the diode (usually 0.7 volts), then the semiconductor circuit 5 The formed diode is forward biased and the excessive voltage of the signal input terminal Vin is guided to the high voltage source line Vdd to achieve an electrostatic discharge protection function to avoid harming the internal working circuit 6.

同理,半導體電路5亦可被耦接於訊號輸入端Vin與低電壓源Vss之間。相似地,當使訊號輸入端的電壓瞬間低於系統正常的額定低電壓(即Vss)時,即可啟動保護功能。藉此,可保證內部工作電路6的輸入範圍在一定的區間之內,避免內部工作電路6因輸入訊號的異常變動而毀損。 Similarly, the semiconductor circuit 5 can also be coupled between the signal input terminal Vin and the low voltage source Vss. Similarly, the protection function can be activated when the voltage at the signal input is instantaneously lower than the normal rated low voltage (ie, Vss) of the system. Thereby, the input range of the internal working circuit 6 can be ensured to be within a certain interval, and the internal working circuit 6 can be prevented from being damaged due to abnormal changes of the input signal.

綜上所述,本發明的半導體電路結構係在多晶矽層形成不同的摻雜區域以形成二極體電路結構,而多晶矽層係設置於介電層上,多晶矽層不直接與基材連接,並以此介電層提供多晶矽層與基材之間的絕緣效果。因此,以此多晶矽層形成之二極體作為靜電放電的放電路徑,可減低對 基材上其他電子元件之干擾。 In summary, the semiconductor circuit structure of the present invention forms different doped regions in the polysilicon layer to form a diode circuit structure, and the polysilicon layer is disposed on the dielectric layer, and the polysilicon layer is not directly connected to the substrate, and This dielectric layer provides an insulating effect between the polysilicon layer and the substrate. Therefore, the diode formed by the polysilicon layer acts as a discharge path for electrostatic discharge, which can reduce the pair Interference from other electronic components on the substrate.

相較於先前技術,本發明提出的半導體電路,可作為電壓源線的穩壓電容,於另一應用中,亦可作為靜電放電電流的放電路徑,因本發明之半導體電路係利用多晶矽層本身的摻雜設計,以形成穩壓電容或靜電放電防護之效果,其結構簡單、製作方便、體積小且不易對電路基材上其他元件造成干擾。 Compared with the prior art, the semiconductor circuit proposed by the present invention can be used as a voltage stabilizing capacitor of a voltage source line. In another application, it can also serve as a discharge path of an electrostatic discharge current. The semiconductor circuit of the present invention utilizes the polysilicon layer itself. The doping design is to form a stabilizing capacitor or an electrostatic discharge protection effect, and has a simple structure, convenient fabrication, small volume, and difficulty in causing interference to other components on the circuit substrate.

藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

1、20、3、5‧‧‧半導體電路 1, 20, 3, 5‧‧‧ semiconductor circuits

2‧‧‧電子裝置 2‧‧‧Electronic devices

202‧‧‧二極體電路結構 202‧‧‧Diode circuit structure

10、200、30、50‧‧‧基材 10, 200, 30, 50‧‧‧ substrates

22、6‧‧‧內部工作電路 22, 6‧‧‧ internal working circuit

12、32、52‧‧‧介電層 12, 32, 52‧‧‧ dielectric layer

14、34、54‧‧‧多晶矽層 14, 34, 54‧‧‧ polycrystalline layer

16、36‧‧‧電壓源線 16, 36‧‧‧voltage source line

340、540‧‧‧第一摻雜區 340, 540‧‧‧ first doped area

342、542‧‧‧第二摻雜區 342, 542‧‧‧Second doped area

344、544‧‧‧本質區 344, 544‧‧‧ Essential Area

56a、56b‧‧‧端點 56a, 56b‧‧‧ endpoint

Vin‧‧‧訊號輸入端 Vin‧‧‧ signal input

Vdd‧‧‧高壓源線 Vdd‧‧‧High voltage source line

Vss‧‧‧低壓源線 Vss‧‧‧ low voltage source line

圖一繪示先前技術中半導體電路的示意圖。 1 is a schematic diagram of a semiconductor circuit in the prior art.

圖二繪示先前技術中具有靜電放電防護用的半導體電路的電子裝置的示意圖。 2 is a schematic diagram of an electronic device having a semiconductor circuit for electrostatic discharge protection in the prior art.

圖三繪示圖二中半導體電路的電路結構示意圖。 FIG. 3 is a schematic diagram showing the circuit structure of the semiconductor circuit in FIG.

圖四繪示根據本發明之一具體實施例中半導體電路的俯視示意圖。 4 is a top plan view of a semiconductor circuit in accordance with an embodiment of the present invention.

圖五繪示圖四中半導體電路的側面示意圖。 FIG. 5 is a side view showing the semiconductor circuit of FIG.

圖六繪示根據本發明之一具體實施例中半導體電路的側面示意圖。 6 is a side elevational view of a semiconductor circuit in accordance with an embodiment of the present invention.

圖七繪示圖六半導體電路用於靜電防護功能時的電路示意圖。 FIG. 7 is a schematic circuit diagram of the semiconductor circuit of FIG. 6 when used for an electrostatic protection function.

3‧‧‧半導體電路 3‧‧‧Semiconductor circuit

30‧‧‧基材 30‧‧‧Substrate

32‧‧‧介電層 32‧‧‧Dielectric layer

34‧‧‧多晶矽層 34‧‧‧Polysilicon layer

36‧‧‧電壓源線 36‧‧‧Voltage source line

340‧‧‧第一摻雜區 340‧‧‧First doped area

342‧‧‧第二摻雜區 342‧‧‧Second doped area

344‧‧‧本質區 344‧‧‧ Essential Area

Claims (6)

一種半導體電路,設置於一電壓源線與一訊號輸入端之間並耦接一內部工作電路,該半導體電路包含:一基材;一介電層,設置於該基材上;以及一多晶矽層,設置於該介電層上,其具有一第一摻雜區、一第二摻雜區以及介於該第一摻雜區與該第二摻雜區之間的一本質區,該電壓源線通過該多晶矽層上方;其中,該第一摻雜區之一第一摻雜型與該第二摻雜區之一第二摻雜型相反,使得該第一摻雜區與該第二摻雜區形成一二極體且該多晶矽層透過該第一摻雜區、該第二摻雜區以及該本質區形成一穩壓電容,該穩壓電容用以對應穩定該電壓源線之一通過電壓,該電壓源線為一高壓源線,若該訊號輸入端發生異常的靜電放電現象,使得該訊號輸入之一瞬間電壓高過系統正常的額定高電壓加上該二極體之啟動電壓時,該二極體即順向偏壓並將該訊號輸入端之過高的該瞬間電壓導引至該電壓源線,以保護該內部工作電路。 A semiconductor circuit is disposed between a voltage source line and a signal input end and coupled to an internal working circuit, the semiconductor circuit comprising: a substrate; a dielectric layer disposed on the substrate; and a polysilicon layer Provided on the dielectric layer, having a first doped region, a second doped region, and an intrinsic region between the first doped region and the second doped region, the voltage source a line passes over the polysilicon layer; wherein a first doping type of the first doping region is opposite to a second doping type of the second doping region, such that the first doping region and the second doping region The stabilizing region forms a diode and the polysilicon layer forms a stabilizing capacitor through the first doping region, the second doping region and the intrinsic region, and the stabilizing capacitor is configured to stabilize one of the voltage source lines Voltage, the voltage source line is a high voltage source line. If an abnormal electrostatic discharge occurs at the signal input end, the instantaneous voltage of one of the signal inputs is higher than the normal rated high voltage of the system plus the starting voltage of the diode. The diode is forward biased and the signal input The high instantaneous voltage to the voltage source line guide, to protect the internal circuitry. 如申請專利範圍第1項所述之半導體電路,其中該介電層為一薄氧化層(thin oxide)。 The semiconductor circuit of claim 1, wherein the dielectric layer is a thin oxide. 如申請專利範圍第1項所述之半導體電路,其中該介電層為一場氧化層(field oxide)。 The semiconductor circuit of claim 1, wherein the dielectric layer is a field oxide. 一種半導體電路,設置於一電壓源線與一訊號輸入端之 間並耦接一內部工作電路,該半導體電路包含:一基材;一介電層,設置於該基材上;以及一多晶矽層,設置於該介電層上,其具有一第一摻雜區、一第二摻雜區以及介於該第一摻雜區與該第二摻雜區之間的一本質區,該電壓源線通過該多晶矽層上方;其中,該第一摻雜區之一第一摻雜型與該第二摻雜區之一第二摻雜型相反,使得該第一摻雜區與該第二摻雜區形成一二極體且該多晶矽層透過該第一摻雜區、該第二摻雜區以及該本質區形成一穩壓電容,該穩壓電容用以對應穩定該電壓源線之一通過電壓,該電壓源線為一低壓源線,當該訊號輸入端之一瞬間電壓低於系統正常的額定低電壓時,即可啟動該二極體維持該內部工作電路的輸入範圍在一特定電壓區間之內,以保護該內部工作電路。 a semiconductor circuit disposed on a voltage source line and a signal input end And interposing an internal working circuit, the semiconductor circuit comprising: a substrate; a dielectric layer disposed on the substrate; and a polysilicon layer disposed on the dielectric layer having a first doping a region, a second doped region, and an intrinsic region between the first doped region and the second doped region, the voltage source line passing over the polysilicon layer; wherein the first doped region a first doping type is opposite to a second doping type of the second doping region, such that the first doping region and the second doping region form a diode and the polysilicon layer passes through the first doping The stabilizing region, the second doping region and the intrinsic region form a voltage stabilizing capacitor, wherein the stabilizing capacitor is configured to stabilize a voltage passing through one of the voltage source lines, and the voltage source line is a low voltage source line, when the signal is input When one of the terminals is lower than the normal rated low voltage of the system, the diode can be activated to maintain the input range of the internal working circuit within a certain voltage range to protect the internal working circuit. 如申請專利範圍第4項所述之半導體電路,其中該介電層為一薄氧化層(thin oxide)。 The semiconductor circuit of claim 4, wherein the dielectric layer is a thin oxide. 如申請專利範圍第4項所述之半導體電路,其中該介電層為一場氧化層(field oxide)。 The semiconductor circuit of claim 4, wherein the dielectric layer is a field oxide.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW416133B (en) * 1999-02-12 2000-12-21 United Microelectronics Corp Manufacturing method for integrated circuit having electrostatic discharge protection circuit
TW200807674A (en) * 2006-07-31 2008-02-01 Alfaplus Semiconductor Inc ESD protection device
TW200816445A (en) * 2006-09-20 2008-04-01 Himax Tech Ltd ESD protection apparatus and circuit thereof
TW200826276A (en) * 2006-11-16 2008-06-16 Alpha & Omega Semiconductor Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
TW200847384A (en) * 2007-05-21 2008-12-01 Alpha & Omega Semiconductor Improved layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW416133B (en) * 1999-02-12 2000-12-21 United Microelectronics Corp Manufacturing method for integrated circuit having electrostatic discharge protection circuit
TW200807674A (en) * 2006-07-31 2008-02-01 Alfaplus Semiconductor Inc ESD protection device
TW200816445A (en) * 2006-09-20 2008-04-01 Himax Tech Ltd ESD protection apparatus and circuit thereof
TW200826276A (en) * 2006-11-16 2008-06-16 Alpha & Omega Semiconductor Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
TW200847384A (en) * 2007-05-21 2008-12-01 Alpha & Omega Semiconductor Improved layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device

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