TWI443964B - Signal converter with overvoltage protection mechanism - Google Patents

Description

Signal converter with overvoltage protection mechanism

The invention relates to a signal converter, in particular to a signal converter with an overvoltage protection mechanism.

Nowadays, the trend of multimedia audio products is toward light, short, and portable. However, in order to consider portability, it is necessary to have a long battery life, so the efficiency of the operation is high, and high-definition is also considered. Degree and high sampling frequency audio quality.

Please refer to Figure 1 for the circuit diagram of Class D audio amplifier. Class D audio amplifier has very good working efficiency compared with linear amplifier. Its theoretical value is up to 100%, and the efficiency is increased relative to the heat generated. Less, less heat is generated without additional heat sinks, thus reducing production costs. The class D audio amplifier is mainly composed of a modulation circuit 1, an amplifying circuit 2 and a low pass filter 3; the modulation circuit 1 usually includes a Pulse-Width-Modulation (PWM) and Sigma-Delta-Modulation (SDM), which mainly adjusts the input audio signal 5 to the second-order voltage signal 6 expressed by the wave width, and then controls the ON of the amplifying circuit 2 by using the second-order voltage signal 6. /OFF, to achieve the purpose of amplifying the current, and finally requires a low-pass filter 3 to restore the signal, and then output by the loudspeaker 4.

When the input audio signal 5 is modulated by the pulse width, it is a second-order voltage signal 6. After the signal is amplified by the amplifying circuit 2, it is still a second-order voltage signal 6, and the function of the subsequent low-pass filter 3 is to filter out the high-frequency harmonic signal. Energy, which reduces the effects of noise and electromagnetic interference. In the time domain, its action is similar to that of an integrator. As time increases, it slowly accumulates or releases the signal level and energy to achieve modulation. After the signal is restored.

However, since the voltage difference of the second-order voltage signal 6 at the moment of voltage change is too large, it is difficult for the low-pass filter 3 to quickly accumulate the signal energy, that is, the phase error itself, causing the signal of the output voltage to be distorted 7, resulting in The signal is not easy to achieve low distortion, high fax audio voltage signal reduction, the second order voltage signal 6 compared to the sinusoidal waveform of the input audio signal 5 contains a lot of signal distortion 7 .

Therefore, the "MULTI-LEVEL OUTPUT SIGNAL CONVERTER" of the US Patent Publication No. 20110019837 discloses a multi-level converter that converts a voltage signal originally having a second-order high-order-difference property into a signal having a multi-order low-order quasi-difference property. Therefore, the design complexity of the low-pass filter in the prior art is greatly simplified, and the high-frequency harmonic interference can be significantly reduced, the signal distortion caused by the amplifying circuit can be reduced, and the signal resolution can be effectively improved. However, if the input signal is too large, the relative converted output signal voltage will also become high. If the output signal voltage is higher than the critical value, it will not only cause serious distortion, but also damage the rear receiving circuit.

In order to avoid damage to the rear receiving circuit, it is necessary to avoid the output voltage or current is higher than the rear receiving circuit, so the output voltage or current must be exceeded by the hard-clipping or soft-clipping method. When reducing the output voltage or current to avoid circuit damage, using the above method can cause serious distortion problems.

The main object of the present invention is to improve the hard cutting or soft cutting mode of the prior art, and to adjust the output voltage or current more appropriately, so as to avoid excessive voltage or current damage to the rear receiving circuit, causing serious component or system damage.

To achieve the above objective, the present invention provides a signal converter having an overvoltage protection mechanism, including a pulse width adjusting unit, a timing processing unit connected to the pulse width adjusting unit, and a timing processing unit connected thereto. a voltage detecting unit, a pulse width control unit, and another multi-stage converting unit connected to the timing processing unit. The pulse width adjusting unit converts a type of analog signal into a pulse signal, and the width of the pulse signal is modulated according to the magnitude of the analog signal; the timing processing unit receives the pulse signal and converts it into a digital signal; The overvoltage detecting unit receives the digital signal and determines that the digital signal is a highest critical signal or a lowest critical value signal, and outputs an over-critical signal; the pulse width control unit and the over-voltage detecting unit and the The pulse width adjusting unit is connected to output a control signal to the pulse width adjusting unit by the judgment of the overvoltage detecting unit; the multi-level converting unit receives the digital signal exchange in the same manner as the overvoltage detecting unit And converted to a multi-level digital signal output.

According to the above description, the overvoltage detecting unit uses the overvoltage detecting unit to capture the digital signal of the timing processing unit, and forms a feedback through the connection between the pulse width control unit and the pulse width adjusting unit to adjust the output voltage to avoid Because the output voltage signal is too high, there is a problem of burning the rear to accept the circuit.

The detailed description and technical contents of the present invention will now be described as follows:

Referring to FIG. 2, the present invention is a signal converter with an overvoltage protection mechanism, including a pulse width adjusting unit 10, a timing processing unit 20 connected to the pulse width adjusting unit 10, and a An overvoltage detecting unit 30 connected to the timing processing unit 20, a pulse width control unit 40, and another multi-stage converting unit 50 connected to the timing processing unit 20. The pulse width adjusting unit 10 converts an analog signal 9 into a pulse signal 11. In the embodiment, the analog signal 9 is an audio output signal, and the pulse signal 11 has a width according to an analogy. The timing signal processing unit 20 receives the pulse signal 11 and converts it into a digital signal 21, and the different digital code combinations of the digital signal 21 respectively represent different pulse signals 11, that is, Corresponding to the numerical value of the analog signal 9, for example, it can be a four-digit digital code, and the numerical value of the analog signal 9 can be divided into 16 orders.

The over-voltage detecting unit 30 is configured to receive the digital signal 21 and determine that the digital signal 21 is a highest critical signal or a lowest critical signal, and outputs an over-critical signal 31. Since the digital code in the digital signal 21 corresponds to the numerical value of the analog signal 9, when the analog signal 9 is greater than the highest value that the circuit can withstand, the digital signal 21 can only be represented by a specific formatted digital code. For example, 1100 or 1111, which is the highest critical signal referred to in the present invention; relatively, when the analog signal 9 is smaller than the lowest acceptable value, the digital signal 21 can only be encoded by another specific number. It means that, for example, 0000 or 0001 is the lowest critical signal referred to in the present invention, and the lowest value referred to herein refers to a negative voltage, so that when the negative value is larger, the circuit is damaged. Therefore, the overvoltage detecting unit 30 can determine whether the analog signal 9 has reached or is greater than (less than) the highest (lowest) power output by whether the digital signal 21 is the highest critical signal or the lowest critical signal. Output limit. Referring to FIG. 3, the overvoltage detecting unit 30 includes a decoder 32 connected to the timing processing unit 20, a timing delay 33 connected to the decoder 32, and a decoder. 32 is coupled to the first timing and gate 34 of the timing delay 33. The decoder 32 receives the digital signal 21 and outputs a determination signal 321 , that is, when the decoder 32 determines that the digital signal 21 is the highest critical signal or the lowest critical signal, the determination signal 321 is output as 1, if not, Then output 0. The determination signal 321 is delayed by the timing delay unit 33 and output to the first timing and gate 34, and directly transmitted to the first timing and gate 34, and the determination signals 321 of the two timings are 1, to determine whether the analog signal 9 is greater than the highest value or less than the lowest value to determine whether the pulse width control unit 40 is to be activated for regulation. Further, the clock generator 35 and a second timing and gate 36 connected to the first timing and gate 34 and the clock generator 35 may be counted, thereby checking the judgment. The signal 321 is maintained for a period of time, and the pulse width control unit 40 can be activated to control after the digital signal 21 is determined to remain at the highest critical signal or the lowest critical signal for a period of time.

The pulse width control unit 40 is connected to the overvoltage detecting unit 30 and the pulse width adjusting unit 10, and outputs a control signal 41 to the pulse width adjusting unit by the judgment of the overvoltage detecting unit 30. 10. For example, when the pulse width control unit 40 receives the over-critical signal 31, a protection mechanism is performed. Please refer to "Figure 4" for the protection mechanism to control the value of an adjustment factor K. The adjustment factor K controls the pulse width of the pulse width adjustment unit 10, which will be described in detail later. The adjustment factor K is preset to 1, which means that 100% of the output signal is output without any modulation, and when the over-critical signal 31 is received, the pulse width control unit 40 first controls the adjustment factor K to lower the certain value. As shown in the figure, the sixth-order down-conversion is set to one-sixth. If the over-critical signal 31 is still received when the detection is performed, the adjustment factor K is decreased by one-sixth until The over-critical signal 31 was not received. It should be noted that if the adjustment factor K has been adjusted to 0, it is judged that the circuit is short-circuited or the circuit is faulty.

Referring to FIG. 5A , the pulse width adjusting unit 10 includes a first amplitude adjuster 12 and a second amplitude adjuster 13 that receive the analog signal 9 and is connected to the first amplitude adjuster 12 . The first pulse wave modulation unit 14 , a second pulse wave modulation unit 15 connected to the second amplitude adjuster 13 , a gate 16 , and a delay device 17 connected to the second pulse wave modulation unit 15 And a gate 18 connected to the AND gate 16 and the retarder 17, respectively. The first amplitude adjuster 12 receives the analog signal 9 and converts and outputs a first amplitude signal 121. In this embodiment, the first amplitude adjuster 12 is a signal amplifier (Amplifier), and the amplification ratio of the signal amplifier is In the invention, the adjustment factor K is multiplied by the analog signal 9 equal to the first amplitude signal 121, and the adjustment factor K of the first amplitude adjuster 12 is 1, indicating that the analog signal 9 is directly backward. Transmit, does not enlarge or reduce the amplitude. The first pulse modulation unit 14 is coupled to the first amplitude adjuster 12 to convert the first amplitude signal 121 into a first pulse modulation signal 141.

The second amplitude adjuster 13 is further connected to the pulse width control unit 40, and the adjustment factor K of the second amplitude adjuster 13 is controlled by the pulse width control unit 40, and the adjustment is controlled by the control signal 41. The factor K adjusts the amplitude of the analog signal 9 and outputs a second amplitude signal 131, and the adjustment factor is less than or equal to 1, the manner of adjustment has been described in the above paragraph, and the second pulse modulation unit 15 and the second The amplitude adjuster 13 is connected to convert the second amplitude signal 131 into a second pulse modulation signal 151. The sluice 16 is connected to the first pulse modulation unit 14 and the second pulse modulation unit 15 and receives the first pulse modulation signal 141 and the second pulse modulation signal 151. For the operation of the logic gate, please cooperate with the operation of the gate 16 in conjunction with the operation of the gate 16 to control the width of the first half of the pulse signal 11, that is, to control the amplitude of the positive half-cycle of the multi-level digital signal 51. And the connection through the delay device 17 and the gate 18 controls the width of the second half of the pulse signal 11, that is, controls the negative half-cycle amplitude of the multi-level digital signal 51, and therefore, by the second pulse The adjustment of the wave modulation signal 151 converts the original pulse wave signal 11 into the adjusted pulse wave signal 11a. The pulse signal 11 is sent to the multi-stage conversion unit 50 after the timing processing unit 20, and the digital signal is received and converted into a multi-level digital signal 51 output. If the pulse signal 11 is adjusted, the original multi-level digital signal 51 is converted into the adjusted multi-level digital signal 51a along with the adjusted pulse signal 11a, so as to avoid the voltage exceeding the critical value and being severe. Distortion or damage to the rear of the circuit.

Specifically, as shown in FIG. 2, the present invention further has a low-pass filtering unit 60 connected to the multi-stage converting unit 50 and an output unit 70 connected to the low-pass filtering unit 60 to receive the multi-step. The digital signal 51 is output. The feedback protection mechanism generated by the overvoltage detecting unit 30 is used to protect the output unit 70. The audio circuit is used as an example. The output unit 70 can be a speaker, a loudspeaker or a speaker.

Please refer to "Figure 6", where the cutting ratio represents the difference between the output voltage and the threshold voltage set by the circuit. In addition to the upper threshold voltage, the larger the cutting rate, the output voltage and the threshold voltage. The difference is greater. Referring to FIG. 7 , when an output waveform 94 exceeds the threshold value Vo, the second region 92 is set. The first region 91 and the third region 93 are regions where the output waveform 94a does not exceed the threshold value Vo. And the cutting weight represents the weight ratio of the output voltage beyond the threshold voltage in the overall output including the time and the voltage magnitude, that is, the second region 92 is integral (the first region 91 + the second region) The proportion of 92+ third area 93), the ratio should be as small as possible. Therefore, as shown in "Fig. 6", the protection mechanism curve 83 obtained by the circuit architecture of the present invention is cut as compared with the hard cutting curve 81 which avoids voltage overload by hard cutting and the soft cutting curve 82 by soft cutting mode. The weighting performance is far superior to the hard cutting curve 81 and the soft cutting curve 82, thereby demonstrating that the mode of the present invention can effectively reduce the weight ratio of the actual output voltage beyond the threshold voltage. The square of the weight ratio is proportional to the heat generation rate. Please cooperate with the figure shown in Figure 8. The heat generated by the protection mechanism curve 83a obtained by the circuit architecture of the present invention is much lower than the hard cutting curve 81a and the soft cutting curve. 82a, it can also be inferred that the architecture of the present invention can reduce the loss of thermal energy conversion due to the output voltage exceeding the threshold voltage, that is, the method of reducing the power loss to reduce the heat generation of the overall circuit.

In summary, the present invention utilizes the overvoltage detecting unit 30 to capture the digital signal 21 of the timing processing unit 20, and forms a feedback through the connection between the pulse width control unit 40 and the pulse width adjusting unit 10. In order to adjust the output voltage, to avoid the output voltage signal is too high and there is a problem of burning the rear to accept the circuit. Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

Conventional technology

1. . . Modulation circuit

2. . . amplifying circuit

3. . . Low pass filter

4. . . loudspeaker

5. . . Input audio signal

6. . . Second-order voltage signal

7. . . Signal distortion

8. . . Multi-value output conversion signal

this invention

9. . . Analog signal

10. . . Pulse width adjustment unit

11. . . Pulse signal

11a. . . Adjusted pulse wave signal

12. . . First amplitude adjuster

121. . . First amplitude signal

13. . . Second amplitude adjuster

131. . . Second amplitude signal

14. . . First pulse modulation unit

141. . . First pulse modulation signal

15. . . Second pulse modulation unit

151. . . Second pulse modulation signal

16. . . Gate

17. . . Delayer

18. . . Gate

20. . . Timing processing unit

twenty one. . . Digital signal

30. . . Overvoltage detection unit

31. . . Over-critical signal

32. . . decoder

321. . . Judgment signal

33. . . Timing delay

34. . . First timing and gate

35. . . Clock generator

36. . . Second timing and gate

40. . . Pulse width control unit

41. . . Control signal

50. . . Multi-level conversion unit

51. . . Multi-order digital signal

52a. . . Adjusted multi-order digital signal

60. . . Low pass filter unit

70. . . Output unit

81, 81a. . . Hard cutting curve

82, 82a. . . Soft cutting curve

83, 83a. . . Protection mechanism curve

91. . . First area

92. . . Second area

93. . . Third area

94, 94a. . . Output waveform

FIG. 1 is a schematic diagram of a circuit structure of a prior art.

FIG. 2 is a schematic diagram of a unit configuration according to a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of a circuit of an overvoltage detecting unit according to a preferred embodiment of the present invention.

4 is a schematic diagram of a pulse width control mechanism according to a preferred embodiment of the present invention.

Fig. 5A is a block diagram showing the configuration of a pulse width adjusting unit according to a preferred embodiment of the present invention.

Figure 5B is a schematic illustration of pulse width and transition waveforms in accordance with a preferred embodiment of the present invention.

Figure 6 is a schematic illustration of the percentage of cutting weights in accordance with a preferred embodiment of the present invention.

FIG. 7 is a schematic diagram of an overload region according to a preferred embodiment of the present invention.

FIG. 8 is a schematic diagram of heat generation rate according to a preferred embodiment of the present invention.

9. . . Analog signal

10. . . Pulse width adjustment unit

11. . . Pulse signal

20. . . Timing processing unit

twenty one. . . Digital signal

30. . . Overvoltage detection unit

31. . . Over-critical signal

40. . . Pulse width control unit

41. . . Control signal

50. . . Multi-level conversion unit

51. . . Multi-order digital signal

60. . . Low pass filter unit

70. . . Output unit

Claims (8)

A signal converter with an overvoltage protection mechanism, comprising:
a pulse width adjusting unit converts a type of analog signal into a pulse signal, and the width of the pulse signal is modulated according to the magnitude of the analog signal;
a timing processing unit connected to the pulse width adjusting unit receives the pulse signal and converts it into a digital signal;
An overvoltage detecting unit connected to the timing processing unit, when receiving the digital signal and determining that the digital signal is a highest critical signal or a lowest critical signal, outputting a critical signal;
a pulse width control unit is respectively connected to the overvoltage detecting unit and the pulse width adjusting unit, and outputs a control signal to the pulse width adjusting unit by the judgment of the overvoltage detecting unit; and another The multi-level conversion unit connected to the timing processing unit receives the digital signal conversion and converts it into a multi-level digital signal output. The signal converter with an overvoltage protection mechanism as described in claim 1, wherein the overvoltage detection unit comprises:
a decoder connected to the timing processing unit, receiving the digital signal and outputting a determination signal;
a timing delay device connected to the decoder, receiving the determination signal and delaying output;
A first timing and a gate connected to the decoder and the timing delayer respectively receive the determination signal and the delayed determination signal. The signal converter having an overvoltage protection mechanism as described in claim 2, wherein the decoder outputs the determination signal to 1 when determining that the digital signal is the highest critical signal or the lowest critical signal, if not The output is 0. The signal converter with an overvoltage protection mechanism as described in claim 3, wherein the overvoltage detecting unit further has a clock generator, and a first timing and gate connected to the clock generator The second sequence and the gate, thereby checking the length of time that the determination signal is maintained at 1. The signal converter with an overvoltage protection mechanism as described in claim 1, wherein the pulse width adjusting unit comprises:
a first amplitude adjuster that receives the analog signal, and receives the analog signal to convert and output a first amplitude signal;
a second amplitude adjuster receiving the analog signal is connected to the pulse width control unit, and the control signal controls an adjustment factor to adjust the amplitude of the analog signal and output a second amplitude signal, and the adjustment factor is multiplied by the The analog signal is equal to the second amplitude signal, and the adjustment factor is less than or equal to 1;
a first pulse wave modulation unit connected to the first amplitude adjuster, converting the first amplitude signal into a first pulse width modulation signal;
a second pulse modulation unit connected to the second amplitude adjuster, converting the second amplitude signal into a second pulse width modulation signal;
a gate and a first pulse wave modulation unit and the second pulse wave modulation unit;
a delay connected to the second pulse modulation unit to delay the second pulse width modulation signal; and a OR gate connected to the AND gate and the delay. The signal converter with the overvoltage protection mechanism described in claim 5, wherein the adjustment factor of the first amplitude adjuster is equal to 1, and the analog signal is directly output, and the first amplitude adjuster and the first The two amplitude adjusters are signal amplifiers. The signal converter with an overvoltage protection mechanism according to claim 1, wherein there is further provided a low pass filtering unit connected to the multi-stage converting unit and an output unit connected to the low-pass filtering unit, Receiving the multi-level digital signal. A signal converter having an overvoltage protection mechanism as described in claim 7 wherein the output unit is selected from the group consisting of a horn, a loudspeaker and a speaker.