JP2013223202A - Pulse width modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse width modulation circuit that suppresses noise and a zero crossing distortion, and reduces pop noise by suppressing the generation of a DC offset.SOLUTION: The pulse width modulation circuit includes: a first PWM circuit 3 for pulse-width-modulating a first audio signal to output a first PWM signal; a second pulse PWM circuit 4 for pulse-width-modulating a second audio signal opposite in phase to the first audio signal to output a second pulse PWM signal; a first half bridge 5 for amplifying the first pulse PWM signal; a second half bridge 6 for amplifying the second PWM signal; and delay control circuits 7A, 7B for changing a delay time between the first PWM signal and the second PWM signal by the same delay at every one of leading and trailing edges of the first and second PWM signals until the delay time reaches a set delay time set beforehand.

Description

  The present invention relates to a pulse width modulation circuit, and in particular, an audio signal input to two pulse width modulation circuits is in reverse phase, and both ends of a load are connected between the outputs of the two pulse width modulation circuits. The present invention relates to a class D amplifier having a (transformer-less) configuration.

  BTL class D amplifiers have been used in in-car audio equipment and the like in recent years because of their very high power amplification efficiency.

  This class D amplifier includes two half bridges in order to amplify the pulse outputs of the two pulse width modulation circuits, respectively. Each half bridge is composed of two switching elements that are complementarily turned on and off. When the level of the audio signal input to the class D amplifier is close to a zero value, the pulse edges of the pulse outputs of the two pulse width modulation circuits match or approach each other. Then, switching currents flow through the two half bridges at the same time, and there is a problem that noise and zero cross distortion occur due to the mutual interference.

  In Patent Document 1, in order to suppress such noise and zero cross distortion, when the level of the audio signal is close to zero, one of the pulses output from the two pulse width modulation circuits is changed with respect to the other. A BTL class D amplifier with a delay is disclosed.

JP-T-2002-521949

  However, the BTL class D amplifier described in Patent Document 1 merely generates a delay between pulses output from two pulse width modulation circuits. For this reason, according to the class D amplifier, although noise and zero cross distortion are suppressed, a DC offset is generated in the output at the instant when a delay is added, which becomes pop noise and causes a problem in sound quality.

  Accordingly, an object of the present invention is to reduce the pop noise by suppressing the occurrence of the DC offset in such a class D amplifier.

A pulse width modulation circuit according to the present invention includes a first pulse width modulation circuit that performs pulse width modulation on a first audio signal and outputs a first pulse width modulation signal; A second pulse width modulation circuit that performs pulse width modulation on the second audio signal and outputs a second pulse width modulation signal; a first half bridge that amplifies the first pulse width modulation signal; Until the delay time between one pulse width modulation signal and the second pulse width modulation signal reaches a preset delay time, the rise time of the first and second pulse width modulation signals And a delay control circuit that changes the delay amount by the same amount at each falling.

  According to the pulse width modulation circuit of the present invention, it is possible to reduce noise and zero-cross distortion and to reduce pop noise by suppressing the occurrence of DC offset.

It is a circuit diagram of a pulse width modulation circuit in an embodiment of the present invention. FIG. 3 is a circuit diagram of a first delay control circuit. It is a wave form diagram explaining operation | movement of the pulse width modulation circuit in embodiment of this invention. It is a wave form diagram explaining operation | movement of the pulse width modulation circuit in embodiment of this invention. It is a wave form diagram explaining operation | movement of the conventional pulse width modulation circuit. It is a wave form diagram explaining operation | movement of the conventional pulse width modulation circuit.

  FIG. 1 is a circuit diagram of a pulse width modulation circuit according to an embodiment of the present invention. As shown in the figure, this pulse width modulation circuit is a BTL class D amplifier, and includes a signal source 1, an inverting circuit 2, a first pulse width modulation circuit 3 (hereinafter referred to as a first PWM circuit 3), 2 pulse width modulation circuit 4 (hereinafter referred to as second PWM circuit 4), first half bridge 5, second half bridge 6, first delay control circuit 7A, and second delay control circuit 7B. Consists of including.

  The signal source 1 is a signal source that generates a digital audio signal. The inverting circuit 2 inverts the level of the audio signal generated from the signal source 1 (hereinafter referred to as the first audio signal) to generate a second audio signal having a reverse phase. That is, the first audio signal and the second audio signal are 180 ° out of phase with each other.

  The first PWM circuit 3 performs pulse width modulation on the first audio signal and outputs a first pulse width modulation signal (hereinafter referred to as a first PWM signal). The second PWM circuit 4 performs pulse width modulation on the second audio signal and outputs a second pulse width modulation signal (hereinafter referred to as a second PWM signal).

  The first PWM circuit 3 includes a binary counter (binary counter) 8, a first triangular wave carrier generation circuit 9 A that generates a digital first triangular wave carrier based on the count value of the binary counter 8, A first comparator 10A that compares one audio signal with a first triangular wave carrier. The output of the first comparator 10A becomes L level when the first audio signal is smaller than the first triangular wave carrier, and becomes H level when the first audio signal is larger than the first triangular wave carrier. The output of the first comparator 10A is the first PWM signal. The count value of the binary counter 8 is reset at a constant period, and the count output is a digital ramp wave.

  Similarly, the second PWM circuit 4 includes a binary counter 8, a second triangular wave carrier generation circuit 9B that generates a digital second triangular wave carrier based on the count value of the binary counter 8, and a second audio. A second comparator 10B that compares the signal and the second triangular wave carrier. The output of the second comparator 10B is the first PWM signal. The binary counter 8 is used in the first and second PWM circuits 3 and 4.

  The first half bridge 5 is composed of a pulse amplifier (power amplifier) that amplifies the first PWM signal. Specifically, the first half bridge 5 includes a PMOS power transistor MP1 and an NMOS power transistor MN1 connected in series between a voltage source (VDD) and the ground, for example. The first PWM signal is applied to the gates of the PMOS power transistor MP1 and the NMOS power transistor MN1.

  Similarly, the second half bridge 6 includes a pulse amplifier that amplifies the second PWM signal. Similarly, the second half bridge 5 can be composed of a PMOS power transistor MP2 and an NMOS power transistor MN2 connected in series between the voltage source (VDD) and the ground. The second PWM signal is applied to the gates of the PMOS power transistor MP2 and the NMOS power transistor MN2.

  The both ends of the load (speaker) 11 are connected between the outputs of the first half bridge 5 and the second half bridge 6. The load 11 is a coil or a resistor on the equivalent circuit. In order to remove high-frequency noise, the outputs of the first half bridge 5 and the second half bridge 6 may be supplied to the load 11 via low-pass filters, respectively. .

  The first delay control circuit 7A or the delay control circuit 7B sets the delay time until the delay time between the first PWM signal and the second PWM signal reaches a preset set delay time. In addition, the same delay amount is changed every time the second pulse PWM signal rises and falls. As a result, it is possible to suppress noise and zero-crossing distortion of a BTL class D amplifier and to suppress pop noise by suppressing occurrence of a DC offset.

  In order to implement such a function, the first delay control circuit 7A sets the first counter value to the count value of the binary counter 8 every time the first triangular wave carrier reaches the peak of the maximum value and the minimum value of the triangular wave. Add values (eg, -1, 0, +1). Thereby, the delay of the first triangular wave carrier can be controlled, and as a result, the delay of the first PWM signal can be controlled as described above. The same applies to the second delay control circuit 7B.

  FIG. 2 is a diagram illustrating a specific circuit example of the first delay control circuit 7A. The same applies to the second delay control circuit 7B.

  As illustrated, the first delay control circuit 7 </ b> A includes a peak detection circuit 12, a register 13, a first addition circuit 14, a comparator 15, and a second addition circuit 16. The level of the first triangular wave carrier from the first triangular wave generating circuit 9A is linearly increased and decreased to form a triangular wave. The peak detection circuit 12 detects the peak of the maximum value and the minimum value of the first triangular wave carrier and outputs a detection pulse.

  The first addition circuit 14 adds the output of the register 13 and the count value of the binary counter 8. The comparator 15 compares the second value (for example, −4 or +4) according to the set delay time with the output of the register 13 and the first value until just before the output of the register 13 reaches the second value. A value (for example, -1, +1) is output. For example, assuming that the second value is “−4”, the comparator 15 outputs “−1” until the output of the register 13 reaches “−4”, and the output of the register 13 is “−”. After reaching “4”, “0” is output unless the second value is changed thereafter.

  The second adder circuit 16 adds the first value from the comparator 15 and the output of the register 13. The register 13 is configured to receive and hold the output of the second addition circuit 16 in accordance with the detection pulse of the peak detection circuit 12.

  The second value corresponding to the set delay time can be input to the comparator 15 via the CPU interface 17.

  Next, the operation of the pulse width modulation circuit in the embodiment of the present invention will be described based on the waveform diagrams of FIGS. In this case, the first delay control circuit 7A performs delay control, but the second delay control circuit 7B does not perform delay control. The second value corresponding to the set delay time in the first delay control circuit 7A is set to “−4”, and the second value corresponding to the set delay time in the first delay control circuit 7A is “0”. "Is set. Further, it is assumed that the first audio signal from the signal source and the inverted second audio signal have a value of zero.

  The output A of the binary counter 8 is a ramp waveform that is reset to zero at a constant period. Initially, the output B of the first delay control circuit 7A is “0”. In this state, the output A of the binary counter 8 increases from a zero value. Then, the level of the first triangular wave carrier D also increases. In this ascending process, the waveform of the first triangular wave carrier D is the same as that of the second triangular wave carrier Dn.

  When the level of the first triangular wave carrier D exceeds the level of the first audio signal E, the first PWM signal F changes from the H level to the L level. Further, when the level of the second triangular wave carrier Dn exceeds the level of the second audio signal En, the second PWM signal G changes from the H level to the L level. At this time, the falling pulse edges of the first PWM signal F and the second PWM signal G coincide with each other.

  Thereafter, the first triangular wave carrier D and the second triangular wave carrier Dn further rise to reach the maximum value peak. At this time, since the output of the comparator 15 of the first delay control circuit 7A is “−1”, “−1” is captured and held in the register 13 in accordance with the peak detection signal of the peak detection circuit 12. . As a result, the output B of the first delay control circuit 7A becomes “−1”.

  “−1” output from the first delay control circuit 7 A is added to the count value of the binary counter 8. As a result, the count value of the binary counter 8 is decreased by “1”.

  Next, when the output A of the binary counter 8 further increases from the intermediate value, the level of the first triangular wave carrier D starts to decrease, but the waveform of the first triangular wave carrier D has a time corresponding to the count value “1” ( For example, it descends with a delay of 10 nanoseconds (= 10 ns). On the other hand, there is no delay in the waveform of the second triangular wave carrier Dn. In FIG. 3, a first triangular wave carrier D indicated by a dotted line represents a waveform when there is no delay, and a first triangular wave carrier D indicated by a solid line represents a delayed waveform.

  When the level of the first triangular wave carrier D falls below the level of the first audio signal E, the first PWM signal F changes from the L level to the H level. Further, when the level of the second triangular wave carrier Dn falls below the level of the second audio signal En, the second PWM signal G changes from the L level to the H level.

  In this case, the rising edge of the first PWM signal F is delayed from the rising edge of the second PWM signal G by a delay amount (10 nanoseconds) corresponding to the count value “1”.

  Thereafter, the level of the first triangular wave carrier D further decreases and reaches the minimum peak. At this time, since the output of the comparator 15 of the first delay control circuit 7A is “−1” and “−1” is held in the register 13, the second adder circuit 16 sets these two values. Is added. “−2” which is the addition output of the second addition circuit 16 is held in the register 13 in accordance with the peak detection signal. As a result, the output B of the first delay control circuit 7A becomes “−2”.

  “−2” output from the first delay control circuit 7 A is added to the count value of the binary counter 8. As a result, the count value of the binary counter 8 is decreased by “2”. When the binary counter 8 is reset, the first triangular wave carrier D rises again, but the first triangular wave carrier D rises with a delay corresponding to the count value “2”. On the other hand, there is no delay of the second triangular wave carrier Dn.

  When the level of the first triangular wave carrier D exceeds the level of the first audio signal E, the first PWM signal F changes from the H level to the L level. Further, when the level of the second triangular wave carrier Dn exceeds the level of the second audio signal En, the second PWM signal G changes from the H level to the L level.

  At this time, the fall of the first PWM signal F is delayed from the fall of the second PWM signal G by a delay amount (20 nanoseconds) corresponding to the count value “2” of the binary counter 8. Become.

  Thereafter, the first triangular wave carrier D further rises and reaches the maximum peak again. At this time, since the output of the comparator 15 of the first delay control circuit 7A is “−1” and “−2” is held in the register 13, these two values are set by the second adder circuit 16. Is added. “−3” which is the addition output of the second addition circuit 16 is held in the register 13 in accordance with the peak detection signal. As a result, the output B of the first delay control circuit 7A becomes “−3”.

  “−3” output from the first delay control circuit 7 A is added to the count value of the binary counter 8. As a result, the count value of the binary counter 8 is decreased by “3”.

  Next, when the output A of the binary counter 8 further increases from the intermediate value, the level of the first triangular wave carrier D starts to decrease, but the waveform of the first triangular wave carrier D has a time corresponding to the count value “3” ( It descends with a delay of 30 nanoseconds). On the other hand, there is no delay in the waveform of the second triangular wave carrier Dn.

  When the level of the first triangular wave carrier D falls below the level of the first audio signal E, the first PWM signal F changes from the L level to the H level. Further, when the level of the second triangular wave carrier Dn falls below the level of the second audio signal En, the second PWM signal G changes from the L level to the H level.

  At this time, the rising edge of the first PWM signal F is delayed from the rising edge of the second PWM signal G by a delay amount (30 nanoseconds) corresponding to the count value “3”.

  Thereafter, by the same operation, the fall of the next first PWM signal F is delayed from the fall of the second PWM signal G by a delay amount (40 nanoseconds) corresponding to the count value “4”. The In this case, since the output B (output of the register 13) of the first delay control circuit 7A is “−4”, the output of the comparator 15 of the first delay control circuit 7A is “0” as described above. . Then, the output B of the first delay control circuit 7A (the output of the register 13) maintains “−4”. Therefore, the first PWM signal F continues to be delayed with respect to the second PWM signal G by a certain delay amount (40 nanoseconds).

  As described above, the delay time between the first PWM signal F and the second PWM signal G reaches the preset delay time (40 nanoseconds) until the delay time reaches the preset delay time (40 nanoseconds). The same delay amount (10 nanoseconds) can be increased every time the pulse PWM signal rises and falls.

  FIG. 4 shows the first PWM signal F, the second PWM signal G, the output H of the first half bridge 5, the output I of the second half bridge 6, and the output voltage VBTL. The output H of the first half bridge 5 is a signal obtained by inverting the first PWM signal F, and the output I of the second half bridge 6 is a signal obtained by inverting the second PWM signal G. The output voltage VBTL is a voltage applied to both ends of the load 11 and is a value (voltage) obtained by subtracting the output I of the second half bridge 6 from the output H of the first half bridge 5.

  Therefore, the output H of the first half bridge 5 is 0 nanoseconds → 10 nanoseconds → 20 nanoseconds → 30 nanoseconds → 40 at every rising and falling with respect to the output I of the second half bridge 6. Delay by the same delay amount (10 nanoseconds), such as nanoseconds. When the delay time reaches 40 nanoseconds, the delay time of both of them maintains 40 nanoseconds for both the rising and falling edges of the pulse.

  Thereby, according to this embodiment, two effects are acquired. First, the switching current flows through the first half bridge 5 and the second second half bridge 6 simultaneously by shifting the pulse edges of the first PWM signal F and the second PWM signal G to each other. Is to prevent noise and zero cross distortion.

  The second effect is a unique effect that is not found in Patent Document 1, and is that generation of a DC offset of the output voltage VBTL is suppressed and pop noise is reduced. This is because, as shown in FIG. 4, the output voltage VBTL changes symmetrically with respect to the DC center voltage so as to cancel the DC bias.

  That is, when both the first and second PWM signals F and G are at the L level, the PMOS power transistor MP1 of the first half bridge 5 and the PMOS power transistor MP2 of the second half bridge 6 are turned on. . From this state, when the second PWM signal G rises to the H level, the PMOS power transistor MP2 of the second half bridge 6 is turned off and the NMOS power transistor MN2 is turned on. As a result, the output voltage VBTL increases. Thereafter, when the first PWM signal F rises to the H level with a delay of 10 nanoseconds, the PMOS power transistor MP1 of the first half bridge 5 is turned off and the NMOS power transistor MN1 is turned on. Thereby, the level of the output voltage VBTL becomes flat.

  Thereafter, when the second PWM signal G falls to the L level, the PMOS power transistor MP2 of the second half bridge 6 is turned on and the NMOS power transistor MN2 is turned off. As a result, the output voltage VBTL decreases and its polarity is reversed with respect to the DC center voltage. Thereafter, when the first PWM signal F rises to the L level with a delay of 20 nanoseconds, the PMOS power transistor MP1 of the first half bridge 5 is turned on and the NMOS power transistor MN1 is turned off. Thereby, the level of the output voltage VBTL becomes flat. By repeating such an operation, the DC center voltage of the output voltage VBTL becomes constant when viewed on average, and the occurrence of DC offset is suppressed.

  Further, after the delay time of the first PWM signal F with respect to the second PWM signal G reaches 40 nanoseconds, the second value corresponding to the set delay time in the first delay control circuit 7A is set to “0”. By changing to, the output of the comparator 15 changes to “+1”. As a result, the delay time decreases at each rise and fall, such as 40 nanoseconds → 30 nanoseconds → 20 nanoseconds → 10 nanoseconds → 0 nanoseconds.

  On the other hand, as shown in FIG. 5, in the method of changing the delay time between the first PWM signal and the second PWM signal at once, a DC offset occurs in the output voltage VBTL. In addition, as shown in FIG. 6, a DC offset is generated in the output voltage VBTL even when the same delay amount (for example, 10 nanoseconds) is shifted and shifted at both edges of the first PWM signal and the second PWM signal. End up.

  In the pulse width modulation circuit of the present embodiment, the first delay control circuit 7A and the second delay control circuit 7B are provided as the delay control circuit, but only one of them may be provided. In the pulse width modulation circuit of this embodiment, each component circuit is configured by a digital circuit. However, each component circuit may be configured by an analog circuit, and an analog audio signal may be input.

  Further, the PMOS power transistor MP1 and the NMOS power transistor in the first half bridge 5 may be used. Similarly, the PMOS power transistor MP2 and the NMOS power transistor in the second half bridge 6 may be used.

DESCRIPTION OF SYMBOLS 1 Signal source 1 2 Inversion circuit 3 1st PWM circuit 4 2nd PWM circuit 4 5 1st half bridge 6 2nd half bridge 7A 1st delay control circuit 7B 2nd delay control circuit 8 Binary counter 9A First triangular wave carrier generation circuit 10A First comparator 9B Second triangular wave carrier generation circuit 10B Second comparator 11 Load 12 Peak detection circuit 13 Register 14 First addition circuit 15 Comparator 16 Second addition circuit

Claims (5)

A first pulse width modulation circuit that performs pulse width modulation on the first audio signal and outputs a first pulse width modulation signal;
A second pulse width modulation circuit that performs pulse width modulation on a second audio signal having a phase opposite to that of the first audio signal and outputs a second pulse width modulation signal;
A first half bridge for amplifying the first pulse width modulated signal;
A second half bridge for amplifying the second pulse width modulated signal;
Until the delay time between the first pulse width modulation signal and the second pulse width modulation signal reaches a preset delay time, the delay time is set to the first and second pulse width modulation signals. A pulse width modulation circuit comprising: a delay control circuit that changes the delay amount by the same delay amount at each rising edge and falling edge. The first or second pulse width modulation circuit includes a counter that outputs a count value so as to be reset at a constant period, a triangular wave carrier generation circuit that generates a triangular wave carrier based on the count value, and the first A first comparator for comparing an audio signal and the triangular wave carrier;
The delay control circuit is provided corresponding to the first pulse width modulation circuit or the second pulse width modulation circuit, and each time the triangular wave carrier reaches its upper limit and lower limit peaks, 2. The pulse width modulation circuit according to claim 1, wherein a value of 1 is added.   The delay control circuit includes: a peak detection circuit that detects a peak of the triangular wave carrier and outputs a detection pulse; a register; a first addition circuit that adds an output of the register and a count value of the counter; A second comparator that compares a second value corresponding to a set delay time with the output of the register and outputs the first value until immediately before the output of the register reaches the second value; And a second adder circuit that adds the value of 1 and the output of the register, wherein the register receives and holds the output of the second adder circuit in response to the detection pulse. Item 3. The pulse width modulation circuit according to Item 2.   4. The pulse width modulation circuit according to claim 2, wherein the delay control circuit is provided corresponding to both the first pulse width modulation circuit and the second pulse width modulation circuit.   4. The pulse width modulation circuit according to claim 2, wherein the second value is input to the second comparator via a CPU interface. 5.

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