TWI448166B - Device for reducing pop noise - Google Patents
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Description
本發明係關於一種用於降低氣爆雜音的信號處理裝置。The present invention relates to a signal processing apparatus for reducing gas explosion noise.
傳統音源訊號放大器可分類為A類、B類、AB類和D類放大器以放大音源訊號。在這些放大器中A類、B類和AB類放大器由於功率轉換效率不佳，所以在高功率輸出時需依靠大型或高效率之散熱器進行散熱，進而增加使用成本和體積。Traditional audio source amplifiers can be classified into Class A, Class B, Class AB, and Class D amplifiers to amplify the source signal. Class A, Class B, and Class AB amplifiers in these amplifiers rely on large or high-efficiency heat sinks for heat dissipation at high power output due to poor power conversion efficiency, which increases cost and size.
近年來，D類放大器由於具有較佳的功率轉換特性和線性度等優點，已逐漸成為音源訊號放大器的主流。D類放大器可用來處理類比輸入音源訊號和數位輸入音源訊號。圖1顯示一習知處理數位輸入音源訊號的D類放大器10之方塊示意圖。參考圖1，該D類放大器10包含一脈寬調變器12、一功率放大器14以及一低通濾波器16。In recent years, Class D amplifiers have gradually become the mainstream of audio signal amplifiers due to their superior power conversion characteristics and linearity. Class D amplifiers can be used to process analog input source signals and digital input source signals. 1 shows a block diagram of a conventional class D amplifier 10 that processes digital input tone signals. Referring to FIG. 1, the class D amplifier 10 includes a pulse width modulator 12, a power amplifier 14, and a low pass filter 16.
該脈寬調變器12在接收一數位音頻訊號後，輸出一脈寬調變訊號PWM至該功率放大器14。接著，該功率放大器14放大該脈寬調變訊號PWM。放大的訊號再經由該低通濾波器16轉換成一類比訊號後，透過一耳機或是喇叭等聲頻輸出裝置18產生聲音。The pulse width modulator 12 outputs a pulse width modulated signal PWM to the power amplifier 14 after receiving a digital audio signal. Then, the power amplifier 14 amplifies the pulse width modulation signal PWM. After the amplified signal is converted into an analog signal by the low pass filter 16, the sound is generated through an audio output device 18 such as a headphone or a speaker.
然而，該脈衝寬度調變訊號PWM在初始產生或結束時，例如在剛開機或突然關機的狀況下，會形成一氣爆雜音(pop noise)。該氣爆雜音會對使用者產生聽覺上的不適應， 因而影響其收聽品質。However, the pulse width modulation signal PWM generates a pop noise at the initial generation or the end, for example, just after the power is turned on or suddenly turned off. The gas blast will cause an audible incompatibility to the user. This affects the quality of its listening.
因此，有必要提供一種用來降低氣爆雜音的裝置以解決上述問題。Therefore, it is necessary to provide a device for reducing gas explosion noise to solve the above problem.
本發明提供一種用於減少氣爆雜音的裝置，包含：一充電電路、一比較電路、一時序控制電路以及一時序產生電路。該時序控制電路用以接收一靜音訊號和一脈衝寬度調變訊號以產生一第一相位訊號和一第二相位訊號。該充電電路用以接收該第一相位訊號和該第二相位訊號以產生一第一電壓和一第二電壓。該比較電路用以比較該第一電壓和該第二電壓以產生一偵測訊號。該時序產生電路用以接收該靜音訊號、該脈衝寬度調變訊號和該偵測訊號以產生一具有多個脈衝之輸出訊號，該輸出訊號之第一脈衝之寬度小於該脈衝寬度調變訊號之每一脈衝之寬度。The invention provides an apparatus for reducing gas explosion noise, comprising: a charging circuit, a comparison circuit, a timing control circuit and a timing generating circuit. The timing control circuit is configured to receive a mute signal and a pulse width modulation signal to generate a first phase signal and a second phase signal. The charging circuit is configured to receive the first phase signal and the second phase signal to generate a first voltage and a second voltage. The comparison circuit is configured to compare the first voltage and the second voltage to generate a detection signal. The timing generating circuit is configured to receive the mute signal, the pulse width modulation signal and the detection signal to generate an output signal having a plurality of pulses, wherein a width of the first pulse of the output signal is smaller than the pulse width modulation signal The width of each pulse.
圖2顯示本發明一實施例之一種用於降低氣爆雜音的裝置200之方塊示意圖。參考圖2，該用於減少氣爆雜音的裝置200包含一充電電路20、一比較電路模組30、一時序控制電路模組50和一時序產生電路模組70。2 shows a block diagram of an apparatus 200 for reducing gas blast noise in accordance with an embodiment of the present invention. Referring to FIG. 2, the apparatus 200 for reducing gas explosion noise includes a charging circuit 20, a comparison circuit module 30, a timing control circuit module 50, and a timing generation circuit module 70.
該充電電路20包含電流源I1 和I2 、複數個開關21~24以及電容C1 和C2 。該比較電路模組30包含一比較器31。該時序控制電路模組50包含一時序控制電路51。該時序產生電路模組70包含一時序產生電路71。The charging circuit 20 includes current sources I 1 and I 2 , a plurality of switches 21-24, and capacitors C 1 and C 2 . The comparison circuit module 30 includes a comparator 31. The timing control circuit module 50 includes a timing control circuit 51. The timing generation circuit module 70 includes a timing generation circuit 71.
參考圖2，該充電電路20利用該電流源I1 經由該開關21對該電容C1 進行充電，藉以產生一電壓V1 ，其中該開關21係由一相位訊號PH1 所控制。該充電電路20利用該電流源I2 經由該開關23對該電容22進行充電，藉以產生一電壓V2 ，其中該開關23係由一相位訊號PH2 所控制。該比較器31在比較該電壓V1 和該電壓V2 的電壓位準後，產生一偵測訊號HP_DET。Referring to Figure 2, the charging circuit 20 by using the current source I 1 through the switch 21 to charge the capacitor C 1, so as to generate a voltage V 1, wherein the line switch 21 controlled by a phase signal PH 1. The charging circuit 20 uses the current source I 2 to charge the capacitor 22 via the switch 23 to generate a voltage V 2 , wherein the switch 23 is controlled by a phase signal PH 2 . The comparator 31 generates a detection signal HP_DET after comparing the voltage levels of the voltage V 1 and the voltage V 2 .
參考圖2，該時序控制電路模組50中的該時序控制電路51用以接收一靜音訊號MUTE和一脈衝寬度調變訊號PWM以產生複數個相位訊號PH1 、/PH1 、PH2 、/PH2 ，其中相位訊號PH1 和/PH1 為互補訊號，且相位訊號PH2 和/PH2 為互補訊號。該些相位訊號會送至該充電電路20，藉以控制開關21~24以產生該電壓V1 和該電壓V2 。Referring to FIG. 2, the timing control circuit 51 of the timing control circuit module 50 is configured to receive a mute signal MUTE and a pulse width modulation signal PWM to generate a plurality of phase signals PH 1 , /PH 1 , PH 2 , and / PH 2 , wherein the phase signals PH 1 and /PH 1 are complementary signals, and the phase signals PH 2 and /PH 2 are complementary signals. The plurality of phase signals will be supplied to the charging circuit 20, thereby controlling the switches 21 to 24 to generate the voltage V 1 is and the voltage V 2.
該時序產生電路模組70中的該時序產生電路71用以接收該靜音訊號MUTE、該脈衝寬度調變訊號PWM和該偵測訊號HP_DET以產生一輸出訊號PWM_HP。該輸出訊號PWM_HP具有多個脈衝，其第一個脈衝為一部分寬度脈衝。詳言之，在本發明之一實施例中，該輸出訊號PWM_HP之第一脈衝之寬度會小於其第二脈衝之寬度。藉由該部分寬度脈衝訊號，該裝置200可以減少氣爆雜音。The timing generating circuit 71 of the timing generating circuit module 70 is configured to receive the mute signal MUTE, the pulse width modulation signal PWM and the detection signal HP_DET to generate an output signal PWM_HP. The output signal PWM_HP has a plurality of pulses, the first pulse of which is a partial width pulse. In detail, in an embodiment of the invention, the width of the first pulse of the output signal PWM_HP is less than the width of the second pulse. With the partial width pulse signal, the device 200 can reduce the gas explosion noise.
圖3顯示本發明一實施例之該時序控制電路51運作時之時序圖。參考圖3，在本實施例中，輸入的該脈衝寬度調變訊號PWM為具有多個連續脈衝的訊號，且每一脈衝之寬 度為0.5＊ T(T為該訊號之週期)。當該靜音訊號MUTE由低邏輯位準轉態為高邏輯位準時，該時序控制電路51會產生該些相位訊號PH1 、/PH1 、PH2 和/PH2 ，其中該相位訊號PH1 對應該訊號PWM在該靜音訊號MUTE轉態後的第一個脈衝，而該相位訊號PH2 對應該訊號PWM在該靜音訊號MUTE轉態後的第二個脈衝。另一方面，當該靜音訊號MUTE由高邏輯位準轉態為低邏輯位準時，該時序控制電路51會更新該些相位訊號PH1 、/PH1 、PH2 和/PH2 ，其中該相位訊號PH1 對應該訊號PWM在該靜音訊號MUTE轉態後的第一個脈衝，而該相位訊號PH2 對應該訊號PWM在該靜音訊號MUTE轉態後的第二個脈衝。FIG. 3 is a timing chart showing the operation of the timing control circuit 51 in accordance with an embodiment of the present invention. Referring to FIG. 3, in the embodiment, the input pulse width modulation signal PWM is a signal having a plurality of consecutive pulses, and each pulse has a width of 0.5 * T (T is a period of the signal). When the mute signal MUTE is changed from a low logic level to a high logic level, the timing control circuit 51 generates the phase signals PH 1 , /PH 1 , PH 2 and /PH 2 , wherein the phase signal PH 1 is The signal PWM should be the first pulse after the mute signal MUTE transition state, and the phase signal PH 2 corresponds to the second pulse of the signal PWM after the mute signal MUTE transition state. On the other hand, when the mute signal MUTE is changed from a high logic level to a low logic level, the timing control circuit 51 updates the phase signals PH 1 , /PH 1 , PH 2 and /PH 2 , wherein the phase The signal PH 1 corresponds to the first pulse of the signal PWM after the mute signal MUTE transition state, and the phase signal PH 2 corresponds to the second pulse of the signal PWM after the mute signal MUTE transition state.
圖4顯示本發明一實施例之該充電電路20和該比較電路模組30運作時之時序圖。參考圖4，在時間T1 時，該相位訊號PH1 為高邏輯位準，因此圖2中的該開關21導通且該開關22截止。此時該電流源I1 對該電容C1 充電以產生隨時間增加的電壓V1 。在時間T2 時，該相位訊號PH1 轉態，故該開關21截止且該開關22導通。此時該電流源I1 會經由該開關22流至地端，而該電壓V1 會保持電壓位準VREF 。在時間T3 時，該相位訊號PH2 為高邏輯位準，故該開關23導通且該開關24截止。此時該電流源I2 對該電容C2 充電以產生隨時間增加的電壓V2 。在本實施例中，該電容C1 和該電容C2 的容值相同，且該電流源I2 的電流值為該電流源I1 的兩倍。故在時間T4 時(T4 -T3 =0.25＊ T)，該電壓V2 會到達電壓位準VREF 。4 is a timing diagram showing the operation of the charging circuit 20 and the comparison circuit module 30 in accordance with an embodiment of the present invention. Referring to Figure 4, at time T 1, the phase signal PH 1 is a high logic level, so that in Figure 2 the switch 21 is turned on and the switch 22 is turned off. At this time, the current source I 1 charges the capacitor C 1 to generate a voltage V 1 that increases with time. At time T 2 , the phase signal PH 1 is in a state of transition, so that the switch 21 is turned off and the switch 22 is turned on. At this time, the current source I 1 will flow to the ground via the switch 22, and the voltage V 1 will maintain the voltage level V REF . 3 at time T, the phase of the signal PH 2 is at high logic level, so that the switch 23 is turned on and the switch 24 is turned off. At this time, the current source I 2 charges the capacitor C 2 to generate a voltage V 2 that increases with time. In this embodiment, the capacitance C 1 and the capacitance C 2 have the same capacitance, and the current source I 2 has a current value twice that of the current source I 1 . Therefore, at time T 4 (T 4 -T 3 =0.25 * T), the voltage V 2 reaches the voltage level V REF .
當該電壓V2 會到達電壓位準VREF ，該比較器31會輸出具有高邏輯位準的訊號HP_DET至該時序產生電路71。在接收該訊號HP_DET後，該時序產生電路71會產生一輸出訊號PWM_HP。在本實施例中，該輸出訊號PWM_HP的第一脈衝之寬度會由該偵測訊號HP_DET和該脈衝寬度調變訊號PWM所決定，而該輸出訊號PWM_HP其後的脈衝之寬度會等於該脈衝寬度調變訊號PWM的脈衝之寬度。因此，該輸出訊號PWM_HP的第一脈衝之寬度(=0.25＊ T)會小於該脈衝寬度調變訊號PWM的脈衝之寬度(=0.5T)。在時間T5 後，電壓V1 和V2 會藉由一開關(未繪出)短路至地端。因此，該比較器31會產生具有低邏輯位準的訊號HP_DET至該時序產生電路71。When the voltage V 2 reaches the voltage level V REF , the comparator 31 outputs a signal HP_DET having a high logic level to the timing generating circuit 71. After receiving the signal HP_DET, the timing generating circuit 71 generates an output signal PWM_HP. In this embodiment, the width of the first pulse of the output signal PWM_HP is determined by the detection signal HP_DET and the pulse width modulation signal PWM, and the pulse width of the output signal PWM_HP is equal to the pulse width. The width of the pulse of the modulation signal PWM. Therefore, the width of the first pulse of the output signal PWM_HP (= 0.25 * T) is smaller than the width of the pulse of the pulse width modulation signal PWM (= 0.5T). After a time T 5, and the voltage V 1 is V 2 will be by a switch (not shown) shorted to ground. Therefore, the comparator 31 generates a signal HP_DET having a low logic level to the timing generating circuit 71.
圖4所述的實施例係假設電容C1 和C2 的容值相同，且電流源I2 的電流值為該電流源I1 的兩倍。然而，本發明不應以此為限。在本發明其他實施例中，電容C1 和C2 的容值以及電流源I1 和I2 的電流值可以任意組合，只要符合該電壓V1 的電壓上升斜率小於該電壓V2 的電壓上升斜率即可。由於該電壓V1 的電壓上升斜率小於該電壓V2 的電壓上升斜率，且該些相位訊號PH1 和PH2 的高邏輯位準時間相同(=0.5T)，故該電壓V2 會較快到達電壓位準VREF 。當該電壓V2 到達電壓位準VREF 時，該時序產生電路71會產生該輸出訊號PWM_HP的第一脈衝，且該第一脈衝會在該相位訊號PH2 轉態為低邏輯位準時結束。該輸出訊號PWM_HP其後之脈 衝會跟隨該脈衝寬度調變訊號PWM之脈衝。Example 4 FIG. Assuming that the capacitor based capacitance values C 1 and C 2 is the same, and the current source current I 2 is twice that of the current source I 1. However, the invention should not be limited thereto. In other embodiments of the present invention, the capacitance values of the capacitors C 1 and C 2 and the current values of the current sources I 1 and I 2 may be arbitrarily combined as long as the voltage rising slope conforming to the voltage V 1 is less than the voltage rise of the voltage V 2 . The slope can be. Since the voltage rising slope of the voltage V 1 is smaller than the voltage rising slope of the voltage V 2 , and the high logic level times of the phase signals PH 1 and PH 2 are the same (= 0.5T), the voltage V 2 will be faster. The voltage level V REF is reached. When the voltage V 2 reaches the voltage level V REF , the timing generating circuit 71 generates a first pulse of the output signal PWM_HP, and the first pulse ends when the phase signal PH 2 transitions to a low logic level. The pulse of the output signal PWM_HP will follow the pulse of the pulse width modulation signal PWM.
參考圖4，該靜音訊號MUTE在時間T8 時由高邏輯位準轉態為低邏輯位準。因此，在時間T9 和時間T10 時該時序控制電路51分別輸出相位訊號PH1 和PH2 ，其中相位訊號PH1和PH2個別對應該訊號PWM在該靜音訊號MUTE轉態後的第一個和第二個脈衝。類似地，藉由該充電電路20和該比較電路模組30之運作，該比較器31會在時間T11 時輸出具有高邏輯位準的該訊號HP_DET。在接收該偵測訊號HP_DET後，該時序產生電路71會終止輸出該訊號PWM_HP。因此，該輸出訊號PWM_HP的最後一個脈衝之寬度(=0.25＊ T)小於先前的脈衝之寬度(=0.5＊ T)。藉由減少該輸出訊號PWM_HP的第一脈衝和最後一個脈衝之寬度，該裝置200可降低耳機或是喇叭等聲頻輸出裝置上所產生的氣爆雜音。Referring to Figure 4, the muting signal MUTE at time T 8 A high to logic level is transited to a low logic level. Accordingly, the phase signals respectively output time period T 9 and T 10 to this timing control circuit 51 PH 1 and PH 2, wherein the phase signal PH1 and PH2 of the individual PWM signal should be muted when the MUTE signal and a first transient The second pulse. Similarly, by comparing the operation of the charging circuit 20 and the circuit module 30, the comparator 31 outputs the signal having a high logic level HP_DET at time T 11. After receiving the detection signal HP_DET, the timing generation circuit 71 terminates outputting the signal PWM_HP. Therefore, the width of the last pulse of the output signal PWM_HP (= 0.25 * T) is smaller than the width of the previous pulse (= 0.5 * T). By reducing the width of the first pulse and the last pulse of the output signal PWM_HP, the device 200 can reduce the blasting noise generated on an audio output device such as a headphone or a speaker.
此外，本發明中的裝置亦可藉由控制輸出訊號PWM_HP的多個脈衝之不同寬度來降低氣爆雜音。圖5顯示本發明另一實施例之充電電路50之細部電路圖。參考圖5，該充電電路50包含電流源I1 、複數個電流源I3-0 ~I3-N 、複數個開關52-0~52-N、複數個開關21~24以及電容C1 和C2 。該些開關52-0~52-N係分別連接於該些電流源I3-0 ~I3-N ，且該些開關52-0~52-N係由一匯流排65上的控制訊號IB[N：0]所控制。In addition, the apparatus of the present invention can also reduce the air blast noise by controlling different widths of the plurality of pulses of the output signal PWM_HP. Fig. 5 is a detailed circuit diagram of a charging circuit 50 according to another embodiment of the present invention. Referring to FIG. 5, the charging circuit 50 includes a current source I 1 , a plurality of current sources I 3-0 ~ I 3-N , a plurality of switches 52 - 0 - 52 - N , a plurality of switches 21 - 24 , and a capacitor C 1 and C 2 . The switches 52-0~52-N are respectively connected to the current sources I 3-0 ~I 3-N , and the switches 52-0~52-N are controlled by a control signal IB on a bus 65 Controlled by [N:0].
圖6顯示本發明一實施例之具有該充電電路60的裝置200’運作時之時序圖。在本實施例中，係以N=3為例說明，即該充電電路50具有四個電流源I3-0 ~I3-3 以及四個開關 52-0~52-3。藉由控制該控制訊號IB[3：0]的數值，可以在該相位訊號PH2 的脈衝期間控制該些開關52-0~52-3的導通狀況以調整充電電流之大小並控制充電時間，進而控制該電壓V2 到達電壓位準VREF 的時間，以決定該偵測訊號HP_DET產生之時間。依此方式，可產生該輸出訊號PWM_HP的不同脈衝之不同寬度。Figure 6 is a timing diagram showing the operation of the apparatus 200' having the charging circuit 60 in accordance with an embodiment of the present invention. In the present embodiment, N=3 is taken as an example, that is, the charging circuit 50 has four current sources I 3-0 to I 3-3 and four switches 52-0 to 52-3. By controlling the control signal IB: value [30], it is possible to control the switches 52-0 ~ 52-3 conducting condition during the pulse phase signal PH 2 to adjust the size of the charging current and the charging time control, Further, the time when the voltage V 2 reaches the voltage level V REF is controlled to determine the time when the detection signal HP_DET is generated. In this way, different widths of the different pulses of the output signal PWM_HP can be generated.
參考圖6，因應於不同之該控制訊號IB[3：0]，會有不同脈衝W1 、W2 、W3 、W4 、W5 、W6 之不同寬度。當該靜音訊號MUTE由低邏輯位準轉態為高邏輯位準時，該時序控制電路51會產生相位訊號PH1 和PH2 ，其中該相位訊號PH2 為具有多個連續脈衝之訊號。在本例中，若該控制訊號IB[3：0]=1111，代表四個電流源I3-0 ~I3-3 都開啟，故總充電電流較大，所以充電時間較短，W1 的寬度則較小。當該控制訊號IB[3：0]=0111，代表四個電流源I3-0 ~I3-3 中有三個開啟，其總充電電流較控制訊號IB[3：0]=1111時為小，所以充電時間較長，W2 的寬度大於W1 。當該控制訊號IB[3：0]=0011，代表四個電流源I3-0 ~I3-3 中僅有兩個電流源開啟，充電電流更小，所以充電時間更長，W3 的寬度較大。在本實施例中，當該偵測訊號HP_DET出現三個短暫脈衝後，該輸出訊號PWM_HP其後之脈衝會跟隨該脈衝寬度調變訊號PWM之脈衝。然而，本發明不應以此為限。Referring to FIG 6, differs in response to the control signal IB [3: 0], have different pulse W 1, W 2, W 3 , W 4, W 5, W 6 of different widths. When the mute signal MUTE transitions from a low logic level to a high logic level, the timing control circuit 51 generates phase signals PH 1 and PH 2 , wherein the phase signal PH 2 is a signal having a plurality of consecutive pulses. In this example, if the control signal IB[3:0]=1111, it means that the four current sources I 3-0 ~I 3-3 are all turned on, so the total charging current is large, so the charging time is short, W 1 The width is smaller. When the control signal IB[3:0]=0111, three of the four current sources I 3-0 ~I 3-3 are turned on, and the total charging current is smaller than the control signal IB[3:0]=1111. , so the charging time is longer, and the width of W 2 is greater than W 1 . When the control signal IB[3:0]=0011, it means that only two current sources of the four current sources I 3-0 ~I 3-3 are turned on, the charging current is smaller, so the charging time is longer, W 3 Larger width. In this embodiment, after three short pulses of the detection signal HP_DET, the subsequent pulse of the output signal PWM_HP follows the pulse of the pulse width modulation signal PWM. However, the invention should not be limited thereto.
另一方面，當該靜音訊號MUTE由高邏輯位準轉態為低邏輯位準時，該時序控制電路51會產生相位訊號PH1 和PH2 ，其中該相位訊號PH2 為具有多個連續脈衝之訊號。在本例中，若該控制訊號IB[3：0]=0011，代表四個電流源I3-0 ~I3-3 中僅有兩個電流源開啟，總充電電流較小，所以充電時間較長，W4 的寬度則較大。類似地，當該控制訊號IB[3：0]=0111，代表四個電流源I3-0 ~I3-3 中有三個開啟，其充電電流較控制訊號IB[3：0]=0011時為大，所以總充電時間較短，W5 的寬度小於W4 。當該控制訊號IB[3：0]=1111，代表四個電流源I3-0 ~I3-3 都開啟，總充電電流較大，所以充電時間較短，W6 的寬度較窄。在本實施例中，當偵測訊號HP_DET出現三個短暫脈波後，該時序產生電路71會終止輸出該訊號PWM_HP。然而，本發明不應以此為限。On the other hand, when the mute signal MUTE is changed from a high logic level to a low logic level, the timing control circuit 51 generates phase signals PH 1 and PH 2 , wherein the phase signal PH 2 has a plurality of consecutive pulses. Signal. In this example, if the control signal IB[3:0]=0011, it means that only two current sources of the four current sources I 3-0 ~I 3-3 are turned on, and the total charging current is small, so the charging time Longer, the width of W 4 is larger. Similarly, when the control signal IB[3:0]=0111, three of the four current sources I 3-0 ~I 3-3 are turned on, and the charging current is lower than the control signal IB[3:0]=0011. It is large, so the total charging time is short, and the width of W 5 is smaller than W 4 . When the control signal IB[3:0]=1111, it means that the four current sources I 3-0 ~I 3-3 are all turned on, and the total charging current is large, so the charging time is short, and the width of W 6 is narrow. In this embodiment, after three short pulse waves appear in the detection signal HP_DET, the timing generation circuit 71 terminates outputting the signal PWM_HP. However, the invention should not be limited thereto.
綜上所述，當該靜音訊號MUTE由低邏輯位準轉態為高邏輯位準時，藉由遞減開啟多個電流源I3-0 ~I3-N 的方式，可以在該相位訊號PH2 的脈衝期間逐漸減少該電容C2 的充電電流，進而改變該電容C2 的充電時間，使該輸出訊號PWM_HP的脈衝寬度可以依序增加。另一方面，當該靜音訊號MUTE由高邏輯位準轉態為低邏輯位準時，藉由遞增開啟多個電流源I3-0 ~I3-N 的方式，可以在該相位訊號PH2 的脈衝期間逐漸增加該電容C2 的充電電流，進而改變該電容C2 的充電時間，使該輸出訊號PWM_HP的脈衝寬度可以依序減少。In summary, when the mute signal MUTE is changed from a low logic level to a high logic level, the phase signal PH 2 can be used by decrementing a plurality of current sources I 3-0 ~ I 3-N . During the pulse period, the charging current of the capacitor C 2 is gradually reduced, thereby changing the charging time of the capacitor C 2 , so that the pulse width of the output signal PWM_HP can be sequentially increased. On the other hand, when the mute signal MUTE is changed from a high logic level to a low logic level, by sequentially turning on a plurality of current sources I 3-0 ~ I 3-N , the phase signal PH 2 can be During the pulse period, the charging current of the capacitor C 2 is gradually increased, thereby changing the charging time of the capacitor C 2 , so that the pulse width of the output signal PWM_HP can be sequentially reduced.
本發明之技術內容及技術特點已揭示如上，然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種 不背離本發明精神之替換及修飾。因此，本發明之保護範圍應不限於實施例所揭示者，而應包括各種不背離本發明之替換及修飾，並為以下之申請專利範圍所涵蓋。The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various changes based on the teachings and disclosures of the present invention. The substitutions and modifications may be made without departing from the spirit of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims
10‧‧‧D類放大器10‧‧‧D class amplifier
12‧‧‧脈寬調變器12‧‧‧ Pulse Width Modulator
14‧‧‧功率放大器14‧‧‧Power Amplifier
16‧‧‧低通濾波器16‧‧‧Low-pass filter
18‧‧‧聲頻輸出裝置18‧‧‧ audio output device
200‧‧‧降低氣爆雜音之裝置200‧‧‧A device for reducing gas explosion noise
20,50‧‧‧充電電路20,50‧‧‧Charging circuit
21~24,52-0 52-1,...,52-N‧‧‧開關21~24, 52-0 52-1,...,52-N‧‧‧Switch
30‧‧‧比較電路模組30‧‧‧Comparative circuit module
31‧‧‧比較器31‧‧‧ Comparator
50‧‧‧時序控制電路模組50‧‧‧Sequence Control Circuit Module
51‧‧‧時序控制電路51‧‧‧Sequence Control Circuit
55‧‧‧匯流排55‧‧‧ Busbar
70‧‧‧時序產生電路模組70‧‧‧Time Generation Circuit Module
71‧‧‧時序產生電路71‧‧‧ Timing generation circuit
C1 ,C2 ‧‧‧電容C 1 , C 2 ‧‧‧ capacitor
I1 ,I2 , I3-0 ,I3-1 ,I3-2 ‧‧‧電流源I 1 , I 2 , I 3-0 , I 3-1 , I 3-2 ‧‧‧ current source
藉由參照前述說明及下列圖式，本發明之技術特徵及優點得以獲得完全瞭解。The technical features and advantages of the present invention are fully understood by reference to the foregoing description and the accompanying drawings.
圖1顯示一習知處理數位輸入音源訊號的D類放大器之方塊示意圖；圖2顯示本發明一實施例之一種用於降低氣爆雜音的裝置之方塊示意；圖3顯示本發明一實施例之該時序控制電路運作時之時序圖；圖4顯示本發明一實施例之該充電電路和該比較電路模組運作時之時序圖；圖5顯示本發明另一實施例之充電電路之細部電路圖；以及圖6顯示本發明一實施例之具有該充電電路的裝置運作時之時序圖。1 is a block diagram showing a conventional class D amplifier for processing digital input sound source signals; FIG. 2 is a block diagram showing an apparatus for reducing gas explosion noise according to an embodiment of the present invention; FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a timing diagram showing the operation of the charging circuit and the comparison circuit module according to an embodiment of the present invention; and FIG. 5 is a detailed circuit diagram of the charging circuit according to another embodiment of the present invention; And FIG. 6 is a timing chart showing the operation of the apparatus having the charging circuit according to an embodiment of the present invention.
200‧‧‧降低氣爆雜音之裝置200‧‧‧A device for reducing gas explosion noise
20‧‧‧充電電路20‧‧‧Charging circuit
21~24‧‧‧開關21~24‧‧‧Switch
30‧‧‧比較電路模組30‧‧‧Comparative circuit module
31‧‧‧比較器31‧‧‧ Comparator
50‧‧‧時序控制電路模組50‧‧‧Sequence Control Circuit Module
51‧‧‧時序控制電路51‧‧‧Sequence Control Circuit
70‧‧‧時序產生電路模組70‧‧‧Time Generation Circuit Module
71‧‧‧時序產生電路71‧‧‧ Timing generation circuit
C1 ,C2 ‧‧‧電容C 1 , C 2 ‧‧‧ capacitor
I1 ,I2 ‧‧‧電流源I 1 , I 2 ‧‧‧ current source
Claims (9)
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| TW101129848A TWI448166B (en) | 2012-08-17 | 2012-08-17 | Device for reducing pop noise |
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| TW101129848A TWI448166B (en) | 2012-08-17 | 2012-08-17 | Device for reducing pop noise |
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