TWI436364B - Non-volatile memory cell unit - Google Patents

Description

Non-volatile memory cell

The present invention relates to a structure and method for a non-volatile memory cell of a single polysilicon layer, and more particularly to a structure and method for improving the reliability and sensing boundary of a non-volatile memory cell of a polycrystalline germanium layer.

A non-volatile memory is a type of memory that can retain its stored data while the memory is not being powered. In today's technology, non-volatile memory can be roughly divided into two types, one of which is a read only memory (ROM), and the other is a flash memory.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram showing a conventional stacked polycrystalline germanium layer non-volatile memory cell unit and its data sensing disclosed in US Pat. No. 5,973,957. The floating polysilicon gates of the transistors 101, 102 for storing data receive the same voltage VG and correspondingly generate currents I1, I2. The comparator CMP detects the data stored in the non-volatile memory cells (the transistors 101, 102) by comparing the currents flowing through the transistors 103, 104 with the currents I1, I2. The transistors 103 and 104 are connected in a diode structure and connected to the operating voltage VCC. The main reason for this data sensing is to use the memory cell as the source of the reference current. In this approach, the sensing margin can be received by using a dummy reference memory cell to receive a similar bias voltage, and the dummy reference memory cell has the same temperature sensitivity as the actual memory cell. And the symmetry of the layout space arrangement greatly improves the reliability of the non-volatile memory cell unit.

In addition, please refer to FIG. 2A. FIG. 2A is a schematic diagram showing the non-volatile memory cell unit and its data sensing disclosed in US Pat. No. 6,950,342. The non-volatile memory cell unit 210 includes capacitors constructed using the transistors M1c, M1t, M0t, and M0c, and transistors M1 and M0 connected to the voltage V. The transistors M1c and M1t respectively couple the received voltages V1c and V1t to the floating polysilicon gate Fg1, and the transistors M0c and M0t respectively couple the received voltages V0c and V0t to the floating polysilicon gate Fg0. The current sensor 220 senses the data stored in the non-volatile memory cell unit 210 by measuring the currents I1, I0 flowing out of the transistors M1, M0. The sensing boundary of such a conventional non-volatile memory cell can also be improved by comparing the current difference between the actual memory cell and the virtual memory cell.

It is worth mentioning that the non-volatile memory cell 210 may occur after a long period of data storage or after multiple reading, writing and erasing due to the gate oxide of the transistor M1 or M0. The phenomenon of leakage and loss of electricity. When the above leakage phenomenon occurs, the current when the transistor M1 or M0 is turned on will decrease as the curve C1 as shown in FIG. 2B decreases with the storage time. As a result, the distance A1 between the current curve CV1 when the transistor M1 or M0 is turned on and the current curve CV2 when it is turned off decreases to the distance A2 as the storage time increases. Along with the sensing result of the current sensor 220, an error may occur, so that the data stored by the non-volatile memory cell unit 210 is misinterpreted.

In order to make the reading data of the non-volatile memory cell unit correct, a so-called memory window is an important parameter for the design of the non-volatile memory cell unit. There are a number of parameters that affect the memory window, such as the inconsistency between the memory cell and the reference device (such as the layout between the memory cell and the reference device, temperature or operating bias), and the floating of the non-volatile memory cell. A polysilicon gate is surrounded (for example, a floating polysilicon gate oxide layer or a severe leakage path of a sidewall spacer). In view of this, various techniques for solving the above various problems to enhance the memory window of the non-volatile memory cell unit have been proposed, respectively.

The present invention provides three non-volatile memory cell units in which two identical memory elements are included in a non-volatile memory cell unit using a predetermined connection to enhance the sensing boundary. Under this condition, all three non-volatile memory cell units can effectively increase the memory window and effectively compensate for the leakage phenomenon generated when storing data.

The invention provides a non-volatile memory cell unit of a single polysilicon layer, comprising a first N-type transistor pair and first and second control gates. The first transistor pair has a first transistor and a second transistor which are connected in series and in the same state along the read path, and the first transistor and the second transistor respectively have a first floating polysilicon gate and a second The floating polysilicon gate is respectively used as a charge storage medium, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other, and when the non-volatile memory cell is read or written or deleted, The charge movement in the first floating polysilicon gate in a transistor and the second floating polysilicon gate in the second transistor is the same.

The invention further provides a non-volatile memory cell unit of a single polysilicon layer, comprising a pair of transistors and first, second, third and fourth control gates. The pair of transistors has a first transistor and a second transistor which are mutually connected and opposite in shape, wherein the first and second transistors respectively have a first floating polysilicon gate and a second floating polysilicon gate as a charge storage medium . The first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other. The first control gate is coupled to the first floating polysilicon gate through the first coupling junction. The second control gate is coupled to the second floating polysilicon gate through the second coupling junction. The third control gate is coupled to the first floating polysilicon gate through the first tunnel junction. The fourth control gate is coupled to the second floating polysilicon gate through the second tunneling junction.

The invention further provides a non-volatile memory cell unit comprising a first P-type, a two-P-type transistor, an N-type transistor pair, and first and second coupling capacitors. The first P-type transistor has a gate and a first source/drain. The second P-type transistor has a gate and a first source/drain. The N-type transistor pair has a third transistor and a fourth transistor connected in series with each other, wherein the third transistor and the fourth transistor respectively have a first floating polysilicon gate and a second floating polysilicon gate, and the first floating The polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other. One end of the first coupling capacitor is coupled to the gate of the first transistor and coupled to the first floating polysilicon gate, and the other end receives the first control voltage. The second coupling capacitor has one end connected to the gate of the second transistor and coupled to the second floating polysilicon gate, and the other end receiving the second control voltage.

Based on the above, the non-volatile memory cell provided by the present invention can pass through FN tunneling, Band-to-Band Tunneling Hot Electron (BBHE), and band-to-band tunneling induction thermoelectric hole ( Band-to-Band tunneling Hot Hole (BBHH), substrate hole and channel hot electron (CHE) to inject or remove electrons or holes to write and delete data. efficacy. The non-volatile memory cell unit provided by the invention can effectively reduce the voltage required for writing and deleting, and effectively compensate for the leakage phenomenon occurring in the stored data.

The above described features and advantages of the present invention will be more apparent from the following description.

3A is a schematic diagram of a single polysilicon layer non-volatile memory cell unit 300 in accordance with an embodiment of the present invention. In some non-volatile memory cell technology, two or more layers of polycrystalline germanium are often used to process and stack and stack for non-volatile memory purposes. In the present embodiment, a non-volatile memory cell unit which is more cost-effective and more suitable for a single-layer polysilicon layer of built-in memory is proposed. Referring to FIG. 3A, the non-volatile memory cell unit 300 includes a transistor pair 310 and control gates CG1, CG2. The transistor pair 310 has a transistor M1 connected in series and a transistor M2. The transistor M1 and the transistor M2 have floating polysilicon gates fg1 and fg2, respectively. And the floating polysilicon gates fg1 and fg2 are physically or electrically isolated from each other. The control gate CG1 is coupled to the floating polysilicon gate fg1 through a capacitive coupling interface. Similarly, the control gate CG2 is coupled to the floating polysilicon gate fg2 through another capacitive coupling interface.

Control gates CG1, CG2 receive control voltages VC1, VC2, respectively, and couple control voltages VC1, VC2 to floating polysilicon gates fg1 and fg2 through corresponding tunneling junctions. Wherein, the control gates CG1, CG2 can be constructed by using a capacitor, such as a junction of P+ and N-well (NW) or N+ and N-well (NW). Moreover, the capacitor can be constructed by the capacitance formed by the transistor (the base, the drain and the source of the transistor are connected to each other as the first end of the capacitor, and the second end of the capacitor is used to make the gate of the transistor) . In this embodiment, since the P-type MOSFET is used as the base of the P-type MOSFET, since the matrix of the N-well can receive a positive voltage isolated from the P-type well P-type substrate, Suitable for forming the above capacitors.

It should be noted here that in the present embodiment, the transistors M1 and M2 in the transistor pair 310 are all N-type gold oxide half field effect transistors and also accept electronic writing or deleting operations. That is to say, the operations of writing and erasing performed on the transistors M1 and M2 are the same. If electrons are stored in the floating polysilicon gates fg1 and fg2, the non-volatile memory cell 300 has a higher threshold voltage and a lower endpoint than when the electrons are not stored in the floating polysilicon gates fg1 and fg2. The on current I _BL flowing out of BL and SL (as shown in FIG. 3B). This means that the electrons stored in the floating polysilicon gates fg1 and fg2 can reduce the conduction current I _BL from the terminals BL and SL of the transistors M1 and M2.

In the design of the non-volatile memory cell 300, the charge retention problem needs to be taken into account, especially in manufacturing techniques with more severe memory leakage. In the actual case, as shown in FIG. 3C, the electrons originally stored in the floating polysilicon gate fg2 may be lost to the floating polysilicon gate fg2 of the transistor M2, and no electrons are present. In this case, the channel under the floating polysilicon gate fg2 of the transistor M2 will be turned on unless there is an external switch for turning off the transistor M2. In order to avoid the above situation, since the floating polysilicon gates fg1, fg2 are physically or electrically isolated from each other, the transistor M1 is designed to be connected in series with the transistor M2 (mainly along the path in which the material is read). To provide a path to close between endpoints BL through SL. In a more careful error rate analysis, the memory array IP includes a memory transistor of floating polysilicon gates of n bits, and the error rate of the transistors of each floating polysilicon gate is "f". And the total error rate of the memory array IP

F1=1-(1-f) ⁿ ;

F1 is the error rate when there is no transistor M1 connected in series.

In order to improve the reliability of the memory array IP, the transistor M1 is added in series with the transistor M2 to construct a memory cell structure of one bit. Under this new architecture, the total error rate of the memory array IP is

F2=1-(1-f ² ) ⁿ ;

F2 is the error rate when there is a transistor M1 connected in series.

The error rate F2 when the transistor M1 connected in series is added is greatly improved with respect to the error rate F1 when the transistor M1 to which the series connection is not applied is added. That is to say, the transistors M1 and M2 form a memory cell which is fault-tolerant and automatically complete the self-repairing operation when the electrons stored in the transistor M1 or M2 are lost.

FIG. 3D illustrates another embodiment of a non-volatile memory cell unit 300 of the present invention. In the present embodiment, transistors M3, M4 are additionally added, and the patterns of the transistors M3, M4 in the transistor pair 320 are opposite to those of the transistors M1, M2. That is to say, in the present embodiment, the transistors M3, M4 are all P-type MOS field-effect transistors, and are connected in parallel and connected to the signal BL _P . As can be seen from the above description, the transistors M1, M2 can be formed in the P-well PW of the integrated circuit, and the transistors M3, M4 can be formed in the N-well of the integrated circuit ( N-well) in NW. Transistors M3, M4 are commonly used for tunneling purposes. Generally, the element sizes of the transistors M3, M4 are the smallest relative to the control gates CG1, CG2 and the transistors M1, M2. Alternatively, the transistors M3, M4 can also be configured in the form of tunneling junctions to provide electron tunneling into/out of the floating gate (polysilicon layer). A tunneling junction can be considered as an area where electrons or charges pass through/in; and a coupling junction is used for capacitive coupling.

Incidentally, the transistors M1 and M2 in this embodiment may be a native device with a lower threshold voltage or a lightly doped Drain (LDD) for processing. The resulting transistor. Since the transistors M1, M2 are read transistors, if the device design has a lower threshold voltage, the voltage required for reading the non-volatile memory cell 300 can be effectively reduced. Moreover, in order to ensure high quality of the non-volatile memory cell unit 300, a salicide protection layer (SAP) for preventing metal oxide formation is overlaid on the floating polysilicon gate. This not only eliminates the mechanical stress from the Inter Layer Dielectric (ILD) in the back-end process, but also avoids the short-circuit of the metal oxide along the sidewall void wall from the floating polysilicon gate to the source of the metal oxide. Or bungee jumping. In the above case, the holding force of the electric charge is effectively increased.

With continued reference to FIG. 3D, the following description of the operations of writing, deleting, and reading the non-volatile memory cell unit 300 will enable those skilled in the art to understand the application of the non-volatile memory cell unit 300.

When writing to the non-volatile memory cell 300, the control gates CG1, CG2 receive the high voltage control voltages VC1, VC2 and capacitively couple the control voltages VC1, VC2 to the floating polysilicon gate fg1 through the coupling junctions, respectively. And fg2. Thereby, the floating polysilicon gates fg1 and fg2 attract electron injection and store a plurality of electrons. At the same time, since the control gates CG1, CG2 also couple the control voltages VC1, VC2 to the floating polysilicon gates fg3, fg4. Therefore, in the case where the transistor pair 320 is disposed, the transistors M3 and M4 also adsorb a plurality of electrons. Please note that since in this embodiment, the transistors M1 and M2 are N-type gold oxide half field effect transistors, the electrons adsorbed on the floating polysilicon gates fg1 and fg2 may cause the transistors M1 and M2. The channel is in a more closed state. In contrast, the transistors M3 and M4 are P-type MOS field-effect transistors, and therefore, the electrons adsorbed on the floating polysilicon gates fg3 and fg4 cause the channels of the transistors M3 and M4 to be more open. .

Under this arrangement, the N-type MOS field-effect transistors M1, M2 are designed to be connected in series. That is to say, one of the source or the drain of the transistor M1 is connected to the unconnected end of the source or the drain of the transistor M2 (which may also be said to be the floating terminal of the source or the drain). point). In contrast, P-type MOS field-effect transistors M3, M4 are designed to be connected to each other. The terminals PB, PS are respectively coupled to one of the source or the drain of the transistors M3, M4. End point BL _{P is} connected to another unfloating end of the source or drain of transistors M3, M4.

When reading for the non-volatile memory cell 300, a voltage can be supplied to the other terminals by the source/drain BL, PB, PS, and BL _{P of the} transistors M1, M3/M4, and is electrically The source/drain SL, PB/PS of the crystals M2, M3/M4 generate corresponding currents. When sensing the data stored in the non-volatile memory cell unit 300, the current generated by the source/drain SL, PB/PS of the transistors M2, M3/M4 can be received with a threshold (reference current) Iref) is compared and used to determine the data (logical high level or logic low level) stored in the non-volatile memory cell unit 300. In the case where the transistor pair 320 is disposed, the current generated by the source/drain SL of the receiving transistor M2 can be compared with the reference current Iref, and the non-volatile memory cell unit 300 can also be known. What is the data in the channel of the medium N-type transistor? When the data in the P-type transistor channel is read, the current read by the PB, PS of the source/drain of the transistor M3/M4 is compared with the reference current Iref. In addition, the non-volatile memory cell unit 300 also plays a self by comparing the current generated by the source/drain SL of the transistor M2 with the current read by the PB and PS of the source M3/M4 source/drain. A memory cell that provides a reference value (Self-Referencing).

Please pay special attention to the fact that if one of the transistors M1 and M2 (for example, the transistor M2) is damaged, the oxide layer of the gate occurs because the natural oxide layer is damaged, the storage time is too long or the periodic oxide layer When the voltage is broken, the electrons adsorbed on the floating polysilicon gate fg2 of the transistor M2 are reduced by the leakage. That is to say, the channel of the transistor M1 may not be continuously maintained in the off state. However, this phenomenon does not cause misinterpretation of the reading operation of the non-volatile memory cell unit 300. Because, although the channel of the transistor M2 may not be turned off, but the channel of the transistor M1 remains in the off state, the current generated by the source/drain SL of the transistor M2 is not oxidized by the gate of the transistor M2. A possible leakage path is created in the layer and changes. Therefore, the data interpretation of the non-volatile memory cell unit 300 does not cause an error. Further, the transistors M1, M2 have the same electron movement in the floating polysilicon gate when the non-volatile memory cell unit 300 performs data writing or erasing.

Next, please refer to FIG. 4. FIG. 4 is a schematic diagram of a non-volatile memory cell unit 400 according to another embodiment of the present invention. Unlike the previous embodiment, the non-volatile memory cell unit 400 further includes control gates CG3 and CG4 coupled to the floating polysilicon gates fg1, fg3 and fg2, fg4 through different tunneling junctions, respectively. The control gates CG3 and CG4 can also be constructed by capacitors, but can also be constructed by means of a transistor coupled to a capacitor. Under the above structure, the tunnel junctions are formed in the control gates CG3 and CG4 instead of the transistors M3 and M4. Transistors M3 and M4 act as read transistors to provide a path for data reading without being stressed by high voltages. Among them, the tunnel junction is susceptible to high voltage and damage.

Referring to FIG. 5A, FIG. 5A illustrates a non-volatile memory cell unit 500 according to still another embodiment of the present invention. The non-volatile memory cell unit 500 includes a transistor pair 510 (M1, M2 source or drain is interconnected), transistors M3, M4, and coupling capacitors C1, C2. The transistor pair 510 has transistors M1 and M2 connected in series with each other. The transistors M1 and M2 respectively have a floating polysilicon gate fg1 and a floating polysilicon gate fg2, and the floating polysilicon gate fg1 and the floating polysilicon gate fg2 are physically or electrically isolated from each other. One end of the coupling capacitor C1 is connected to the gate of the transistor M3 and capacitively coupled to the floating polysilicon gate fg1, and the other end of the coupling capacitor C1 receives the control voltage CGB. In contrast, one end of the coupling capacitor C2 is connected to the gate of the transistor M4 and capacitively coupled to the floating polysilicon gate fg2, and the other end of the coupling capacitor C2 receives the control voltage CG. In addition, the non-volatile memory cell unit 500 is connected to the transistor switch SW1, and when the transistor switch SW1 is turned on according to the word line signal WL, the voltage Vdd is supplied to the transistor pair 510.

It is worth mentioning that the transistors M3 and M4 are not a general 4-terminal transistor with both source and drain. Please refer to FIG. 5A and FIG. 5B simultaneously. FIG. 5B is a schematic diagram showing the process structure of the transistors M3 and M4. As can be seen from FIG. 5B, the transistor M3 has only the gate G3 and the source (or drain) 521. That is, the transistor M3 does not have a drain (or source). Similarly, the transistor M4 has only the gate G4 and the source (or drain) 522. That is to say, the transistor M4 does not have a drain (or source). The area of the drain (or source) that should be used to form the transistors M3 and M4 is replaced by shallow trench isolation (STI) 540.

In this embodiment, the coupling capacitors C1 and C2 can also be capacitively coupled by a capacitor (for example, formed by a P+/N type well or an N+/N type well) or a transistor (for example, a P-type gold oxide semiconductor). Way to form. Moreover, the coupling capacitors C1, C2 can be constructed in a P-well in a deep N-well of the integrated circuit to reduce the writing and erasing of the non-volatile memory cell unit 500. The voltage required for the data. The transistors M1 and M2 in the transistor pair 510 are the same type of N-type gold-oxygen half-field effect transistors, and the transistors M3 and M4 are P-type gold-oxygen half-field effect transistors.

Next, in the actual operation of the non-volatile memory cell unit 500, in the present embodiment, when writing to the floating polysilicon gate fg1 of the transistor M1, it is necessary to synchronize the floating polysilicon gate fg2 of the transistor M2. delete. That is, when the control voltage CGB received by the coupling capacitor C1 is a high voltage (for example, 8.5 volts and the thickness of the floating polysilicon gate is 65 angstroms (A)) for data writing, the coupling capacitor C2 receives the control voltage CG at a low voltage ( For example, 0 volts) for data deletion. To be more precise, the coupling capacitor C1 couples the received 8.5 volts voltage to the floating polysilicon gate fg1 and applies a voltage of 0 volts to the HSB of the M3 and its N-well to make the floating polysilicon gate fg1 tunnel through FN. Inject a large number of electrons to complete the writing of the data. In contrast, the coupling capacitor C2 couples the received 0 volts voltage to the floating polysilicon gate fg2, and applies a voltage of 8.5 volts to the HS of the M4 and its N-type well, so that the floating polysilicon gate fg2 is removed by the FN tunneling effect. The adsorbed electrons complete the deletion of the data.

The source (or drain) of transistor M3 receives a bias voltage HSB (eg, 2 volts) and the N-well of transistor M3 receives a bias voltage of 8.5 volts (not shown in FIG. 5A). In this way, the above-mentioned bias voltage is set by the band-to-band tunneling induced thermoelectric effect to inject electrons into the floating polysilicon gate fg1 to accelerate the writing operation. On the other hand, the source (or drain) of the transistor M4 can receive a bias voltage HS (for example, 8.5 volts), or a bias voltage HS that receives a low voltage (for example, 2 volts) and is in its transistor. The M4 N-well receives 8.5 volts. This 2 volt bias voltage HS will help the transistor M4 to inject holes (remove electrons) into the floating polysilicon gate fg2 by means of substrate hole injection to accelerate data deletion. A bias voltage HS of 8.5 volts promotes the pulling of electrons by transistor M4 from its floating polysilicon gate fg2. Therefore, the deletion of the data can be completed by this.

In addition, the source (or drain) of the transistor M1 in the transistor pair 510 can receive a bias voltage DB of a low voltage (eg, 0 volts) or remain floating to assist the write operation of the transistor M1. . The source (or drain) of the transistor M2 can also receive a bias voltage D of a low voltage (for example, 0 volts) or maintain a floating, or can also receive a high voltage (for example, 6 volts). The voltage D is applied to cause the transistor M2 to pass through the effect of the band-to-band tunneling induction thermowell injection, and the hole is injected (removed electrons) to the floating polysilicon gate fg2 to accelerate the data deletion.

It is important to note that when the coupling capacitors C1, C2 are built into the P-type well in the deep N-well of the integrated circuit, the control voltages CGB, CG will be able to shift the voltage level. With the above-described control voltages CGB, CG and bias voltages HSB, HS between 0 and 8.5 volts, the control voltages CGB, CG and the bias voltages HSB, HS can be moved between -4.55 and 4.25 volts. That is, the voltage amplitude required for writing and erasing of the non-volatile memory cell unit 500 can be applied to the P-type well in the deep N-type well in the integrated circuit without short-circuiting because the negative bias voltage is not short-circuited. Effectively reduced.

In the near-reading operation for the non-volatile memory cell 500, only the conductive crystal switch SW1 is required to supply the voltage Vdd to the transistors M1, M2, and the bias voltages DB, D are received by the transistors M1, M2. The endpoints receive and compare the currents respectively to successfully access and read the data stored in the non-volatile memory cell unit 500. At the same time, the bias voltages HSB, HS, control voltages CGB, CG can be set to remain at the logic high voltage level (eg, 1.8 volts) used by conventional integrated circuits.

Incidentally, the transistors M1 and M2 in this embodiment are N-type gold oxide half field effect transistors. In general, N-type gold oxide half field effect transistors have twice the driving current of the P-type gold oxide half field effect transistor. Therefore, when reading, the N-type metal oxide half-field effect transistor has a faster electron movement rate and can sense the correct storage data faster.

The preservative power and reliability of the non-volatile memory cell unit 500 are also greatly improved because the sensing boundary is related to the off current of the transistor M1 and the difference in the on-current of the transistor M2 (floating polysilicon gate in the transistor M1) The pole fg1 is in the data write mode and the floating polysilicon gate fg2 of the transistor M2 is in the data deletion mode). If the electrons of the floating polysilicon gate fg1 are gradually lost by the floating polysilicon gate fg1, the non-volatile memory cell 500 can still be normal due to a large sensing boundary (greater than the applied reference current Iref generation mechanism). jobs. Therefore, the variation of the reference current Iref will not cause trouble. In the prior art, the reference current Iref is between the on current and the off current to reduce the sensing boundary, and the sensing boundary is smaller than the sensing boundary of the previous embodiment of the invention (equal to the on current and the cutoff) The difference in current).

Referring to FIG. 6A, FIG. 6A is a schematic diagram of a non-volatile memory cell unit 600 according to a further embodiment of the present invention. Unlike the non-volatile memory cell unit 500 of the previous embodiment, the transistors M3 and M4 of the non-volatile memory cell unit 600 are transistors having both a drain and a source. Please refer to FIG. 6B at the same time. FIG. 6B is a schematic diagram showing the process structure of the transistors M3 and M4. Wherein, the transistor M3 has a gate G3, a source (or drain), and a drain (or source) 631, 632. The transistor M4 has a gate G4, a source (or a drain), and a drain ( Or source) 633, 632. The transistors M3 and M4 share a drain (or source) 632. The gate of transistor M3 is coupled to capacitor C1 and to control voltage CGB, while gate G4 of transistor M4 is coupled to capacitor C2 and to control voltage CG.

In addition, when data is written for the transistor M1 of the non-volatile memory cell unit 600 and data is deleted by the transistor M2, the transistor M3 receives a bias voltage HSB of, for example, 3.3 volts, and the transistor M4 receives, for example, 8.5 volts. The bias voltage HS, at which time the electron transmission is removed from the floating polysilicon gate fg2 by the transistor M4 by the high electric field FN tunneling effect, and is injected into the floating polysilicon gate fg1 by the transistor M3 through the channel hot electron effect. Write and delete actions are more efficient.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a non-volatile memory cell unit 700 according to an embodiment of the present invention. The non-volatile memory cell unit 700 includes a transistor pair 710 and control gates CG1, CG2, CG3, and CG4. The transistor pair 710 has a transistor M1 and a transistor M2 which are connected in series and opposite in shape. The transistors M1 and M2 respectively have floating polysilicon gates fg1 and fg2, and the floating polysilicon gates fg1 and fg2 are physically or electrically isolated from each other. In this embodiment, the transistor M1 is an N-type MOSFET, and the transistor M2 is a P-type MOSFET, and the transistors M1 and M2 are coupled to the signal SL, and the transistor M1 and The source/drain electrodes BL1, BL2 of the transistor M2 are not coupled.

Please note that, as in all of the foregoing embodiments, the control gates CG1, CG2, CG3, and CG4 can be implemented by capacitors, and the capacitors can be constructed by a transistor or a coupling junction coupled to a capacitor.

When the writing and deleting operations are performed for the non-volatile memory cell unit 700, the non-volatile memory cell unit 700 of the present embodiment can be performed in two modes. One of the modes is to simultaneously write or delete two transistors of the transistor pair 710 (that is, simultaneously write or simultaneously delete the transistors M1, M2). Another mode is to write one of the two transistors of the transistor pair 710 and simultaneously delete it for the other transistor.

First, the first mode is described. Referring to FIG. 8 below, FIG. 8 is a schematic diagram showing the operation of the first mode of the non-volatile memory cell unit 700. When the transistors M1 and M2 are simultaneously written, the control gates CG1, CG2, CG3, and CG4 can simultaneously receive the high-level control voltages VCG1 to VCG4. At this time, the floating polysilicon gates fg1, fg2 will attract electrons through the high electric field F-N tunneling effect, while being injected with a plurality of electrons to store data. At the same time, since the transistor M1 is an N-type gold-oxygen half-field effect transistor and the transistor M2 is a P-type gold-oxygen half-field effect transistor, the channel of the transistor M1 will be turned off and the channel of the transistor M2 will be turned on. . In other words, when the data stored in the non-volatile memory cell unit 700 is to be read, only the currents IBL1, IBL2 flowing out of the transistor M1 and the transistor M2 need to be compared by the comparator 720 (in the above example) The current IBL1 provided by the transistor M1 is smaller than the current IBL2 provided by the transistor M2, and the data stored in the non-volatile memory cell unit 700 can be sensed.

The reliability of non-volatile memory cells can also be improved as the sensing boundary is effectively. The memory window therein is equal to the difference in current between one of the non-volatile memory cells and the other transistor.

Of course, when the transistors M1 and M2 are simultaneously deleted, the channel of the transistor M1 will be turned on and the channel of the transistor M2 will be turned off. At this time, the current IBL1 provided by the transistor M1 is larger than the current IBL2 provided by the transistor M2. Similarly, the state of the data stored in the non-volatile memory cell unit 700 can also be known by the comparison result of the comparator 720.

For a description of the second mode, please refer to FIG. 9. FIG. 9 is a schematic diagram showing the second mode operation of the non-volatile memory cell unit 700. When the data is written for the transistor M1 and the data is deleted for the transistor M2, the control gates CG1, CG3, and CG4 can simultaneously receive the high-level control voltages VCG1, VCG3, and VCG4, respectively, and control the gate CG2. At the same time, the low level control voltage VCG2 is received. At this time, the floating polysilicon gate fg1 will be injected with a plurality of electrons at the same time to store data, and the electrons of the floating polysilicon gate fg2 are removed to delete the data. At the same time, since the transistor M1 is an N-type MOSFET and the transistor M2 is a P-type MOS field-effect transistor, the channels of the transistors M1 and M2 will also be turned off. In other words, when the data stored in the non-volatile memory cell unit 700 is to be read, only the current flowing out of the transistor M1 and the transistor M2 needs to be added by the adder 730, and the sum of the currents is obtained. The comparator 740 compares the sum of the currents with the reference current Iref (the sum of the currents is less than the reference current Iref), and the data stored in the non-volatile memory cell unit 700 can be sensed.

Conversely, when data is deleted for the transistor M1 and data is written to the transistor M2 at the same time, the channels of the transistors M1 and M2 will also be turned on, and the current sum will be greater than the reference current Iref by the comparator. 720 compares the current sum with the reference current Iref to sense the state of the data stored in the non-volatile memory cell 700.

In summary, the present invention provides multiple paths in a non-volatile memory cell unit, and injects or removes electrons and holes into the floating gate of the non-volatile memory cell unit by various effects. Complete operations such as writing and deleting non-volatile memory cells. And effectively reduce the operating voltage required for the non-volatile memory cell unit, thereby effectively improving the efficiency of writing and deleting for reading. The non-volatile memory cell unit proposed by the invention can also increase the memory window and reduce data misjudgment caused by charge loss in the floating polysilicon gate caused by excessive storage time or high voltage operation damage, thereby reducing the failure rate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

101, 102, 103, 104, M1~M4, M1c, M1t, M0c, M0t. . . Transistor

210, 300, 400, 500, 600, 700. . . Non-volatile memory cell

310, 320, 510, 710. . . Transistor pair

540. . . Shallow trench isolation

720, 740. . . Comparators

730. . . Adder

VG, VCC, Vdd, V. . . Voltage

I0, I1, I2, IBL1, IBL2, I _BL . . . Current

CMP. . . Comparators

Fg0, fg1~fg4. . . Floating polysilicon gate

CG1~CG4. . . Control gate

CGB, CG. . . Control voltage

PW. . . P-well

NW. . . N-type well

CV1, CV2. . . curve

SW1. . . Transistor switch

C1, C2. . . Coupling capacitor

A1, A2. . . distance

VC1, VC2,. . . Control voltage

BL, PB, SL, PS, BL1, BL2, 521, 522, 631~633. . . Source/bungee

G3, G4. . . Gate

HS, HSB, D, DB. . . Bias voltage

Iref. . . Reference current

FIG. 1 is a schematic diagram showing a conventional non-volatile memory cell of a stacked polycrystalline germanium layer and data sensing thereof.

2A is a schematic diagram showing another conventional non-volatile memory cell unit and its data sensing.

FIG. 2B is a graph showing the relationship between current and storage time when the transistor is turned on.

3A-3C are schematic views showing a non-volatile memory cell unit of a single polysilicon layer according to an embodiment of the present invention.

3D is a schematic diagram of a non-volatile memory cell unit in accordance with another embodiment of the present invention.

4 is a schematic diagram of a non-volatile memory cell unit of a single polysilicon layer according to still another embodiment of the present invention.

FIG. 5A illustrates a non-volatile memory cell unit of a single polysilicon layer according to still another embodiment of the present invention.

FIG. 5B is a schematic diagram showing the process structure of the transistors M3 and M4.

6A is a schematic diagram of a non-volatile memory cell unit of a single polysilicon layer according to a further embodiment of the present invention.

FIG. 6B is a schematic diagram showing the process structure of the transistors M3 and M4.

7 is a schematic diagram of a non-volatile memory cell unit of a single polysilicon layer according to an embodiment of the invention.

Figure 8 is a schematic diagram showing the first mode operation of a non-volatile memory cell of a single polysilicon layer.

9 is a schematic diagram showing a second mode operation of a non-volatile memory cell of a single polysilicon layer.

M1~M4. . . Transistor

300. . . Non-volatile memory cell

310, 320. . . Transistor pair

Fg1~fg4. . . Floating polysilicon gate

CG1, CG2. . . Control gate

PW. . . P-well

NW. . . N-type well

VC1, VC2. . . Control voltage

BL, PB, SL, PS. . . Source/bungee

Claims (20)

A non-volatile memory cell unit of a single polysilicon layer includes: a first N-type transistor pair having a first transistor and a second transistor which are connected in series and in the same state along a read path, The first transistor and the second transistor respectively have a first floating polysilicon gate and a second floating polysilicon gate for respectively as a charge storage medium, wherein the first floating polysilicon gate and the second floating polysilicon gate Extremely electrically or physically isolated from each other, and when the non-volatile memory cell is written or deleted, the first floating polysilicon gate in the first transistor and the second in the second transistor The charge movement in the floating polysilicon gate is the same; a first control gate is coupled to the first floating polysilicon gate through a first capacitive coupling junction; and a second control gate is transmitted through a second A capacitive coupling junction is coupled to the second floating polysilicon gate, wherein a first source/drain junction of the first transistor is coupled to a second source/drain junction of the second transistor, And the first source/dip The second source/drain junction is physically isolated from the external power source. The non-volatile memory cell unit of the single polycrystalline germanium layer according to claim 1, wherein the non-volatile memory cell unit further comprises: a second P-type transistor pair having one mutually parallel and identical type a third transistor and a fourth transistor, the third transistor and the fourth transistor respectively having a third floating polysilicon gate and a fourth floating polysilicon gate, wherein the third floating polysilicon gate and the The fourth floating polysilicon gate is electrically or physically isolated from each other, the third floating polysilicon gate is physically coupled to the first floating polysilicon gate and the fourth floating polysilicon gate is physically coupled to the second floating Polycrystalline germanium gate. The non-volatile memory cell of the single polysilicon layer of claim 2, further comprising: a third control gate coupled to the first and third floating polysilicon gates via a first tunnel junction And a fourth control gate coupled to the second and fourth floating polysilicon gates via a second tunnel junction. The non-volatile memory cell unit of the single polysilicon layer according to claim 1, wherein when the non-volatile memory cell is read, the read current is directly transmitted from the first transistor to the second Transistor. The non-volatile memory cell of the single polysilicon layer according to claim 2, wherein when the non-volatile memory cell is written or deleted, the first, second, third and fourth floating polysilicon gates are The charge movement is the same. The non-volatile memory cell unit of the single polysilicon layer according to claim 2, wherein the first and second transistors have a charge that disappears from the corresponding storage medium, the first The second transistor acts as an error-tolerant cell and automatically performs a self-healing action. The non-volatile memory cell of the single polysilicon layer according to claim 2, wherein the first, second, third and fourth floating polysilicon gates further comprise a protective layer for preventing salidation of a metal salicide. Improve charge retention. The non-volatile memory cell of the single polysilicon layer of claim 2, wherein the first N-type transistor pair and the second P-type transistor are applied to a suitable bias voltage. The difference in current generated is performed to perform a self-referencing mechanism. The non-volatile memory cell of the single polysilicon layer according to claim 3, wherein the first capacitive coupling junction and the second capacitive coupling junction, the first tunneling junction, and the second wearing The tunnel faces are each formed by a transistor. The non-volatile memory cell of the single polysilicon layer according to claim 9, wherein the first and second transistors are native transistors or additionally receive lightly doped drains. LDD) Processed transistors with low threshold voltage characteristics. A non-volatile memory cell unit of a single polysilicon layer, comprising: a pair of transistors having a first transistor and a second transistor which are mutually connected and opposite in shape, wherein the first and second transistors respectively have a first floating polysilicon gate and a second floating polysilicon gate as a charge storage medium, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other; a first control a gate coupled to the first and second floating polysilicon gates via a first capacitive coupling junction; a second control gate coupled to the first and second floating polysilicon gates via a second capacitive coupling junction; a third control gate coupled to the first floating polysilicon gate through a first tunnel junction; and a fourth control gate coupled to the second floating polysilicon gate via a second tunnel junction . The non-volatile memory cell of the single polycrystalline germanium layer according to claim 11, wherein the first and second floating polysilicon gates further comprise a protective layer covering the formation of a salicide to promote charge preservation. force. The non-volatile memory cell of the single polysilicon layer according to claim 11, wherein the first floating polysilicon gate and the second floating polysilicon gate are written or deleted when the non-volatile memory cell is written or deleted. The poles move differently. The non-volatile memory cell of the single polysilicon layer according to claim 11, wherein the first floating polysilicon gate and the second floating polysilicon gate are written or deleted when the non-volatile memory cell is written or deleted. The poles move the same. The non-volatile memory cell of the single polysilicon layer according to claim 14, wherein the first transistor is an N-type native transistor or an additional lightly doped drain (lightly doped drain, LDD) Process of low threshold voltage transistors. A non-volatile memory cell unit of a single polysilicon layer, comprising: a first P-type transistor having a gate and a first source/drain; a second P-type transistor having a gate and a first source/汲An N-type transistor pair having a third transistor and a fourth transistor connected to each other, wherein the third transistor and the fourth transistor respectively have a first floating polysilicon gate and a second a floating polysilicon gate, and the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other; a first coupling capacitor having one end connected to the gate of the first transistor and connected to the gate a first floating polysilicon gate, the other end of which receives a first control voltage; and a second coupling capacitor having one end connected to the gate of the second transistor and connected to the second floating polysilicon gate, the other end receiving A second control voltage. The non-volatile memory cell of the single polysilicon layer of claim 16, wherein the first transistor further has a second source/drain, and the second transistor also has a second source/drain. And the second source/drain of the first transistor is coupled to the second source/drain of the second transistor. The non-volatile memory cell of the single polysilicon layer according to claim 16, wherein the first floating polysilicon gate and the second floating polysilicon gate are further covered with a protective layer for preventing metal halide formation. Charge retention force. The non-volatile memory cell of the single polysilicon layer according to claim 18, wherein the third and fourth transistors are N-type native transistors or additionally receive lightly doped bucks (lightly doped) Drain, LDD) process of low threshold voltage transistors. The non-volatile memory cell unit of the single polysilicon layer described in claim 16 wherein the first and second coupling capacitors are constructed in a P-well in a deep N-well (P-well) )in.