TW201140588A - Non-volatile memory cell unit - Google Patents

Abstract

An only-one polysilicon layer non-volatile memory unit cell is disclosed. The non-volatile memory unit cell includes a first N-type transistor pair and a first and a second control gate. The first N-type transistor pair includes a first and a second transistor with same type and connected along a read path. The first and the second transistors have a first floating gate and a second floating gate to serve as charge storage mediums, separately. The first control gate coupled to the first floating gate through a tunneling junction and the second control gate coupled to the second floating gate through the other tunneling junction. A first source/drain junction of the first transistor is coupled to a second source/drain junction of the second transistor and the first source/drain junction and the second source/drain junction are physically isolated from external power supplies.

Description

201140588

Uyouio 32928twf.doc/I VI. Description of the Invention: [Technical Field] The present invention relates to a structure and a method for a non-volatile memory cell of a single polycrystalline layer, in particular to an improved polycrystalline layer The reliability and sensing structure and method of the non-volatile memory cell unit. [Prior Art] '., ' φ Non-volatile memory is a type of memory that can retain its stored data even when the memory is not powered. In today's technology, non-volatile memory can be roughly divided into two types, which are read only memory (ROM), and the other is flash memory. Referring first to Figure 1, there is shown a schematic diagram of a conventional stacked polycrystalline germanium layer non-volatile memory cell unit and its data sensing as disclosed in U.S. Patent No. 5,973,957. Among them, the floating φ-transistor gates of the transistors 1〇1 and 1〇2 for storing data receive the same voltage VG and correspondingly generate currents II and 12. The comparator CMP detects the data stored in the non-volatile memory cells (the transistors 101, 102) by comparing the currents flowing through the transistors 1〇3, 1〇4 by the currents II and 12. The transistors 1〇3 and 1〇4 are connected in a diode structure and connected to the operating voltage VCC. This method of data sensing mainly uses the memory cell as the source of the reference current. In this practice, the 'sensing margin' can be received by a dummy reference memory cell to receive a similar bias voltage, and the same reference temperature cell has the same temperature sensitivity as the actual memory cell. And layout 201140588

\J7〇\J l\J j2928twf.doc/I Symmetrical reliability on the spatial arrangement. The non-volatile memory cell unit is greatly improved. Fig. 2A shows the schematic diagram of U.S. Patent No. 6,950,342 memory cell unit and its data sensing. Not X. The transistor singularity 210 includes a capacitor using a transistor, a capacitor, and a transistor M1 connected to a voltage V. The transistors Mlc and Mlt of the eighth are respectively coupled to the received =, W to the floating poly (four) pole Fgl, the crystal hall, the dirty respectively: the received voltage VGC, VGt to the floating multi-corrector Fg0. Current, the measurement 220 is measured by the current Π ' flowing from the transistor button and the biliary to sense the non-volatile memory cell unit 21G _ stored data = the sense of the conventional non-volatile memory cell unit Measuring the boundary can also be improved by comparing the current difference between the actual memory cell and the virtual memory cell. It is worth mentioning that the non-volatile memory cell unit 〇 after a long period of tributary storage or after repeated reading and writing and erasing, will be due to the gate oxide of the transistor Ml or M0 (gate 〇 Xide) A phenomenon in which damage occurs due to damage (secret). When the above leakage phenomenon occurs, the current when the transistor 1^1 or 1^ is turned on will decrease as the curve C1 as shown in Fig. 2B decreases with the storage time. As a result, the distance A1 between the current curve LV1 when the transistor M1 or M〇 is turned on and the current curve CV2 when it is turned off decreases to the distance A2 as the storage time increases. Along with this, the sensing result of the current sensor 22A may cause an error such that the data stored by the non-volatile memory cell 210 is misinterpreted.

32928twf.doc/I 201140588 In order to make the reading data of non-volatile memory cells correct, a so-called memory window is an important parameter for non-volatile memory cell design. There are a number of parameters that affect the memory window example & memory cells and reference device (reference device) does not match (for example, | cell and reference device layout, temperature or operating bias), non-volatile notes The floating cell of the emotional cell is surrounded by a floating polysilicon gate (such as a floating polysilicon gate oxide layer or a severe leakage path of a sidewall spacer). There are various techniques for solving the above problems to enhance the memory window of the non-volatile memory cell unit, respectively. SUMMARY OF THE INVENTION The present invention provides three non-volatile memory cell units in which two identical memory elements are included in a non-volatile memory cell using a predetermined connection = to enhance the sensing boundary. Under this condition, all three non-volatile memory cell units can effectively increase the memory window and effectively compensate for the leakage caused by storage. _ The present invention proposes a non-volatile memory cell of a single polysilicon layer, including a first-type transistor pair and a first- and second-control gate: a crystal, the pair having a read-by_read and a homotype (4) The jth body's first transistor and the second transistor respectively have a third X and a second floating (four) gate to serve as an electrical storage medium, respectively! 'The towel--floating polycrystalline and the physical isolation of the first, and when the non-abbreviated, the first-floating polycrystal in the first transistor

201140588 098016 32928twf.doc/I The charge movement in the second floating polysilicon gate in the gate and the second transistor is the same. The invention further provides a non-volatile memory cell of a single polysilicon layer comprising a pair of transistors and first, second, third and fourth control gates. The pair of transistors has a first transistor and a second transistor which are mutually connected and opposite in shape, wherein the first and second transistors respectively have a first floating polysilicon gate and a second floating polysilicon gate Charge storage medium. The first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other. The first control gate is coupled to the first floating polysilicon gate through the first coupling junction. The second control gate is coupled to the second floating polysilicon gate through the second coupling junction. The third control gate is coupled to the first floating polysilicon gate through the first tunnel junction. The fourth control gate is coupled to the second floating polycrystalline silicon gate through the second tunneling junction. The invention further provides a non-volatile memory cell unit comprising a first P-type, a two-P-type transistor, an N-type transistor pair, and first and second coupling capacitors. The first P-type transistor has a gate and a first source/drain. The second P-type transistor has a gate and a first source/drain. The N-type transistor pair has a third transistor and a fourth transistor connected in series with each other, wherein the third transistor and the fourth transistor respectively have a first floating polysilicon gate and a second floating polysilicon gate, and the first floating The polysilicon gate and the second floating polysilicon gate are electrically or physically isolated from each other. One end of the first coupling capacitor is coupled to the gate of the first transistor and coupled to the first floating polysilicon gate, the other end of which receives the first control voltage. The second coupling capacitor has one end connected to the gate of the second transistor and coupled to the second floating polysilicon gate, and the other end receiving the second control power 201140588

υ^δυιο 3292Stwf.doc/I pressure. Based on the above, the non-volatile memory cell provided by the present invention can pass through FN tunneling, Band_t〇_Band tunneling Hot Electron (BBHE), and band-to-band tunneling induction thermoelectric hole (Band). -to_Band tunneling Hot Hole (BBHH), substrate hole and Channel Hot Electron (CHE) method to inject or remove electrons or holes to achieve the effect of writing and deleting data φ. The non-volatile memory cell provided by the invention is effective in reducing the electric power required to write the 'deletion of the sufficiency and effectively compensating for the leakage phenomenon occurring in the stored data. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. Embodiments FIG. 3A is a schematic diagram of a single polysilicon layer non-volatile memory cell unit 300 in accordance with an embodiment of the present invention. In some non-volatile memory cell technology, two or more layers of polycrystalline germanium are often used to process and multiply and achieve non-volatile memory purposes. In the present embodiment, a non-volatile memory cell unit which is more cost-effective and more suitable for a single layer of polysilicon layer of built-in memory is proposed. Referring to FIG. 3A, the non-volatile memory cell unit 3 includes a transistor pair 31A and a control gate CG1=CG2. Among them, the transistor pair 31〇 has a transistor group connected in series and the transistor M2, and the transistor Μ1 and the transistor M2 have floating polysilicon gates fgl and fg2, respectively. And floating polysilicon gates fgl and fg2 he 201140588

Weuio j2928twf.doc/I ^ Physically or electrically isolated from each other. The control side pole (10) is connected to the oceanic polycrystalline stone gate by the capacitive hybrid "face". Similarly, the control gate (10) is lightly connected to the floating polycrystal dream gate through the other-capacitive light interface. The control gate CG CG2 receives the control cake vc Bu VC2, respectively, and transmits the corresponding hybrid (4) (4) να, vc2 _ to the floating polycrystalline slab gate fgl and fg2, wherein the control gate CG (10) can be Use capacitors to construct, such as p+ and N-wells (NW) or N+ and N-junctions. And 'this capacitance can be read by the crystal = the structure / the base of the transistor, the drain and the source The poles are interconnected to form the first end of the capacitor and utilize the second end of the capacitor between the capacitors. In the present embodiment, 'because of the N-type well as the base of the ?-type gold-oxygen half-field effect transistor because The base of the N-well can receive a positive voltage isolated from the p-type well p-type substrate, Strate, and is therefore more suitable for forming the above-mentioned clay spoon capacitance. In this eye, in this embodiment, the transistor pair The transistors M1 and M2 in 31〇 are all N-type gold oxide half field effect transistors and are also electronically accepted. The operation of writing or deleting. That is to say, 'the operation of writing and deleting the lines on the transistors Μι and M2 is the same. If the electrons are stored in the oceanic polymorphic hair-closing poles fgl and fg2, The volatile memory cell unit has a higher threshold voltage and a lower on-current IBL (the current flowing from the end point 3B and !51^) when there is no electron storage in the flip-flops fgl and fg2. As shown in the figure, this means that the floating polycrystals and the electrons stored in fg2 can reduce the conduction current Ibl of the transistors M1 and M2 flowing from the terminals BL and SL. '" 201140588

098016 32928twf.doc/I In the design of the non-volatile memory cell 300, the problem of charge retention is a problem that needs to be taken into account, especially in the case of more severe memory leakage. In the actual case, as shown in Fig. 3C, the electrons originally stored in the floating polysilicon & electrode will be lost to the floating polysilicon gate fg2 of the transistor %2 without any electrons. In this case, the channel below the floating crystal gate fg2 of the transistor milk will be turned on unless there is an external switch that is closed with M2. In order to avoid the above situation, ‘=====sex_sense=the path to be read);===::: love. In a more careful analysis of the error rate, the memory matrix encapsulates the polycrystalline (four) pole memory transistors, and the transistors are erroneous. And the memory is corrected by an F1 error rate, where F1 is the error of the transistor M1 without the external serial connection, the reliability of the good memory_IP, and the transistor m is added to the circuit of the electric Japanese body M2 Then take the road · _ 1 , plus (four) Λ County to construct a memory cell structure of 1 bit, under this new money, remember the total error rate of IP _ IP F2 = 1 ~ (l-f2) n; rate. ', F2 is an error when there is a transistor connected in series

201140588 υ^δυιο ^2928twf.doc/I The error rate F2 when the transistor 外1 is connected in series is improved relative to the error in the experience of the electron crystal without the external series connection. That is to say, the transistor and the milk form a memory cell that is fault-tolerant and acts from the action of the wire when the electrons stored in the crystal or the dish are in an enemy state. Figure 3D is another embodiment of a non-volatile memory cell of the present invention. In the present embodiment, human crystals M3, M4 are additionally added, and the type of transistor M3, M4 of the transistor pair 320 t is opposite to that of the transistor milk and ritual. That is to say, in the present embodiment, the transistor and the legs are all P-type gold-oxygen half-field electric solar celestial bodies, and are connected in parallel with each other (e. (10) 匕 parallel) and connected to the signal BLp. It can be seen from the above description that the transistor ΝΠ, M2 can be formed in the p-type well (p_weii) pw of the integrated circuit, and the transistors M3, M4 can be formed in the N-type well of the integrated circuit (N-well ) NW. Transistors M3, M4 are commonly used for wearable applications. Usually, the component size of the CG2 and the transistor group, the transistor M3, and the M4 are the smallest relative to the control gate. Alternatively, transistors M3, M4 can also be configured in the form of tunneling junctions to provide electron tunneling into/out of the floating gate (polysilicon layer). A tunneling junction can be considered as an area where electrons or charges pass through/in; and a coupling junction is used for the purpose of capacitively coupling. Incidentally, the transistors M1 and M2 in this embodiment may be a native device having a lower threshold voltage or receiving an additional lightly doped Drain (LDD) for processing. Generating 201140588

098016 32928twf.doc/I The transistor Prisoner M1, M2 is a read transistor. If the cell has a pure threshold voltage, this can effectively reduce the non-burst memory cell for reading. The time needed. And ^ In order to ensure the high quality of the non-volatile memory cell unit 3, -, the formation of the protective layer of oxides (salicide pl. fine iQn lay = cover on the oceanic multiple (four) gate. This is not only Eliminate the money segment process from the interlayer dielectric (Inter Layei. Dieleetri (:, ILD) mechanical external 'and avoid metal oxides along the sidewall void wall caused by floating polycrystals short circuit to the source of metal oxide or In the above, the 'retention of the electric charge is effectively improved.' Please continue to refer to the figure. The following is the operation of writing, deleting, and reading the non-volatile memory cell unit 3 to make this In the field and usually the knowledgeable person can understand the application of the forward memory cell unit. ~ When controlling the non-volatile memory cell unit _, the control idle voltage (10), CG2 receives the high voltage control voltage % i, v ( : 2 and through the transfer junction, the control voltage VC1, VC2 are divided into the capacity _ to ^ polysilicon gates fgl and fg2. By this, the floating polycrystalline stone gate gate planer and fg2 will attract electrons and store the majority Electronic. Here, due to control idle C G Bu CG2 also controls Lai να and VC2 to floating polycrystalline slab gates fg3 and fg4. Therefore, in the case where 32 〇 of transistor pairs are arranged, Lang M3 and M4 also adsorb a large number of electrons. Note this, because in this embodiment, the transistors M1 and M2 are N-type gold-oxygen half-field effect transistors. Therefore, the floating polysilicon is applied to the gates fgl and fg2.

201140588 uy»uio j2928twf.doc/T will make the channels of transistors Ml, M2 appear more closed state. The opposite 'transistors M3 and M4 are P-type gold-oxygen half-field effect transistors. Therefore, the electrons adsorbed on the floating polycrystalline slab gates fg3 and fg4 will make the channels of the transistors M3 and M4 appear more. Open state. Under this arrangement, the N-type metal oxide half field effect transistors M1, M2 are designed to be connected in series. That is to say, one of the source or the drain of the transistor M1 is connected to the unconnected end of the source or the drain of the transistor M2 (which may also be said to be the floating terminal of the source or the drain). point). In contrast, p-type MOS field-effect transistors M3, M4 are designed to be connected to each other. The terminals pb, PS are respectively coupled to one of the source or the drain of the transistors M3, M4. The end point BLp is connected to the source or the other unfloating end of the transistor M3, M4. When reading for the non-volatile memory cell unit 300, a voltage can be supplied to the other terminals by the source/no-pole BL, PB, PS, and BLP of the transistors M1, M3/M4, and in the transistor. The source/drain SL and PB/PS of M2 and M3/M4 generate corresponding currents. When the data stored in the non-volatile memory cell unit 300 is sensed, the current generated by the helper electrodes SL, PB/PS of the transistors M2, M3/M4 can be received with a threshold value (reference current Iref) The comparison is made to determine the data (logical high level or logic low level) stored in the non-volatile memory cell unit 300. In the case where the transistor pair 32G is disposed, it can also be compared with the reference current by receiving the current generated by the source electrode SL of the transistor M2, and can also be stored in the non-volatile memory cell unit. 〇中(4) What is the data in the channel of the transistor? When reading the p-type transistor pass 12 20^40588 3-, the data in the channel is completed by comparing the current bought by the transistor M3/M4 source/drain PB, ps with the reference current lref. . In addition, the non-volatile memory cell unit 3 also reads the current generated by comparing the source/丨 and the terminal SL of the transistor m2 with the pB, ps of the transistor M3/M4 source/drain. /'il to know the memory cells that provide self-reference values. ~

Please pay special attention here, if one of the transistors Ml, M2 (for example, the damage of the germanium transistor M2 is caused by the occurrence of its gate oxide layer due to the natural oxide layer damage storage time is too long or the periodic oxide layer When the ink is broken by the electric ink, the electrons adsorbed on the floating polycrystal fg2 of the transistor M2 will be reduced by the leakage. That is, the pass 1 may not be kept in the closed state. , = ί : ::: The reading action of the non-volatile memory cell 300 produces the transistor M1. Although the channel of the transistor 可能 2 may not be turned off, the /, and 枉ST, the channel remain closed. The state, so the transistor M2 = produced; the current does not change due to the transistor core: i. Therefore, non-extraordinary, the crystal (10), will not cause errors. This material is written or deleted The action of the Iff memory cell 300 is the same as the movement of the carrier. The electric current in the gate of the oceanic polysilicon gate is as follows. Please refer to FIG. 4, and FIG. 4 is a non-volatile memory cell unit. Non-volatile record of another embodiment Single cell _: Hess and the previous embodiment is different dagger dagger months earlier Cloth 400 further comprises a control gate CG3, CG4 13.

-, 2928twf.doc/I 201140588 is coupled to floating polysilicon gates fgl, fg3 and fg2, fg4 through different tunneling junctions, respectively. The control gates CG3 and CG4 can also be constructed by capacitors, but can of course be constructed by coupling the transistors into capacitors. Under the above structure, tunneling junctions are formed in the control gates CG3 and cG4 instead of the transistors M3 and M4. Transistors M3 and M4 act as read transistors to provide a path for data reading without being stressed by high voltages. Among them, the tunnel junction is susceptible to high voltage and is damaged.非 曰曰 Referring now to Figure 5A, Figure 5A illustrates a non-volatile s-recall cell unit 500 in accordance with yet another embodiment of the present invention. The non-volatile memory cell unit 5 includes an electrical integrated pair 510 (one of the M1, M2 source or the drain is connected to each other), the electric body M3, M4, and the coupling capacitor c, and the C2e transistor pair has a mutual Serial transistors] and M2. The transistors ^^ & M2 have a floating polycrystalline gate fgl and a floating polygate gate fg2, respectively, and the floating polycrystalline gate gate fg 1 and the floating polycrystalline gate gate fg 2 are mutually connected to each other. Physical or electrical isolation. One end of the combined capacitor C1 is connected to the gate of the transistor M3 and capacitively coupled to the floating polysilicon gate fgl, and the other end of the coupling capacitor 接收 receives the control voltage CGB. In contrast, one end of the coupling is connected to the transistor M4 (four) and capacitively coupled to the floating polycrystalline whisker fg2, and the other end of the coupling capacitor C2 receives the control voltage CG. In addition, the non-volatile memory cell unit 500 is connected to the transistor switch SW1. When the crystal switch SW1 is turned on according to the word line signal WL, the voltage is supplied to the transistor pair 510. It is worth mentioning that 'the transistors M3 and M4 r have both the source 14

201140588 uysuio 32928twf.d〇c/I A general 4-terminal transistor with bungee. Please refer to FIG. 5a and FIG. 5B simultaneously. FIG. 5B is a schematic diagram showing the process structure of the transistor M3 & M4. As can be seen from Fig. 5B, the transistor M3 has only the gate G3 and the source (or drain) 521. That is, the transistor M3 does not have a drain (or source). Similarly, the transistor M4 has only the gate G4 and the source (or drain) a]. That is to say, the transistor M4 does not have a drain (or source). The area of the immersion (or source) which should be used to form the transistors M 3 and M4 is replaced by shallow trench isolation (STI) 54 。. In the case of the real p, the electric red C2 can also be used to form a capacitor or a transistor (for example, P (di) oxygen + transistor) with a capacitor. Way to form. And, the voltage required by the unit, the data of the cell body M, M2 is the same type of electric crystal face M3 in the 510 face, and the P-type gold oxygen half field field effect transistor in the cell, the transistor is in the present Greedy example t, d has 5 yuan. The actual operation aspect of °. When writing, the floating polycrystalline gate gate fgl step of the needle is removed. That is, when the two 2^ floating polysilicon gate fg2 and the CGB are high voltage (for example, the control voltage of 65 angstroms (A) received by each C1 of the 85 volt packet) for data writing, the floating polysilicon gate is The thickness is CG for low voltage (for example, 〇 'volts ^' coupling capacitor C2 receives the control voltage, the coupling capacitor C1 is connected to the 'X for data deletion. Careful 8.5 volts to the floating polysilicon 201140588

Υνβυιο j2928twf.doc/I Gate fgl, and HSB in M3 and j: xr agent π to make the floating polycrystal remnant by F_N, wear into = voltage, to complete the miscellaneous. The relative number of electronic genius Newton moves the polycrystalline stone to the gate of the extreme fg2, and in the book and the = well, the volt voltage is applied, so that the floating polycrystal dream gate thief is absorbed by the (9) wear-through effect Electronic to complete the deletion of the data. The source (or the poleless) of the crystal M3 receives the bias voltage (not shown in Figure 5Α). Such a · , Ϊ - '+' ΛΑ Kp «e, with the cake book tunnel belt 2 The above-mentioned bias voltage is set by the V to π tooth _ should be hot electron ribs to make the electronic injection float, To speed up the writing operation. On the other hand, the transistor ^ ^ pole (or recording) can receive the bias of the Hs (for example, 8 5 , is receiving a low voltage (for example, 2 volts > bias voltage hS and in its electric M4 The N-well receives 8.5 volts. This 2 volt dust (4) 有助于 helps electricity = Μ 4 to inject the floating polycrystalline shi gate fg2 by means of the base hole M (subsu 'zero 〇 her) The hole (moved to speed up the removal of the tribute. 8:5 volts biased electric house η § promoted. The body leg is pulled out by its floating polycrystalline dream thief to remove the electron ^ and can be completed by this. In addition, the source (or the pole) of the transistor M1 of the transistor 510 can receive a low voltage (for example, 0 volt) bias voltage DB i to float to assist the writing of the transistor M1. Action. The source (or no pole) of the transistor touch can also receive the bias voltage of low power (for example, pressure D or _ 浮 o oa (4), or also ^ 201140588 uysuic, 3292Stwf.doc/I 〇 符) D, the effect of the injection of the hot hole will be == transmitted through the belt pair with the induction gate fg2 to accelerate the data deletion. "Electronics} to the oceanic polycrystalline stone road Ϊ = Rongyi is constructed in the integrated body, and the two wells, the control voltage CGB, CG will be biased; the displacement of the two t bits. The above control voltage CGB, CG with pressure HSB, Hs between 〇~8 5 volt sample pressure

425~=Γ麟驾HSB, Hs _ move to between the nest and another. 1 volt. That is to say, the voltage amplitude required for the main deletion of the non-volatile memory cell unit 500 can be added to the p-type well in the deep N-type well in the integrated circuit because the negative bias can be short: === When the non-volatile memory cell 500 is in the near-reading operation, only the fourth conductive transistor switch SW1 supplies the voltage (4) to the transistor=1 M2, and the transistor, M2 receives the bias voltage, and the 偏压The endpoints receive and compare the currents, respectively, to successfully access and read the data stored in the glow memory cell unit 500. At the same time, the bias voltages CSB, HS, control voltages cgb, CG can be set to be maintained at a logic high voltage level (e.g., 1.8 volts) used by a general integrated circuit. Incidentally, the transistor Μ; ι, m2 in this embodiment is an N-type MOS field effect transistor. In general, N-type MOS field-effect transistors have twice the driving current of a p-type MOS field effect transistor. Therefore, when reading, the N-type gold-oxygen half-field effect transistor has a faster electron movement rate and can sense the correct storage data faster. 17 201140588

保存^ουιο j2928twf.doc/I β non-volatile memory cell unit 500's preservation power and reliability are also greatly improved' because the sensing boundary is related to the off current of the transistor M1 and the difference between the on-current of the transistor M2. (In the floating polysilicon gate of the transistor, fgl is in the data write mode and the floating polysilicon of the transistor M2, the pole fg2 is in the data deletion mode. If the original floating polycene gate fgl electrons gradually floats more When the spar 夕 gate pole fgl is lost, the non-volatile _ _ unit. 5 〇〇 can still work normally due to the large sensing boundary (greater than the additional reference current · flow Iref generation mechanism). The change of the current test rainbow trout will not cause any trouble. In the well-known Φ technology field, the reference current ^ is between the on current and the off current, which reduces the ❹ ❹ and makes the fine boundary smaller than the pre-operative The sensing boundary of the embodiment of the present invention is equal to the difference between the on current and the off current. Referring next to FIG. 6A, FIG. 6A is a schematic diagram of a non-volatile memory cell unit 6 according to a further embodiment of the present invention. Unlike the non-volatile memory cell unit of the previous embodiment, the transistor of the non-volatile memory cell unit _V[3 and M4 is a transistor having both a immersion and a source. Please refer to FIG. 6B at the same time. FIG. 6B is a schematic diagram showing the process junction of the transistors M3 and M4. The transistor %3 has a gate G3, a source (or a gate), and a drain (or source) 631, 632, a transistor. M4 has a gate G4, a source (or drain) and a drain (or source) 633, 632. The transistors M3, M4 share a drain (or source) 632. The gate of the transistor M3 is connected to The capacitor ci is connected to the control voltage CGB, and the gate 〇4 of the transistor M4 is connected to the capacitor C2 and connected to the control voltage cg. In addition, the transistor 18 for the non-volatile memory cell unit 6 201140588

Uysuio 32928twf.doc/I write and transistor M2 _ data deletion, electricity _ M3 3.3 volt bias power wish coffee, and the transistor core mouth. = partial factory firm voltage HS 'this electron through the electron crystal _ The ΓΓ effect is removed by the floating polycrystalline (four) thief, and the transmissive M3 is more efficient by the channel hot electrons to hide from the floating polycrystalline stone to the fgl'.

Pure 7, Mesh 7 & _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Non-volatile memory cell unit; 7(10) includes transistor pair 710 and control gates CG1, C(}2, (10), and ca4. Pair 710 has a group of transistors that are connected in series and opposite in shape, and = steroid M2. The transistor group and the moving group respectively have a floating polycrystalline dream room 4, _fg2, and the floating polysilicon gates fgb隹2 are physically s% isolated from each other. In this embodiment, the transistor] να is an n-type gold oxygen half field. ϊ ϊ crystal ' and the transistor milk is a p-type MOS half-field effect transistor, and the electric 曰曰 ΜΙ, M2 are coupled to the signal S1, the transistor M1 and the transistor Μ 2 source / no pole BL1, BL2 are not coupled In the same manner as all the foregoing embodiments, the control gates CG1, CG2, and CG4 can be implemented by capacitors, and the power pads can be constructed by a transistor or a coupling junction that is consumed as a capacitor. When the non-volatile memory cell 700 is written and deleted, the non-volatile memory cell 700 of the present embodiment can be divided into two modes. One of the modes is for the transistor pair 710 at the same time. The two, the transistor is written or deleted (that is, the transistor Xie, Μ 2 with Write or delete). Another model is for the transistors of the two 19710

201140588 υ^ουιυ j2928twf.d〇c/ One of the transistors is written and synchronized for another deletion. Gastric administration First, the first mode will be described. Referring to Fig. 8, the following description shows the non-volatile recording unit and the f-plane operation. When the transistors M1 and M2 are simultaneously written, the control CG CG2, CG3, and CG4 can simultaneously receive the high-level control VCGKVCG4. At this time, the floating polycrystalline slab gate is unloaded, and fg2 attracts electrons through the tunneling effect of the electric field F-N, and at the same time, a plurality of electrons are injected to store data. At the same time, since the transistor M1 is an N-type gold-oxygen half-field drinking crystal and the transistor M2 is a P-type gold-oxygen half-field effect transistor, the channel of the electric body M1 will be closed and the channel of the transistor M2 will be Turn on. In other words, when the data stored in the non-volatile memory cell unit 7 is to be read, only the current IBU" and IBL2 flowing out of the transistor M1 and the transistor M2 need to be compared by the comparator 72〇 (in the case of In the above example, the current IBL1 provided by the transistor M1 is smaller than the current IBL2) provided by the transistor M2, and the data stored in the non-volatile memory cell unit 7 can be sensed. The reliability of non-volatile memory cells can also be improved as the sensing boundary is effectively. The memory window therein is equal to the difference in current between one of the non-volatile memory cells and the other transistor. Of course, when the transistors M1 and M2 are simultaneously deleted, the channel of the transistor M1 will be turned on and the channel of the transistor m2 will be turned off. At this time, the current IBL1 supplied from the transistor M1 is larger than the current IBL2 provided by the transistor M2. 'Also through the comparison result of the power piracy 720, you can also know the non-201140588

υ^〇υ 1 υ 32928twf.doc/I Volatile memory cell 7λ About the second mode: the state of the stored data. For the memory cell unit 7 (see ^, please refer to Figure 9, Figure 9 shows the non-volatile crystal crystal Wei:: Schematic diagram of the operation of the seed mode. When the gate is controlled for the time division, the data is erased at the same time. The control voltages Vc and CG4 can be received separately from the daily guards.

At the same time, the low-precision 3 and VCG4 are received, and the gate gl2 gate fgl is controlled to be (4). At this time, the floating polycrystalline 曰 曰 卩 卩 卩 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数 多数The channels of the transistors 1^1 and M2 will be etched six times, and the readout of the non-volatile memory cell unit 700, the '*# tributary day ^' only needs to flow out the transistor M1 and the transistor M2. The second=error is added by the adder 730, and the sum of the currents is obtained, and then the comparison between the sum of the current and the reference current 1 ref (the sum of the currents is smaller than the reference current Iref) can be sensed. Data stored in the volatile memory cell unit 7〇〇.曰Right 'When the data is deleted for the transistor mi and the data is written to the same time, the channels of the transistors M1 and M2 will be the same. The current sum will be greater than the reference current iref, and the comparison will be 790. ～°° The sum of the sum of the retracted bamboo currents and the reference current Iref is also sensed to sense the state of the data stored in the non-volatile memory cell unit 700. , 'vT, above, the present invention provides multiple ways in non-volatile memory cells, and uses various effects to make electrons and holes to non-volatile memory.

Uy δυ i o j2928twf.doc/I Floating-gate injection of cell unit You write and edit the cell of a unit. The operating voltage required for the forwarding memory cell is: And effectively reduce the non-volatile memory running ίί: The non-volatile memory cell unit proposed by the invention can also reduce the operation due to excessive storage time or high voltage operation; the data misjudgment caused by the charge loss in the second S-moving polycrystalline Na Two losses

Although the present invention has been disclosed in the above embodiments, the scales thereof are used to define the invention, and any of the techniques of the present invention (4) f knowledge: within the spirit and scope of the invention, when some changes can be made and retouched, the protection of the present X is protected. ® is subject to the definition of the application for the special purpose of the money. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing a conventional stacked multi-(four) layer non-volatile memory cell unit and its data sensing. One

Figure 2A is a schematic illustration of another conventional non-volatile memory cell single-substance sensing. Figure 2B is a graph showing the relationship between current and storage time when the transistor is turned on. 3A to 3C are schematic views showing a non-volatile memory cell unit of a single polysilicon layer according to an embodiment of the present invention. Figure 3D is a schematic illustration of a non-volatile memory cell of another embodiment of the present invention. ~ Figure 4 illustrates a non-volatile portion of a single polycrystalline germanium layer in accordance with yet another embodiment of the present invention.

201140588 uysu i o 32928twf.doc/ Schematic diagram of the I-memory cell unit. Fig. 5A is a view showing a non-volatile memory cell unit of a single polysilicon layer according to still another embodiment of the present invention. FIG. 5B is a schematic diagram showing the process structure of the transistors M3 and M4. 6A is a schematic diagram of a non-volatile memory cell unit of a single polysilicon layer in accordance with a further embodiment of the present invention. FIG. 6B is a schematic diagram showing the process structure of the transistors M3 and M4. Fig. 7 is a schematic view showing a non-volatile memory cell unit of a single polysilicon layer according to an embodiment of the present invention. Figure 8 is a schematic illustration of the first mode operation of a non-volatile memory cell of a single polysilicon layer. Figure 9 is a schematic illustration of a second mode operation of a non-volatile memory cell of a single polysilicon layer. [Description of main component symbols] 101, 102, 103, 104, M1 to M4, Mlc, Mlt, MOc, MOt: transistors 210, 300, 400, 500, 600, 700: non-volatile memory cells 310, 320, 510, 710: transistor pair 540: shallow trench isolation 720, 740: comparator. 730: adder VG, VCC, Vdd, V: voltage 23

.2928twf.doc/I 201140588 10, η, 12, IBU, IBL2, IBL: Current CMP: Comparator

FgO, fgl~fg4: floating polysilicon gate CGI~CG4: control gate CGB, CG: control voltage PW: P-well NW: N-well CV1, CV2: curve SW1: transistor switch

Cl, C2: coupling capacitor

Al, A2: distance VC1, VC2: control voltage BL, PB, SL, PS, BU, BL2, 52, 522, 631 ~ 633: source / no pole G3, G4: gate HS, HSB, D, DB: Bias voltage

Iref: Reference current φ 24

Claims (1)

201140588 υ^δυιο 32928twf.doc/I -c - a non-swinging first N-type transistor pair of a single polycrystalline layer, having two cryptic units, including: and a first type of homomorphic The crystal and the read path are connected in series with each other, and the second transistor has a -th == transistor, and the first transistor has two floating polycrystalline slab gates as f-moving polycrystalline slab gates and a first a floating polycrystalline slab gate and the second floating, storage medium, wherein the first rational isolation, and when the non-volatile, 矽 gate is electrically or electrically, the first in the first transistor The second floating polysilicon is written or deleted by the crystal cell, and the second electric first control gate is the same; the first floating polycrystalline stone夕 极 ; ; ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -罘 / / / original Λ and pole junction, and the first source / 盥竽 盥竽 when the source / wire junction is physically isolated from the external power supply. The non-volatile layer of the single polycrystalline layer described in item 1 of the first aspect of the present invention includes: - a pair of p-type transistors, which are mutually coupled and identical a second transistor and a fourth transistor, the third transistor and the fourth transistor having a second floating polysilicon gate and a fourth floating polysilicon gate/the third floating The polycrystalline slab gate and the fourth floating polycrystalline slab gate are electrically or physically isolated from each other, and the third floating polycrystalline slab is open to the physical physics 25 201140588 v ^ 2928 twf.doc/I The polysilicon electrode is electrically coupled to the second floating polysilicon gate. 3. For example, the single-multiple (four) hair cell unit according to item 2, which further includes: non-glow to the third control gate, coupling two floating polycrystals through a first tunnel junction a single-gate non-recalling unit as described in the application for the second paragraph, wherein the non-volatile memory cell unit When the beta current is conducted directly from the first transistor to the second electrical signal, please refer to the single-multiple (four) layer of the second aspect of the patent scope: when the The deletions are the same. .—4 ton moving multi-turn gate charge transfer cell unit paste two like two pairs, _ memory in the lost time 'the first and the second transistor, ',, an error-tolerant cell and automatically execute self Repair the action. Japanese-style hair ^Please apply for a single (four) layer of non-swings described in item 2 of the patent f (4). Among them, the ...-three and four floating heart enhancements "= prevent the formation of a protective layer of salleide. The non-wave cell of the single polycrystalline layer described in item 2, 201140588 3292Stwf.doc/I f memory cell unit, wherein a suitable bias is applied to the first p-type transistor pair by applying the pair of transistor pairs The difference between the currents generated by the voltage setting is performed to perform a self-referencing mechanism. 9. If the non-volatile memory cell unit of the single-multiple rectifying layer of the third item is applied for, the first-wire joint is applied. The surface and the second electrical interface, the first tunneling junction and the second tunneling junction are respectively formed by a transistor. Μ Μ ί ί W 专利 专利 专利 专利 专利 专利 专利The non-waxing of the layering: 曰2': the cell is early 兀' wherein the first and second transistors are of the native type (-), the Japanese bean or the additional lightly doped peddrain (LDD) process A transistor with low threshold voltage characteristics. 11. A non-volatile memory cell unit of a single polycrystalline dream layer, comprising: a private crystal pair 'having a first electron crystal that is mutually concatenated and opposite in shape, a second transistor, the first one The two transistors respectively have a ^--------------------------------------------------------------------------- The two floating polysilicon gates are electrically or physically isolated from each other; the first control gate is coupled to the first and second floating polysilicon gates via a first capacitive coupling junction; and the second control gate is transmitted through a second The capacitive light-bonding surface is coupled to the first and a floating polycrystalline silicon gate; ☆-the second control gate's through-first tunneling junction is coupled to the first floating polycrystalline silicon gate And the fourth control gate 'transmission-second wear-to-connect surface is lightly coupled to the second 27 z928tw£doc/I 201140588 floating polycrystalline slab gate. 12. If the volatile memory cell unit mentioned in the scope of patent application is in the U range, the A layer of the non-supplemental layer of the A layer is the second, and the protective layer formed by the metal halide (4)-) is prevented. Enhance the non-memory=element of the single-multiple (four) layer as described in Item 11 of the patent application: Charge transfer of the non-volatile memory cell type write pole 2 f-polar polycrystalline stone eve of the opening ceremony 5: Patent Model 31 The single-multiple (four) layer non-or unit cell according to item 11, wherein #the non-volatile memory cell haplotype is written to i: the first-floating polycrystalline (tetra) pole and the second floating polycrystalline stone The electric power of the eve gate is the same. The non-f~~ is also earlier than the single polycrystalline dream layer as described in the middle of the patent scope, wherein the transistor is an N-type native crystal or additionally receives light doping; and the pole (1; ί_Υ) D〇Ped drain, LDD) A low threshold voltage transistor. A non-volatile memory cell unit of a single polycrystalline germanium layer, comprising: a splitting transistor 'having a gate and a first source/> and a pole; a p-type transistor having a gate and a first source/no pole; a β-ray, a pair of transistor pairs having a third transistor and a two-electrode body connected to each other, wherein the third transistor and the fourth transistor respectively have a floating gate, a polysilicon gate And a second floating polysilicon gate, and the 'pre-polysilicon gate and the second floating polysilicon gate are electrically connected to each other 28 201140588 .........32928twf.doc/I or physically isolated; the coupling capacitor, one end thereof Connecting the first one to the first floating-type polycrystalline, the other soil:: body; Second electricity: the second floating polycrystalline, its other end receiving - the second control 挥发 volatilization: note the single (four) layer of non-made, (four) ιΓΓ,:, with the first - transistor has a second source / no body fork , 分铉-1 private day and limbs and Dan Yule two $ crystal of the ^7? /, 曰曰 ^ also has a second source / no pole, and And the first source of the first electric source is recorded to the second source of the second transistor. The secret Lt towel should be specially designed for the non-cell unit of the single (four) layer described in item 16 of the Wei (4), where the first-floating polycrystalline stone gate and the second iiL gate are covered more to prevent the formation of the metal dream compound. To enhance the charge retention. It is also a non-*5e, lt cell unit of the single multi-remediation layer described in item 18 of the patent application scope, and (4) third, fourth telecrystal county] ^ type native nativ:) transistor or additional receiving light Doping is not a Norwegian and suppressing & drain, LDD) system of low low-voltage hybrid crystal. For example, please refer to the non-memory cell of the single polycrystalline layer described in item 16 of the patent scope, where the first and second age capacitors are constructed in the p-well of the deep ö-well (p_well) )in. 29