TWI429918B - Peak voltage detector - Google Patents

Description

Voltage peak detector

The invention relates to a voltage peak detector, in particular to a voltage peak detector capable of accurately determining the highest voltage level.

Referring to FIG. 4, the conventional voltage peak detector 200 includes an analog peak detecting circuit 210, an analog digital converting unit 220, a digital peak detecting circuit 230, a control system 240, and a digital analog converting unit 250. The analog peak detection circuit 210 can receive an input signal and can perform peak detection on the input signal, and output a peak signal. The peak signal is converted into a digital signal by the digital analog conversion unit 220, and the digital signal is further converted by the digital signal. The peak detecting circuit 230 receives the digital signal, and the control system controls the action of the analog peak detecting circuit 210, the digital analog converting unit 220, and the digital peak detecting circuit 230, and finally transmits the output digital signal to The digital analog conversion unit 250 converts the analog signal into an analog signal to achieve peak detection. However, the analog signal of the output cannot completely track the peak value of the input signal, and the peak of the input signal in each cycle will pass through the The circuit and system cause a drop in the output signal, which affects the accuracy.

The main purpose of the present invention is to provide a voltage peak detector comprising an analog buffer, a low pass filter, an amplifier, a comparator, a first switch, a second switch, a first capacitor, a thyristor, a third switch, a flip flop and a charging switch, the analog snubber has a voltage signal input, the low pass filter is electrically connected to the analog buffer, and the amplifier is electrically connected The low-pass filter has a positive terminal, a negative terminal and an output terminal. The positive terminal is electrically connected to the amplifier, and the first open relationship is electrically connected to the amplifier and the comparator. In an extreme, the second open relationship is electrically connected to the negative end of the comparator, the first capacitor is electrically connected to the second switch and the negative end of the comparator, and the OR gate is electrically connected to the second switch And the first switch, the third open relationship is electrically connected to the OR gate and the output end of the comparator, the flip-flop has a pulse input end and a uniform energy end, and the pulse input end is electrically connected to the The output of the comparator, the It is electrically connected to the electrically-apart relationship of the positive terminal of the comparator, the flip-flop of the first capacitor and the enable terminal. According to the present invention, when the charging switch, the flip-flop and the first capacitor are electrically connected, when the output of the comparator outputs a high voltage level, the flip-flop triggers the charging switch. The charging switch can immediately keep up with the voltage level of the positive terminal of the comparator, so that the first capacitor does not overcharge and cause a false positive to the highest level. In addition, the charging switch is combined with the first capacitor. The charging method can greatly reduce the charging time and increase the working efficiency of the circuit.

Referring to FIG. 1 , a preferred embodiment of the present invention is a voltage peak detector 100 for receiving a voltage signal output by a Flexural Plate Wave (FPW) sensor and Detecting its voltage level, the voltage peak detector 100 includes an analog buffer 110, a low pass filter 120, an amplifier 130, a comparator 140, a first switch 150, a second switch 160, and a a first capacitor 170, a gate G, a third switch SW, a flip-flop 180 and a charging switch 190, wherein the analog buffer 110 has a voltage signal input terminal 111 for receiving a voltage signal, the low pass filtering The amplifier 120 is electrically connected to the analog buffer 110. The amplifier 130 is electrically connected to the low pass filter 120. In this embodiment, the amplifier 130 is a non-inverting amplifier. In addition, the amplifier 130 has a first resistor 131 and a second resistor 132 electrically connected to the first resistor 131. The comparator 140 has a positive terminal 141, a negative terminal 142 and an output terminal 143. The positive terminal 141 is electrically connected. The amplifier 130 is electrically connected to the first switch 150 The amplifier 130 and the positive terminal 141 of the comparator 140 are electrically connected to the negative terminal 142 of the comparator 140. The first capacitor 170 is electrically connected to the second switch 160 and the comparator. The negative terminal 142 of the 140 is electrically connected to the first switch 150 and the second switch 160. The third switch SW is electrically connected to the OR gate G and the output end 143 of the comparator 140. In this embodiment, the first switch 150, the second switch 160, and the third switch SW can be a metal oxide half field effect transistor, and the flip-flop 180 has a pulse input end 181 and uniform energy. The terminal 182 and the reset terminal 183 are electrically connected to the output end 143 of the comparator 140. The charging switch 190 is electrically connected to the positive terminal 141 of the comparator 140 and the first capacitor. 170, and the enable terminal 182 of the flip-flop 180, preferably, the charge switch 190 can be a CMOS inverter.
Referring to FIG. 1 again, in the embodiment, the voltage peak detector 100 further has a third resistor R and a second capacitor C. The third terminal of the third resistor R is electrically connected to a bias voltage. The other end of the third resistor R is electrically connected to the positive terminal 112 of the analog buffer 110, and the bias adjustment terminal VBIAS can pull the DC potential of the voltage signal input terminal 111, the second The other end of the capacitor C is electrically connected to the voltage signal input terminal 111, and the other end of the second capacitor C is electrically connected to the third resistor R and the positive terminal 112 of the analog buffer 110. The G system has a first reset signal terminal g1, a second reset signal terminal g2, and an output terminal g3. The first reset signal terminal g1 is electrically connected to the second switch 160, and the output terminal g3 is electrically connected. Connecting the first switch 150 and the third switch SW, the first reset signal terminal g1 can input a high potential signal, and the first switch 150 and the second switch 160 cause the main circuit Zeroing the node can effectively avoid the initial floating value generation, and when the circuit of the voltage peak detector 100 is activated Thereafter, the first reset signal terminal g1 inputs a high potential signal to drive the third switch SW to be turned on, so that the output terminal 143 of the comparator 140 is reset to zero to prevent the circuit from performing the next operation, the comparator 140 The output terminal 143 is still at a high voltage level. In the embodiment, the first switch 150 has a first gate terminal 151, a first threshold 152 and a first source terminal 153. The second switch The 160 series has a second gate terminal 161, a second gate terminal 162 and a second source terminal 163. The first gate terminal 151 is electrically connected to the first reset signal terminal g1 of the gate G. The second gate 161 is electrically connected to the output end g3 of the gate G. The charging switch 190 has a first end 191, a second end 192 and a third end 193. The first end 191 is electrically connected. The first end 192 is electrically connected to the positive terminal 141 of the comparator 140, and the third end 193 is electrically connected to the first capacitor 170. The third switch SW has a third gate terminal t1, a third terminal extreme t2 and a third source terminal t3, and the third terminal extreme t2 is electrically The output terminal 143 of the comparator 140 is electrically connected to the reset terminal 183 of the flip-flop 180 and the output terminal g3 of the OR gate G.
The operation of the present invention is as follows. The voltage signal received by the voltage signal input terminal 111 of the analog buffer 110 is zeroed by the second capacitor C, and then passed through the analog buffer 110. The low-pass filter 120 outputs a waveform that is close to a direct current, and the waveform changes as the voltage signal of the curved flat wave sensor changes. In the embodiment, the low-pass filter 120 is a A low-pass filter of a voltage-controlled voltage source (VCVS), the detailed circuit of the eighth-order voltage-controlled voltage source low-pass filter is disclosed in FIG. 2, and the amplifier 130 is used for amplification and filtering. The voltage signal is filtered by the second capacitor C and the eighth-order voltage-controlled voltage source low-pass filter, so that the specifications of the amplifier 130 and the comparator 140 at the back end are greatly reduced. The filtered and amplified voltage signal is sent to the positive terminal 141 of the comparator 140 and compared with the negative terminal 142. Since the voltage signal of the voltage signal input terminal 111 changes with time, the positive The voltage level of the terminal 141 also changes. When the voltage level of the positive terminal 141 gradually rises and is greater than the voltage level of the negative terminal 142, the output terminal 143 of the comparator 140 outputs a high potential signal to The pulse input terminal 181 of the flip-flop 180, the enable terminal 182 of the flip-flop 180 outputs the enable signal to the charging switch 190 to turn on the charging switch 190, so the positive terminal 141 The voltage signal is charged to store the first capacitor 170 to store the highest peak level of the voltage signal. If the voltage level below the positive terminal 141 is higher than the voltage level of the negative terminal 142, the system is charged. It is indicated that a higher peak occurs. Therefore, the enabler 182 of the flip-flop outputs the enable signal again, so that the charging switch 190 is turned on. The first capacitor 170 is electrically connected to the positive terminal 141 and simultaneously stored. When the voltage signal input terminal 111 receives the maximum voltage peak from the curved flat wave sensor, the first capacitor 170 can access its corresponding voltage level to represent the curved plate wave. The resonant frequency of the sensor, then, when the electricity When the voltage level of the voltage input terminal 111 is lower than the maximum voltage peak, the output terminal 143 of the comparator 140 outputs a low voltage level to turn off the charging switch 190, so the voltage of the first capacitor 170 is accurate. The first reset signal terminal g1, the voltage signal input terminal 111, the output end of the eighth-order voltage-controlled voltage source filter, and the positive terminal of the comparator 140 are still maintained. 141. The waveform diagram of the negative terminal 142 and the enable terminal 182 of the flip-flop 180 is disclosed in FIG.
The present invention is an electrical connection between the charging switch 190, the flip-flop 180 and the first capacitor 170. When the output terminal 143 of the comparator 140 outputs a high voltage level, the flip-flop is made. When the charging switch 190 is triggered, the charging switch 190 can immediately keep up with the voltage level of the positive terminal 141 of the comparator 140, so that the first capacitor 170 does not overcharge and causes the highest level of misjudgment. In addition, the charging time can be greatly reduced by the charging switch 190 in combination with the charging mode of the first capacitor 170.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Voltage peak detector

110‧‧‧ analog buffer

111‧‧‧Voltage signal input

112‧‧‧ positive end

120‧‧‧low pass filter

130‧‧‧Amplifier

131‧‧‧First resistance

132‧‧‧second resistance

140‧‧‧ Comparator

141‧‧‧ positive end

142‧‧‧negative end

143‧‧‧output

150‧‧‧First switch

151‧‧‧The first gate extreme

152‧‧‧ first extreme

153‧‧‧First source extreme

160‧‧‧second switch

161‧‧‧second gate extreme

162‧‧‧second extreme

163‧‧‧second source extreme

170‧‧‧first capacitor

180‧‧‧Fracture

181‧‧‧pulse

182‧‧‧Enable end

183‧‧‧Reset end

190‧‧‧Charge switch

191‧‧‧ first end

192‧‧‧ second end

193‧‧‧ third end

SW‧‧‧third switch

T1‧‧‧third gate extreme

T2‧‧‧third extreme

T3‧‧‧ Third source extreme

G‧‧‧ or gate

G1‧‧‧First reset signal end

G2‧‧‧Second reset signal end

G3‧‧‧output

VBIAS‧‧‧bias adjustment end

R‧‧‧ third resistor

C‧‧‧second capacitor

200‧‧‧Voltage peak detector

210‧‧‧ analog peak detection circuit

220‧‧‧ analog digital conversion unit

230‧‧‧Digital Peak Detection Circuit

240‧‧‧Control system

250‧‧‧Digital Analog Conversion Unit

Figure 1 is a circuit diagram of a voltage peak detector in accordance with a preferred embodiment of the present invention.
Figure 2 is a circuit diagram of a low pass filter of the voltage peak detector in accordance with a preferred embodiment of the present invention.
Figure 3 is a waveform diagram of the voltage peak detector in accordance with a preferred embodiment of the present invention.
Figure 4: Schematic diagram of a conventional voltage waveform detector.

100‧‧‧Voltage peak detector

110‧‧‧ analog buffer

111‧‧‧Voltage signal input

112‧‧‧ positive end

120‧‧‧low pass filter

130‧‧‧Amplifier

131‧‧‧First resistance

132‧‧‧second resistance

140‧‧‧ Comparator

141‧‧‧ positive end

142‧‧‧negative end

143‧‧‧output

150‧‧‧First switch

151‧‧‧The first gate extreme

152‧‧‧ first extreme

153‧‧‧First source extreme

160‧‧‧second switch

161‧‧‧second gate extreme

162‧‧‧second extreme

163‧‧‧second source extreme

170‧‧‧first capacitor

180‧‧‧Fracture

181‧‧‧pulse

182‧‧‧Enable end

183‧‧‧Reset end

190‧‧‧Charge switch

191‧‧‧ first end

192‧‧‧ second end

193‧‧‧ third end

SW‧‧‧third switch

T1‧‧‧third gate extreme

T2‧‧‧third extreme

T3‧‧‧ Third source extreme

G‧‧‧ or gate

G1‧‧‧First reset signal end

G2‧‧‧Second reset signal end

G3‧‧‧output

VBIAS‧‧‧bias adjustment end

R‧‧‧ third resistor

C‧‧‧second capacitor

Claims (10)

A voltage peak detector comprising:
a type of buffer having a voltage signal input;
a low pass filter electrically connected to the analog buffer;
An amplifier electrically connected to the low pass filter;
a comparator having a positive terminal, a negative terminal and an output terminal, the positive terminal being electrically connected to the amplifier;
a first switch electrically connected to the amplifier and the positive terminal of the comparator;
a second switch electrically connected to the negative terminal of the comparator;
a first capacitor electrically connected to the second switch and the negative terminal of the comparator;
a thyristor electrically connected to the second switch and the first switch;
a third switch electrically connected to the OR gate and the output end of the comparator;
a flip-flop having a pulse input end and a uniform energy end, the pulse input end being electrically connected to the output end of the comparator; and a charging switch electrically connected to the comparator Positive terminal, the first capacitor and the enabler of the flip-flop. The voltage peak detector of claim 1, wherein the charging open relationship has a first end, a second end, and a third end, the first end electrically connected to the flip flop The second end is electrically connected to the positive end of the comparator, and the third end is electrically connected to the first capacitor. The voltage peak detector of claim 2, wherein the charging open relationship is a CMOS inverter. The voltage peak detector of claim 1, wherein the orbital system has a first reset signal end, a second reset signal end, and an output end, the first reset signal end system The second switch is electrically connected, and the output end is electrically connected to the first switch. The voltage peak detector according to claim 4, wherein the first switch and the second open relationship may be a MOSFET, the first open relationship has a first gate terminal, and a first 汲 extreme and a first source terminal, the second open relationship having a second gate terminal, a second 汲 terminal and a second source terminal, the first gate terminal being electrically connected to the gate A reset signal terminal is electrically connected to the output end of the OR gate. The voltage peak detector according to claim 1, wherein the low pass filter is an eighth-order voltage-controlled voltage source low-pass filter. The voltage peak detector of claim 1, further comprising a third resistor, one end of the third resistor is electrically connected to a bias adjustment end, and the other end of the third resistor is electrically Connect the positive terminal of the first analog buffer. The voltage peak detector according to claim 7 , further comprising a second capacitor, wherein one end of the second capacitor is electrically connected to the voltage signal input end, and the other end of the second capacitor is electrically connected Connecting the third resistor and the positive terminal of the first analog buffer. For example, in the voltage peak detector described in claim 1, the third open relationship may be a MOS field effect transistor, and the third open relationship has a third gate terminal, a third 汲 terminal and one The third source terminal is electrically connected to the output end of the comparator, and the third gate terminal is electrically connected to the OR gate. The voltage peak detector of claim 9, wherein the flip-flop further has a reset terminal electrically connected to the third gate terminal of the third switch.