TWI428976B - A manufacturing method of a semiconductor device, a manufacturing apparatus for a semiconductor device, a computer memory medium, and a memory medium having a memory program - Google Patents
A manufacturing method of a semiconductor device, a manufacturing apparatus for a semiconductor device, a computer memory medium, and a memory medium having a memory program Download PDFInfo
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- TWI428976B TWI428976B TW096127562A TW96127562A TWI428976B TW I428976 B TWI428976 B TW I428976B TW 096127562 A TW096127562 A TW 096127562A TW 96127562 A TW96127562 A TW 96127562A TW I428976 B TWI428976 B TW I428976B
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 44
- 238000000034 method Methods 0.000 claims description 128
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 239000002184 metal Substances 0.000 claims description 68
- 238000001312 dry etching Methods 0.000 claims description 63
- 229920002120 photoresistant polymer Polymers 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 44
- 238000004380 ashing Methods 0.000 claims description 36
- 238000001039 wet etching Methods 0.000 claims description 35
- 239000000956 alloy Substances 0.000 claims description 22
- 229910045601 alloy Inorganic materials 0.000 claims description 22
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 238000003889 chemical engineering Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 105
- 239000007789 gas Substances 0.000 description 43
- 229910021417 amorphous silicon Inorganic materials 0.000 description 24
- 238000005530 etching Methods 0.000 description 19
- 238000001020 plasma etching Methods 0.000 description 17
- 230000002411 adverse Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Description
本發明是關於適於用來製造例如液晶顯示裝置等的半導體裝置的半導體裝置之製造方法、半導體裝置之製造裝置、電腦記憶媒體及記憶有處理程式之記憶媒體。The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a semiconductor device such as a liquid crystal display device, a device for manufacturing a semiconductor device, a computer memory medium, and a memory medium in which a processing program is stored.
過去以來，在半導體裝置的製程中，進行所要部位的蝕刻時，大多是採用使用藥液的濕式蝕刻、及使用氣體的乾式蝕刻。乾式蝕刻已知有：例如讓蝕刻氣體的電漿產生，藉由該電漿的作用來進行蝕刻之電漿蝕刻等。In the past, in the process of semiconductor devices, when etching a desired portion, wet etching using a chemical solution and dry etching using a gas are often used. Dry etching is known, for example, by plasma generation of an etching gas, plasma etching by etching by the action of the plasma, and the like.
例如液晶顯示裝置之非晶質矽TFT(薄膜電晶體)的製造工程等，係在將金屬膜予以蝕刻來形成閘極、源極以及汲極的工程、將非晶質矽膜等予以蝕刻來形成島形構造的工程、形成通道的工程中等，適當地使用濕式蝕刻及乾式蝕刻。並且，濕式蝕刻主要用於金屬膜的蝕刻工程之情形為多。另外，已知的有：在上述的蝕刻工程之間，利用氧氣及含有氟的氣體之混合氣體進行灰化，除去半導體層周緣部的隆起層，以改善電流特性的技術(例如，參照日本專利文獻1)。For example, in the manufacturing process of an amorphous germanium TFT (thin film transistor) of a liquid crystal display device, an amorphous thin film or the like is etched by etching a metal film to form a gate, a source, and a drain. The formation of the island-shaped structure, the formation of the channel, etc., the wet etching and the dry etching are suitably used. Moreover, there are many cases where wet etching is mainly used for the etching process of a metal film. In addition, there is known a technique in which ashing is performed by a mixed gas of oxygen and a gas containing fluorine between the above etching processes to remove the ridge layer on the peripheral portion of the semiconductor layer to improve current characteristics (for example, refer to Japanese patent) Document 1).
另外，上述液晶顯示裝置之非晶質矽TFT的製程，朝藉由使用呈段狀地形成的光阻遮罩(Resist Mask)，使遮罩數減少之省遮罩製程發展。該省遮罩製程，係藉由將呈段狀形成之光阻遮罩灰化到中途來變更該形狀，並當作2種 遮罩來使用，依此可以減少1次遮罩形成工程。Further, in the process of the amorphous germanium TFT of the above liquid crystal display device, a masking process for reducing the number of masks is developed by using a resist mask formed in a segment shape. The province's masking process changes the shape by ashing the photoresist mask formed in a segment shape to the middle, and treats it as two kinds. The mask is used to reduce the mask formation process by one time.
進而，依照在使用上述呈段狀形成的光阻遮罩的工程，進行2次濕式蝕刻工程及2次乾式蝕刻工程的方法，將第2次的濕式蝕刻工程置換成乾式蝕刻，能夠提升配線寬度、通道長度等之控制性；降低濕式藥液之使用成本；縮短工程等，依此可謀求提升生產性和良品率。Further, according to the method of performing the wet etching process and the secondary dry etching process twice using the above-described photoresist mask formed in a segment shape, the second wet etching process is replaced by dry etching, which can be improved. Controllability of wiring width, channel length, etc.; reducing the use cost of wet chemical liquid; shortening engineering, etc., thereby improving productivity and yield.
然而，例如當在之後利用乾蝕刻蝕刻將進行過1次乾式蝕刻的金屬膜予以蝕刻時，由於在進行濕式蝕刻蝕時與蝕刻液相接觸，形成在金屬膜的緣部(露出部)之變質層，在乾式蝕刻時則不被蝕刻，成為殘渣餘留著，有對之後的工程造成不良影響或對裝置特性造成不良影響的問題。例如，當在源極-汲極間存在有上述的殘渣時，則會導致源極-汲極間電短路的事態。However, for example, when a metal film which has been subjected to dry etching once is etched by dry etching etching, it is formed at the edge (exposed portion) of the metal film because it is in contact with the etching liquid phase at the time of performing wet etching. The metamorphic layer is not etched during dry etching, and remains as a residue, which may adversely affect subsequent processes or adversely affect device characteristics. For example, when the above-mentioned residue exists between the source and the drain, a situation in which the source-drain is electrically short-circuited is caused.
專利文獻1：日本專利特開2005-72443號公報Patent Document 1: Japanese Patent Laid-Open Publication No. 2005-72443
如以上所述，習知的技術所存在的課題為：具有將金屬模予以濕式蝕刻的工程、及之後再將該金屬膜予以乾式蝕刻的工程之時，濕式蝕刻時曝露在藥液中之金屬膜的側面所形成的變質層，會在乾式蝕刻時不被蝕刻而變成殘渣呈圍籬狀殘留著，有對之後的工程造成不良影響或對裝置特性造成不良影響之課題。As described above, the conventional technology has problems in that it has a process of wet etching a metal mold, and a process of dry etching the metal film later, and is exposed to the chemical liquid during wet etching. The deteriorated layer formed on the side surface of the metal film is not etched during dry etching, and the residue remains in a fence shape, which may adversely affect subsequent processes or adversely affect device characteristics.
本發明係為了要解決上述課題而提案，其目的係提供 在具有將金屬膜予以濕式蝕刻的工程、及之後具有將該金屬膜予以乾式蝕刻的工程之時，可以減少：在濕式蝕刻工程中被形成在金屬膜上之變質層的殘渣導致對之後的工程所造成的不良影響和對裝置特性所造成的不良影響，又可以穩定地製造良質的半導體裝置的半導體裝置之製造方法、半導體裝置之製造裝置、電腦記憶媒體及記憶有處理程式之記憶媒體。The present invention has been proposed in order to solve the above problems, and an object thereof is to provide In the case of having a process of wet etching a metal film, and thereafter having a process of dry etching the metal film, it is possible to reduce the residue of the deteriorated layer formed on the metal film in the wet etching process. The adverse effects of the engineering and the adverse effects on the characteristics of the device, the manufacturing method of the semiconductor device capable of stably manufacturing a good semiconductor device, the manufacturing device of the semiconductor device, the computer memory medium, and the memory medium storing the processing program .
本發明申請專利範圍第1項所述的半導體裝置之製造方法，是一種具有：將被形成在基板上的金屬膜經由光阻遮罩在濕式蝕刻工程中予以蝕刻之後，將前述金屬膜予以乾式蝕刻之乾式蝕刻工程的半導體裝置之製造方法其特徵為：具備有以下的工程：將前述光阻遮罩的一部分予以灰化變更前述光阻遮罩的形狀之灰化工程、及使用包含SF6 和Cl2 之混合氣體，或包含SF6 和O2 之混合氣體的電漿，除去在前述濕式蝕刻工程中被形成在露出的前述金屬膜之緣部上的變質層之變質層除去工程、及經由在前述灰化工程中變更形狀之前述光阻遮罩，將前述金屬膜予以乾式蝕刻之乾式蝕刻工程。A method of manufacturing a semiconductor device according to claim 1, wherein the metal film formed on the substrate is etched by a photoresist mask in a wet etching process, and then the metal film is applied A method of manufacturing a semiconductor device for a dry etching dry etching process, comprising: ashing a part of the photoresist mask by ashing the shape of the photoresist mask, and using SF a mixed gas of 6 and Cl 2 or a plasma containing a mixed gas of SF 6 and O 2 to remove the altered layer removal engineering of the altered layer formed on the edge of the exposed metal film in the wet etching process described above And dry etching of the metal film by dry etching through the photoresist mask having a shape changed in the ashing process.
本發明申請專利範圍第2項所述的半導體裝置之製造方法，如同申請專利範圍第1項所述的半導體裝置之製造方法，其中，將前述基板收容在處理腔室內，不從前述處 理腔室內搬出前述基板，持續執行前述灰化工程及前述變質層除去工程及前述乾式蝕刻工程。The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the substrate is housed in a processing chamber, not from the foregoing The substrate is carried out in the chamber, and the ashing process, the altered layer removal process, and the dry etching process are continuously performed.
本發明申請專利範圍第3項所述的半導體裝置之製造方法，是一種具有：將被形成在基板上的金屬膜經由光阻遮罩在濕式蝕刻工程中予以蝕刻之後，再將前述金屬膜予以乾式蝕刻之乾式蝕刻工程的半導體裝置之製造方法其特徵為：具備有以下的工程：經由前述光阻遮罩，將前述金屬膜之下層的非晶質矽膜予以乾式蝕刻之第1乾式蝕刻工程、及將前述光阻遮罩的一部分予以灰化變更前述光阻遮罩的形狀之灰化工程、及使用包含SF6 和Cl2 之混合氣體，或包含SF6 和O2 之混合氣體的電漿，除去在前述濕式蝕刻工程被形成在露出的前述金屬膜之緣部上的變質層之變質層除去工程、及經由在前述灰化工程中變更形狀之前述光阻遮罩，將前述金屬膜予以乾式蝕刻之第2乾式蝕刻工程、及經由在前述灰化工程中變更形狀之前述光阻遮罩，將前述非晶質矽膜予以乾式蝕刻之第3乾式蝕刻工程。A method of manufacturing a semiconductor device according to claim 3, wherein the metal film formed on the substrate is etched by a photoresist mask in a wet etching process, and then the metal film is further removed. A method of manufacturing a semiconductor device for dry etching by dry etching, characterized in that the first dry etching is performed by dry etching an amorphous germanium film under the metal film via the photoresist mask Engineering, and ashing a part of the photoresist mask to change the shape of the photoresist mask, using a mixed gas containing SF 6 and Cl 2 , or a mixed gas containing SF 6 and O 2 The plasma is removed from the altered layer removal process of the altered layer formed on the edge portion of the exposed metal film by the wet etching process, and the photoresist mask is changed in shape by the ashing process. The second dry etching process of the metal film is dry etching, and the amorphous germanium film is dry etched by the photoresist mask having a shape changed in the ashing process. Third dry etching project.
本發明申請專利範圍第4項所述的半導體裝置之製造方法，如同申請專利範圍第3項所述的半導體裝置之製造方法，其中，將前述基板收容在處理腔室內，不從前述處理腔室內搬出前述基板，持續執行前述第1乾式蝕刻工程、及前述灰化工程、及前述變質層除去工程、及前述第2乾式蝕刻工程、及前述第3乾式蝕刻工程。The method of manufacturing a semiconductor device according to claim 4, wherein the substrate is housed in a processing chamber, not from the processing chamber. The first substrate is removed, and the first dry etching process, the ashing process, the modified layer removing process, the second dry etching process, and the third dry etching process are continuously performed.
本發明申請專利範圍第5項所述的半導體裝置之製造方法，是一種具有：具有：將被形成在基板上的金屬膜經由光阻遮罩在濕式蝕刻工程中予以蝕刻之後，將前述金屬膜予以乾式蝕刻之乾式蝕刻工程的半導體裝置之製造方法其特徵為：具備有以下的工程：將前述光阻遮罩的一部分予以灰化變更前述光阻遮罩的形狀之灰化工程、及使用包含SF6 和Cl2 之混合氣體，或包含SF6 和O2 之混合氣體的電漿，除去在前述濕式蝕刻工程中被形成在露出的前述金屬膜之緣部上的變質層之變質層除去工程、及經由在前述灰化工程中變更形狀之前述光阻遮罩，將前述金屬膜之下層的非晶質矽膜予以乾式蝕刻之第1乾式蝕刻工程、及經由在前述灰化工程中變更形狀之前述光阻遮罩，將前述金屬膜予以乾式蝕刻之第2乾式蝕刻工程、及經由在前述灰化工程中變更形狀之前述光阻遮罩，將前述非晶質矽膜予以乾式蝕刻之第3乾式蝕刻工程。The method of manufacturing a semiconductor device according to claim 5, further comprising: forming the metal film formed on the substrate by etching in a wet etching process through a photoresist mask A method of manufacturing a semiconductor device for dry etching of a film by dry etching, characterized in that it is provided with a process of ashing a part of the photoresist mask, changing the shape of the photoresist mask, and using a mixed gas containing SF 6 and Cl 2 or a plasma containing a mixed gas of SF 6 and O 2 to remove a metamorphic layer of a metamorphic layer formed on the edge of the exposed metal film in the wet etching process described above a first dry etching process in which the amorphous ruthenium film under the metal film is dry etched and the ashing process is passed through the removal process and the photoresist mask having a shape changed in the ashing process Changing the shape of the photoresist mask, dry etching the metal film by a second dry etching process, and changing the shape of the photoresist through the ashing process , The amorphous silicon film will be the third dry etching step of dry etching.
本發明申請專利範圍第6項所述的半導體裝置之製造方法，如同申請專利範圍第5項所述的半導體裝置之製造方法，其中，利用前述第1乾式蝕刻工程，將前述金屬膜的一部分予以乾式蝕刻。The method of manufacturing a semiconductor device according to claim 5, wherein the method of manufacturing the semiconductor device according to the fifth aspect of the invention, wherein the part of the metal film is applied by the first dry etching process Dry etching.
本發明申請專利範圍第7項所述的半導體裝置之製造方法，如同申請專利範圍第5或6項所述的半導體裝置之製造方法，其中，將前述基板收容在處理腔室內，不從前 述處理腔室內搬出前述基板，持續執行前述灰化工程、及前述變質層除去工程、及前述第1乾式蝕刻工程、及前述第2乾式蝕刻工程、及前述第3乾式蝕刻工程。The method of manufacturing a semiconductor device according to claim 5, wherein the substrate is housed in a processing chamber, not before. The substrate is carried out in the processing chamber, and the ashing process, the modified layer removing process, the first dry etching process, the second dry etching process, and the third dry etching process are continuously performed.
本發明申請專利範圍第8項所述的半導體裝置之製造方法，申請專利範圍第1項所述的半導體裝置之製造方法，其中，前述金屬膜為鋁或其合金膜、鉬或其合金膜、鋁或其合金膜與鉬或其合金膜的層積膜中的任何一種。The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the metal film is aluminum or an alloy film thereof, molybdenum or an alloy film thereof, Any one of a laminated film of aluminum or an alloy film thereof and a film of molybdenum or an alloy thereof.
本發明申請專利範圍第9項所述的半導體裝置之製造裝置，其特徵為，具備有：收容基板之處理腔室、及將處理氣體供應至前述處理腔室內之處理氣體供應手段、及將從前述處理氣體供應手段所供應的前述處理氣體予以電漿化來處理前述基板之電漿產生手段、及控制成在前述處理腔室內執行申請專利範圍第1項所述的半導體裝置之製造方法之控制部。The apparatus for manufacturing a semiconductor device according to claim 9, comprising: a processing chamber for accommodating the substrate; and a processing gas supply means for supplying the processing gas into the processing chamber, and The plasma generating means for treating the substrate by the plasma processing of the processing gas supply means, and controlling the manufacturing method of the semiconductor device according to the first aspect of the invention in the processing chamber unit.
依據本發明，提供當具有金屬膜進行濕式蝕刻的工程、及之後該金屬膜進行乾式蝕刻的工程的情況，可以減少：在濕式蝕刻工程被形成在金屬膜上之變質層的殘渣導致對之後的工程所造成的不良影響、及對裝置特性所造成的不良影響，又可以穩定地製造優質的半導體裝置的半導體裝置之製造方法、半導體裝置之製造裝置、電腦記憶媒體 及記憶有處理程式之記憶媒體。According to the present invention, it is possible to reduce the case where the metal film is subjected to wet etching, and then the metal film is subjected to dry etching, and the residue of the deteriorated layer formed on the metal film in the wet etching process is reduced. A semiconductor device manufacturing method, a semiconductor device manufacturing device, and a computer memory medium capable of stably manufacturing a high-quality semiconductor device due to adverse effects caused by subsequent engineering and adverse effects on device characteristics And remember the memory medium with the processing program.
以下，參考圖面來說明本發明的實施形態。第1圖為擴大表示本實施形態的半導體裝置之製造方法的基板100之剖面構成。第2圖為表示本實施形態之作為半導體裝置之製造裝置之電漿蝕刻裝置的構成。首先，參考第2圖來說明電漿蝕刻裝置的構成。Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view showing an enlarged structure of a substrate 100 showing a method of manufacturing a semiconductor device of the present embodiment. Fig. 2 is a view showing the configuration of a plasma etching apparatus as a manufacturing apparatus of a semiconductor device of the present embodiment. First, the configuration of the plasma etching apparatus will be described with reference to Fig. 2 .
電漿蝕刻裝置1係由反應性離子蝕刻(RIE)裝置所構成，該反應性離子蝕刻(RIE)裝置則是使處理腔室2內產生處理氣體的電漿，析出電漿中的離子來與該處理腔室2內所配置的基板100產生作用，以進行蝕刻。另外，該處理腔室2內，並不侷限於進行電漿蝕刻，也可以進行後述的變質層除去工程和灰化工程等。The plasma etching apparatus 1 is constituted by a reactive ion etching (RIE) apparatus which generates a plasma of a processing gas in the processing chamber 2 and deposits ions in the plasma. The substrate 100 disposed in the processing chamber 2 functions to perform etching. Further, in the processing chamber 2, it is not limited to plasma etching, and a modified layer removing process, an ashing process, and the like which will be described later may be performed.
可氣密地封閉內部之處理腔室2形成為角筒形狀，在該處理腔室2內設有被支持在向上下配置之2種絕緣性支撐構件3a、3b之承載器3。然後，在該承載器3上載置液晶顯示裝置用的玻璃基板等的基板100。承載器3連接著高頻電源4，從該高頻電源4來對承載器3供應特定頻率(例如，13.56MHz)的高頻電力。The processing chamber 2, which can hermetically seal the inside, is formed in a rectangular tube shape, and a carrier 3 supported by two kinds of insulating support members 3a, 3b disposed up and down is provided in the processing chamber 2. Then, a substrate 100 such as a glass substrate for a liquid crystal display device is placed on the carrier 3 . The carrier 3 is connected to a high-frequency power source 4 from which high-frequency power of a specific frequency (for example, 13.56 MHz) is supplied to the carrier 3.
處理腔室2的頂棚部設有對向電極5，該對向電極5為接地電位。對向電極5具有多數個穿孔5a，以朝向基板100呈噴淋狀地供應從這些穿孔5a供應到氣體入口6之處理氣體的方式構成。氣體入口6連接著氣體供應管7。進 而，該氣體供應管7經由閥8、質量流量控制器9連接著處理氣體供應源10。從處理氣體供應源10供應特定的處理氣體。The ceiling portion of the processing chamber 2 is provided with a counter electrode 5 which is at a ground potential. The counter electrode 5 has a plurality of perforations 5a, and is configured to supply the processing gas supplied from the perforations 5a to the gas inlets 6 in a shower-like manner toward the substrate 100. The gas inlet 6 is connected to the gas supply pipe 7. Enter Further, the gas supply pipe 7 is connected to the process gas supply source 10 via a valve 8 and a mass flow controller 9. A specific process gas is supplied from the process gas supply source 10.
處理腔室2的底部連接著排氣管11，該排氣管11連接著排氣裝置12。排氣裝置12具備有渦輪分子泵等的真空泵，以可將處理腔室2內抽真空至特定的減壓雰圍為止的方式構成。另外，處理腔室2的側壁部設有閘閥13，在該閘閥13開啟的狀態下，從相鄰的負載鎖定室(load-lock chamber)(未圖示)，將基板100予以搬入和搬出。An exhaust pipe 11 is connected to the bottom of the processing chamber 2, and the exhaust pipe 11 is connected to the exhaust device 12. The exhaust device 12 is provided with a vacuum pump such as a turbo molecular pump, and is configured to evacuate the inside of the processing chamber 2 to a specific reduced pressure atmosphere. Further, the side wall portion of the processing chamber 2 is provided with a gate valve 13, and in a state where the gate valve 13 is opened, the substrate 100 is carried in and out from an adjacent load-lock chamber (not shown).
上述構成的電漿蝕刻裝置1係藉由控制部60來統籌控制該動作。該控制部60設有具備CPU來控制電漿蝕刻裝置1的各部位之製程控制器61、及使用者界面62、及記憶部63。The plasma etching apparatus 1 having the above configuration is controlled by the control unit 60 to coordinate the operation. The control unit 60 is provided with a process controller 61 including a CPU to control each part of the plasma etching apparatus 1, a user interface 62, and a memory unit 63.
使用者界面62係由為使製程管理者方便管理電漿蝕刻裝置1而進行指令的輸入操作之鍵盤、或以可視化來顯示電漿蝕刻裝置1的運作狀況之顯示器等所構成。The user interface 62 is constituted by a keyboard for inputting an instruction for facilitating management of the plasma etching apparatus 1 by a process manager, or a display for visually displaying the operation state of the plasma etching apparatus 1.
記憶部63中儲存著記憶有經由控制製程控制器61以實現電漿蝕刻裝置1所執行的各種處理用的控制程式(軟體)或處理條件數據之程式。然後，因應於需求，依照來自使用者界面62的指示等，製程控制器61執行從記憶部63所叫出的任意程式，在製程控制器61的控制下，進行電漿蝕刻裝置1所要進行的處理。另外，控制程式或處理條件數據等的程式，也能夠使用被儲存在電腦可讀取的電 腦記憶媒體(例如，硬碟、CD、軟碟、半導體記憶體等)等的狀態的程式、或者由其他的裝置，透過例如專線隨時傳送經由上線來使用程式。The memory unit 63 stores therein a program for storing a control program (software) or processing condition data for controlling various processes executed by the plasma etching apparatus 1 via the control process controller 61. Then, in accordance with an instruction from the user interface 62, the process controller 61 executes an arbitrary program called from the memory unit 63, and performs the plasma etching apparatus 1 under the control of the process controller 61. deal with. In addition, programs that control programs or process condition data can also be used to store readable data on a computer. A program of a state of a brain memory medium (for example, a hard disk, a CD, a floppy disk, a semiconductor memory, or the like) or another device can be used to transmit a program via a line at any time through, for example, a dedicated line.
藉由上述構成的電漿蝕刻裝置1來對基板100進行電漿蝕刻等的電漿處理的情況，首先閘閥13開啟後，基板100則從負載鎖定室(未圖示)搬入處理腔室2內，載置在承載器3上。接著閘閥13關閉，藉由排氣裝置12，將處理腔室2內抽真空至特定的真空度為止。When the substrate 100 is subjected to plasma treatment such as plasma etching by the plasma etching apparatus 1 having the above configuration, first, after the gate valve 13 is opened, the substrate 100 is carried into the processing chamber 2 from the load lock chamber (not shown). , placed on the carrier 3 . Then, the gate valve 13 is closed, and the inside of the processing chamber 2 is evacuated to a specific degree of vacuum by the exhaust unit 12.
之後，閥8開啟，從處理氣體供應源10所供應的特定氣體，藉由質量流量控制器9，調整該流量，並通過處理氣體供應管7、氣體入口6，導入到處理腔室2內。Thereafter, the valve 8 is opened, and the specific gas supplied from the processing gas supply source 10 is adjusted by the mass flow controller 9, and introduced into the processing chamber 2 through the processing gas supply pipe 7, the gas inlet 6.
然後，處理腔室2內的壓力維持在特定的壓力，並且特定頻率的高頻電力從高頻電源4施加給承載器3。藉由此方式，處理氣體解離而在處理腔室2內產生電漿，並且析出該電漿中的離子，到達被處理基板100，進行電漿蝕刻等的電漿處理。Then, the pressure in the processing chamber 2 is maintained at a specific pressure, and high frequency power of a specific frequency is applied from the high frequency power source 4 to the carrier 3. In this way, the treatment gas is dissociated to generate plasma in the processing chamber 2, and ions in the plasma are precipitated, reaching the substrate to be processed 100, and plasma treatment such as plasma etching is performed.
然後，當特定的電漿處理結束，則停止高頻電力的供應和處理氣體的供應，依照與上述的順序相反的順序，從處理腔室2內搬出基板100。Then, when the specific plasma processing is completed, the supply of the high-frequency power and the supply of the processing gas are stopped, and the substrate 100 is carried out from the processing chamber 2 in the reverse order to the above-described order.
其次，液晶顯示裝置之非晶質矽TFT的製造方法，作為本實施形態的半導體裝置之製造方法，參考第1圖來進行說明。第1圖為以模式來表示本實施形態中之基板100的剖面構成。如第1(a)圖所示，由透明玻璃基板所組成的基板100上，首先形成由金屬膜所組成的閘極102，該 金屬膜則是使用由光阻劑所組成的遮罩，進行蝕刻(濕式蝕刻)來形成為特定形狀。Next, a method of manufacturing an amorphous germanium TFT of a liquid crystal display device will be described with reference to FIG. 1 as a method of manufacturing the semiconductor device of the present embodiment. Fig. 1 is a cross-sectional view showing the structure of the substrate 100 in the present embodiment in a pattern. As shown in FIG. 1(a), on the substrate 100 composed of a transparent glass substrate, a gate 102 composed of a metal film is first formed, which The metal film is formed into a specific shape by etching (wet etching) using a mask composed of a photoresist.
其次，除去遮罩101之後，如第1(b)圖所示，由下側起依序形成絕緣膜103、a-Si膜(非晶質膜)104、n+ a-Si膜105、金屬膜106，在金屬膜106的上面，形成呈段狀的光阻遮罩107。金屬膜可以使用例如Al或其合金膜、Mo或其合金膜、Mo或其合金/Al或其合金的層積膜、Mo或其合金/Al或其合金/Mo或其合金的層積膜等。Next, after the mask 101 is removed, as shown in FIG. 1(b), the insulating film 103, the a-Si film (amorphous film) 104, the n + a-Si film 105, and the metal are sequentially formed from the lower side. The film 106 is formed with a segmented photoresist mask 107 on the upper surface of the metal film 106. As the metal film, for example, a laminated film of Al or an alloy film thereof, Mo or an alloy film thereof, Mo or an alloy thereof/Al or an alloy thereof, a film of Mo or an alloy thereof/Al or an alloy thereof/Mo or an alloy thereof, or the like can be used. .
其次，如第1(c)圖所示，將呈段狀形成的光阻遮罩107作為遮罩，經由濕式蝕刻來將金屬膜予以蝕刻，之後進行：將、n+ a-Si膜105、a-Si膜104予以乾式蝕刻來形成島形部分之灰化工程。上述的濕式蝕刻工程，會在與濕式蝕刻用的藥液相接觸之金屬膜106的緣部(露出部)，形成變質層(推測主要是氧化物)108。Next, as shown in FIG. 1(c), the photoresist mask 107 formed in a segment shape is used as a mask, and the metal film is etched by wet etching, followed by: n + a-Si film 105 The a-Si film 104 is dry etched to form an ashing process of the island portion. In the wet etching process described above, a modified layer (presumably mainly an oxide) 108 is formed at the edge (exposed portion) of the metal film 106 which is in contact with the liquid phase for wet etching.
其次，如第1(d)圖所示，進行：將呈段狀形成的光阻遮罩107灰化到中途之半灰化工程。Next, as shown in Fig. 1(d), it is performed to ash the photoresist mask 107 formed in a segment shape to the half-ashing process in the middle.
之後，如第1(e)圖所示，進行除去變質層108之變質層除去工程。該變質層除去工程係使用含有SF6 及Cl2 的混合氣體、或是使用含有SF6 及O2 的混合氣體，作為處理氣體，利用該電漿來進行。使用含有SF6 及Cl2 的混合氣體來作為處理氣體的情況，Cl2 的流量例如為100~150sccm，Cl2 與SF6 的流量比例如為5/1~15/1，壓力例如為6.65~13.3Pa，高頻的電力為0.58~0.86W/cm2 程度。另外，使用含有SF6 及O2 的混合氣體來作為處 理氣體的情況，處理條件的一個例子：SF6 /O2 =50/50sccm，壓力=2.66Pa，高頻電力=0.58~W/cm2 。Thereafter, as shown in Fig. 1(e), the metamorphic layer removal process for removing the altered layer 108 is performed. This modified layer removal process is carried out using a mixed gas containing SF 6 and Cl 2 or a mixed gas containing SF 6 and O 2 as a processing gas. When a mixed gas containing SF 6 and Cl 2 is used as the processing gas, the flow rate of Cl 2 is , for example, 100 to 150 sccm, and the flow ratio of Cl 2 to SF 6 is, for example, 5/1 to 15/1, and the pressure is, for example, 6.65. 13.3Pa, the high-frequency power is about 0.58~0.86W/cm 2 . Further, in the case where a mixed gas containing SF 6 and O 2 is used as the processing gas, an example of the processing conditions is SF 6 /O 2 = 50 / 50 sccm, pressure = 2.66 Pa, and high-frequency power = 0.58 - W / cm 2 .
之後，如第1(d)圖所示，將半灰化之呈段狀形成的光阻遮罩107作為遮罩，經由乾式蝕刻來將金屬膜106、n+ a-Si膜105、a-Si膜104的一部分予以蝕刻，形成通道109。Thereafter, as shown in Fig. 1(d), the half-ashed photoresist mask 107 formed in a segment shape is used as a mask, and the metal film 106, the n + a-Si film 105, a- are removed by dry etching. A portion of the Si film 104 is etched to form a channel 109.
然後，上述工程之後，進行形成鈍化膜和形成使用第3光阻遮罩的接觸孔之蝕工程、形成ITO膜和形成使用第4光阻遮罩的像素電極之蝕刻工程，製造液晶顯示裝置。Then, after the above-described process, an etching process for forming a passivation film and forming a contact hole using a third photoresist mask, forming an ITO film, and forming a pixel electrode using the fourth photoresist mask were performed to fabricate a liquid crystal display device.
如以上所述，本實施形態，因經由變質層除去工程來除去濕式蝕刻所產生的金屬膜之變質層10，所以可以減輕變質層108的殘渣導致對之後的工程所造成的不良影響、及對裝置特性所造成的不良影響。As described above, in the present embodiment, since the altered layer 10 of the metal film generated by the wet etching is removed by the process of removing the altered layer, the deterioration of the deteriorated layer 108 can be reduced, which causes adverse effects on subsequent processes. Adverse effects on device characteristics.
相對於此，不施行變質層除去工程的情況，如第4圖所示，在濕式蝕刻導致在金屬膜106形成變質層108的狀態下(a)，接著進行半灰化工程，呈段狀形成的光阻遮罩107則會收縮(shrink)，金屬膜106的一部分因而露出(b)。然後，在該狀態下進行金屬膜106的乾式蝕刻工程，藉此在露出部分形成突刺形狀，只有外側的變質層108(殘渣)會呈圍籬狀地殘留著(c)。該圍籬狀的殘渣如同第4(c)圖的上部(上面圖)所示形成為框狀，故會有發生源極-汲極間的電短路等的情況。On the other hand, in the case where the modified layer removal process is not performed, as shown in FIG. 4, in the state where the modified layer 108 is formed in the metal film 106 by wet etching (a), the half-ashing process is carried out, and the film is in the form of a segment. The formed photoresist mask 107 is shrunk, and a portion of the metal film 106 is thus exposed (b). Then, in this state, the dry etching process of the metal film 106 is performed, whereby a spur shape is formed in the exposed portion, and only the outer modified layer 108 (residue) remains in a fence shape (c). The fence-like residue is formed in a frame shape as shown in the upper portion (top view) of Fig. 4(c), and thus an electric short circuit between the source and the drain may occur.
上述實施形態中，將呈段狀形成的光阻遮罩107作為遮罩，以以下的條件，進行經由濕式蝕刻(蝕刻液=磷酸 +醋酸+硝酸)來將金屬膜106予以蝕刻之後的一連串工程。In the above-described embodiment, the photoresist mask 107 formed in a segment shape is used as a mask, and is subjected to wet etching under the following conditions (etching liquid = phosphoric acid + Acetic acid + nitric acid) A series of processes after etching the metal film 106.
即是使用SF6 與Cl2 的混合氣體，進行：將n+ a-Si膜105、a-Si膜104予以乾式蝕刻來形成島形部分之島形裝蝕刻工程，再使用O2 氣體，進行：將呈段狀形成的光阻遮罩107灰化到中途之半灰化工程。之後，以處理氣體Cl2 /SF6 =150/10sccm，壓力=10.64Pa，高頻電力=0.58~0.86W/cm2 的條件，進行除去變質層108的變質層除去工程。然後，將半灰化之呈段狀形成之光阻遮罩107作為遮罩，金屬膜106中，Mo膜使用的Cl2 及O2 的混合氣體來進行蝕刻，Al膜使用BCl3 及Cl2 的混合氣體來進行蝕刻，再使用Cl2 及SF6 的混合氣體來將n+ a-Si膜105、a-Si膜104的一部分予以蝕刻，形成通道109。That is, using a mixed gas of SF 6 and Cl 2 , the n + a-Si film 105 and the a-Si film 104 are dry-etched to form an island-shaped portion of the island-shaped etching process, and then O 2 gas is used. : The photoresist mask 107 formed in a segment shape is ashed to a half-ashing project in the middle. Thereafter, the metamorphic layer removal process for removing the altered layer 108 was carried out under the conditions of the treatment gas Cl 2 /SF 6 =150/10 sccm, pressure = 10.64 Pa, and high-frequency power = 0.58 to 0.86 W/cm 2 . Then, a half-ashed photoresist mask 107 formed in a segment shape is used as a mask, and a mixed gas of Cl 2 and O 2 used for the Mo film in the metal film 106 is etched, and Al film is made of BCl 3 and Cl 2 . The mixed gas is etched, and a part of the n + a-Si film 105 and the a-Si film 104 is etched using a mixed gas of Cl 2 and SF 6 to form a channel 109.
該結果，可以將變質層108的殘渣所導致之突刺形狀或圍籬狀的構造物等不會產生之良好狀態的薄膜電晶體予以製造出來。此外，在使用上述一連串之段狀形成的電晶體的工程中，最初的濕式蝕刻以後的工程係藉由第2圖所示的電漿蝕刻裝置1來實施。此時，一經將基板100收容到腔室2內之後，依序變更處理氣體等的處理條件，藉由此方式，不必取出基板100就可以進行處理。因而，比中途進行濕式蝕刻的情況還要更良好的效率且可以在短時間內進行處理。As a result, a thin film transistor which does not have a good state such as a spur shape or a fence-like structure due to the residue of the altered layer 108 can be produced. Further, in the process of using the above-described series of segments formed of transistors, the first post-wet etching process is performed by the plasma etching apparatus 1 shown in FIG. At this time, once the substrate 100 is housed in the chamber 2, the processing conditions of the processing gas and the like are sequentially changed, whereby the processing can be performed without taking out the substrate 100. Therefore, it is more efficient than the case of performing wet etching in the middle and can be processed in a short time.
其次，參考第3圖來說明其他的實施形態。如第3(a)圖所示，在由透明玻璃基板所組成的基板100，首先形 成由使用由光阻劑所組成的遮罩101進行蝕刻(濕式蝕刻)形成為特定形狀的金屬膜所組成之閘極102。Next, other embodiments will be described with reference to Fig. 3. As shown in Fig. 3(a), in the substrate 100 composed of a transparent glass substrate, first shape The gate 102 composed of a metal film of a specific shape is formed by etching (wet etching) using a mask 101 composed of a photoresist.
其次，除去遮罩101之後，如第3(b)圖所示，由下側起依序形成絕緣膜103、a-Si膜(非晶質膜)104、n+ a-Si膜105、金屬膜106，在金屬膜106，在金屬膜106的上面形成呈段狀形成光阻遮罩107。金屬膜可以使用例如Al或其合金膜、Mo或其合金膜、Mo或其合金/Al或其合金的層積膜、Mo或其合金/Al或其合金/Mo或其合金的層積膜等。Next, after the mask 101 is removed, as shown in FIG. 3(b), the insulating film 103, the a-Si film (amorphous film) 104, the n + a-Si film 105, and the metal are sequentially formed from the lower side. In the film 106, a photoresist mask 107 is formed in a segment shape on the metal film 106. As the metal film, for example, a laminated film of Al or an alloy film thereof, Mo or an alloy film thereof, Mo or an alloy thereof/Al or an alloy thereof, a film of Mo or an alloy thereof/Al or an alloy thereof/Mo or an alloy thereof, or the like can be used. .
其次，如第3(c)圖所示，將呈段狀形成的光阻遮罩107作為遮罩，藉由濕式蝕刻來將金屬膜106予以蝕刻。此工程是要在經濕式蝕刻過之金屬膜106的緣部形成變質層108。Next, as shown in Fig. 3(c), the photoresist mask 107 formed in a segment shape is used as a mask, and the metal film 106 is etched by wet etching. This process is to form a metamorphic layer 108 at the edge of the wet etched metal film 106.
其次，如第3(d)圖所示，進行：只將呈段狀形成的光阻遮罩107灰化到中途來變更該形狀之半灰化工程。Next, as shown in the third (d) diagram, it is performed that only the photoresist mask 107 formed in a segment shape is grayed out to change the half-ashing process of the shape.
之後、與上述過的實施形態同樣的方式，進行除去變質層108的變質層除去工程，然後，將n+ a-Si膜105、a-Si膜104予以蝕刻來形成島形部分，再經由乾式蝕刻，將金屬膜106、n+ a-Si膜105、a-Si膜104的一部分予以蝕刻，形成通道109。此外，也可以在將n+ a-Si膜105、a-Si膜104予以乾式蝕刻來形成島形部分時，依照金屬膜的種類來將通道部分之金屬膜的一部分予以蝕刻。Thereafter, in the same manner as in the above-described embodiment, the modified layer removal process for removing the altered layer 108 is performed, and then the n + a-Si film 105 and the a-Si film 104 are etched to form an island-shaped portion, and then dried. By etching, a part of the metal film 106, the n + a-Si film 105, and the a-Si film 104 is etched to form a channel 109. Further, when the n + a-Si film 105 and the a-Si film 104 are dry-etched to form an island-shaped portion, a part of the metal film of the channel portion may be etched in accordance with the type of the metal film.
與前述過的實施形態不同處則是本實施形態中換成半灰化工程及島形蝕刻工程，不過半灰化工程之後進行變質 層除去工程，可以獲得與前述過的實施形態同樣的效果。另外，本實施形態中，若是變質層除去工程使用Cl2 /SF6 的話，可以使用這系列的氣體來將n+ a-Si膜105、a-Si膜104予以蝕刻，所以可以持續執行島形蝕刻工程，又可以實質上減少工程數。The difference from the above-described embodiment is that the half-ashing process and the island-shaped etching process are replaced in the present embodiment. However, after the half-ashing process, the modified layer removing process is performed, and the same effects as those of the above-described embodiment can be obtained. Further, in the present embodiment, when Cl 2 /SF 6 is used for the process of removing the altered layer, the n + a-Si film 105 and the a-Si film 104 can be etched using the gas of this series, so that the island shape can be continuously performed. The etching process can substantially reduce the number of projects.
100‧‧‧基板100‧‧‧Substrate
101‧‧‧遮罩101‧‧‧ mask
102‧‧‧閘極102‧‧‧ gate
103‧‧‧絕緣膜103‧‧‧Insulation film
104‧‧‧a-Si膜104‧‧‧a-Si film
105‧‧‧n+ a-Si膜105‧‧‧n + a-Si film
106‧‧‧金屬膜106‧‧‧Metal film
107‧‧‧呈段狀形成的光阻遮罩107‧‧‧Photoreceptive mask formed in segments
108‧‧‧變質層108‧‧‧ Metamorphic layer
109‧‧‧通道109‧‧‧ channel
第1圖為以模式來表示本發明的實施形態之基板的剖面構成之圖。Fig. 1 is a view showing a cross-sectional configuration of a substrate according to an embodiment of the present invention in a mode.
第2圖為表示本發明的實施形態之半導體裝置的製造裝置的概略構成之圖。Fig. 2 is a view showing a schematic configuration of a manufacturing apparatus of a semiconductor device according to an embodiment of the present invention.
第3圖為以模式來表示本發明的其他實施形態之基板的剖面構成之圖。Fig. 3 is a view showing a cross-sectional structure of a substrate according to another embodiment of the present invention in a mode.
第4圖為以模式來表示習知技術中基板的上面和剖面的構成之圖。Fig. 4 is a view showing the configuration of the upper surface and the cross section of the substrate in the prior art in a pattern.
100‧‧‧基板100‧‧‧Substrate
101‧‧‧遮罩101‧‧‧ mask
102‧‧‧閘極102‧‧‧ gate
103‧‧‧絕緣膜103‧‧‧Insulation film
104‧‧‧a-Si膜104‧‧‧a-Si film
105‧‧‧n+ a-Si膜105‧‧‧n + a-Si film
106‧‧‧金屬膜106‧‧‧Metal film
107‧‧‧光阻遮罩107‧‧‧Light-shielding mask
108‧‧‧變質層108‧‧‧ Metamorphic layer
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