TWI424547B - Leadframe-based semiconductor device and leadframe thereof - Google Patents
Leadframe-based semiconductor device and leadframe thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
本發明係有關於一種半導體裝置，尤指一種導線架式半導體裝置及其導線架。The present invention relates to a semiconductor device, and more particularly to a lead frame type semiconductor device and a lead frame thereof.
傳統導線架(Lead Frame)式之半導體封裝件，如美國專利第5,793,108、6,072,243、6,208,023、5,623,123等專利揭示，其係提供一包含有晶片座及多數設於該晶片座周圍之導腳的導線架，並將一晶片黏置於該晶片座上，復藉複數條銲線電性連接晶片表面上各晶片銲墊(Electrode Pads)至對應導腳，再以一封裝膠體包覆該晶片及銲線而形成一導線架式半導體封裝件。A conventional lead frame type semiconductor package, such as those disclosed in U.S. Patent Nos. 5,793,108, 6, 072, 243, 6, 208, 023, 5, 623, 123, etc., which provide a lead frame including a wafer holder and a plurality of guide pins disposed around the wafer holder. And bonding a wafer to the wafer holder, and electrically connecting a plurality of bonding pads (Electrode Pads) on the surface of the wafer to the corresponding guiding pins, and coating the wafer and the bonding wire with a sealing gel. A lead frame type semiconductor package is formed.
惟前述傳統之導線架結構設計在對應各式功能及作用不同之晶片電性需求時，可供彈性調整該導線架之導腳佈局空間誠屬有限，尤其面對高度集積化且輕薄型之晶片時，所需之導腳間距及封裝件尺寸愈來愈小，該傳統導線架可供強化電性表現之設計方式已大幅限制，不易有改善空間。However, when the conventional lead frame structure is designed to meet the electrical requirements of various functions and functions, the space for guiding the lead frame of the lead frame can be flexibly adjusted, especially for highly integrated and thin wafers. At the same time, the required pitch of the leads and the size of the package are getting smaller and smaller, and the design method of the conventional lead frame for enhancing the electrical performance has been greatly limited, and it is not easy to improve the space.
請參閱第1A及1B圖，鑒於前述傳統導線架設計之缺失，美國專利第4,943,843、4,937,656、5,234,866遂揭示一種未設有晶片座之導線架式半導體封裝件，其係包括有：複數信號(signal)導腳11；一絕緣薄片12，係設置於部分信號導腳11上；一半導體晶片13，係藉由黏著層14而接置於該絕緣薄片12上；複數銲線15，係電性連接該半導體晶片13及信號導腳11內端；以及封裝膠體16，係包覆該信號導腳11內端、絕緣薄片12、半導體晶片13及銲線15，並使該信號導腳11外端外露出該封裝膠體16。俾藉由省去傳統導線架之晶片座設置，以提供信號導腳具有較充足之布局空間。Referring to FIGS. 1A and 1B, in view of the above-described conventional lead frame design, U.S. Patent Nos. 4,943,843, 4,937,656, 5,234,866, the disclosure of each of each of each of each of each of each of each of a lead 11; an insulating sheet 12 is disposed on the portion of the signal pin 11; a semiconductor wafer 13 is attached to the insulating sheet 12 by the adhesive layer 14; the plurality of bonding wires 15 are electrically connected The semiconductor chip 13 and the inner end of the signal guiding pin 11; and the encapsulant 16 cover the inner end of the signal guiding pin 11, the insulating sheet 12, the semiconductor wafer 13 and the bonding wire 15, and the outer end of the signal guiding pin 11 The encapsulant 16 is exposed.俾 By eliminating the wafer holder arrangement of the conventional lead frame, the signal pin has a sufficient layout space.
然而在半導體晶片電性需求愈來愈高之情況下，對於信號、電源、及接地之輸入/輸出(I/O)相互間的設計匹配性愈來愈重要，因此前述之導線架結構已無法滿足現今電性之需求。However, as the electrical requirements of semiconductor wafers become higher and higher, the design matching between the input/output (I/O) of signals, power supplies, and grounding is becoming more and more important, so the aforementioned leadframe structure cannot be used. Meet the needs of today's electricity.
再者，前述導線架中延伸至晶片下方作為支撐晶片之信號導腳設計，僅考慮該些信號導腳相對於晶片銲墊之佈局，確已無法滿足現今高電性及高散熱性之電子商品需求。尤其因目前高頻電子產品特性為信號的上升時間(rise time)愈來愈短、積體電路(IC)的輸入/輸出(I/O)接腳愈來愈多、接腳的接線密度(interconnects density)愈來愈高，同時，IC雜散效應也日趨嚴重，通常對於上升時間在ns這個數量級時，當信號上升時間縮短時，或/及電流量增加時，電流的變化率就會增大，接地反彈的電壓也就增加，此時接地平面已經不是理想的零電位，而電源端也不是理想的直流電位。當系統的速度愈快，而且為數眾多的邏輯閘同時轉換狀態時就愈容易造成嚴重的電壓陷落(Power Drop)現象，或稱為接地彈跳(Ground Bounce)。Furthermore, the signal pin design of the lead frame extending below the wafer as a supporting chip only considers the layout of the signal guiding pins relative to the die pad, and thus can not meet the current high electrical and high heat dissipation electronic products. demand. In particular, due to the current high-frequency electronic product characteristics, the rise time of the signal is getting shorter and shorter, the input/output (I/O) pins of the integrated circuit (IC) are getting more and more, and the wiring density of the pins ( The interconnects density is getting higher and higher. At the same time, the IC spur effect is becoming more and more serious. Generally, when the rise time is in the order of ns, when the signal rise time is shortened, or / and the current amount is increased, the current change rate is increased. The voltage of the ground bounce is also increased. At this time, the ground plane is not the ideal zero potential, and the power supply terminal is not the ideal DC potential. The faster the system is, and the more numerous logic gates are simultaneously transitioning, the more likely it is to cause a severe Power Drop phenomenon, or Ground Bounce.
傳統為簡化處理問題，通常把電源和接地都當成理想的情況來處理，但在高速設計中，這種簡化卻會造成越來越難以預測電路系統在實現後的行為。儘管電路設計直接可看到的結果是從信號完整性上表現出來的，但絕不能因此忽略了電源完整性的設計，因為電源完整性被破壞後終究會反映至信號的完整性，而且在很多情形下，影響信號畸變、擾動的主要原因是電源系統，例如：多電源/接地平面的分割不理想、接地反彈雜訊太大、電流分配的不均等。Traditionally, to simplify processing problems, both power and ground are often treated as ideal, but in high-speed designs, this simplification makes it increasingly difficult to predict the behavior of the system after it is implemented. Although the results directly seen by the circuit design are manifested in signal integrity, the design of the power integrity must not be neglected because the integrity of the power supply is destroyed and will eventually be reflected to the integrity of the signal, and in many In this case, the main cause of signal distortion and disturbance is the power supply system, for example, the division of multiple power/ground planes is not ideal, the ground bounce noise is too large, and the current distribution is uneven.
因此，如何提供一種導線架結構與導線架式半導體封裝件可有效強化電性功能、降低接地彈跳問題及提升散熱效能，實已成為目前亟欲解決之課題。Therefore, how to provide a lead frame structure and a lead frame type semiconductor package can effectively enhance the electrical function, reduce the ground bounce problem and improve the heat dissipation performance, which has become a problem to be solved at present.
鑑於上述習知技術問題點，本發明之一目的係在提供一種可強化電性功能之導線架式半導體裝置及其導線架。In view of the above-mentioned conventional technical problems, it is an object of the present invention to provide a lead frame type semiconductor device capable of enhancing electrical functions and a lead frame thereof.
本發明之又一目的係提供一種可降低接地彈跳問題之導線架式半導體裝置及其導線架。It is still another object of the present invention to provide a lead frame type semiconductor device and a lead frame thereof which can reduce the ground bounce problem.
本發明之再一目的係提供一種可提升散熱效能之導線架式半導體裝置及其導線架。Still another object of the present invention is to provide a lead frame type semiconductor device and a lead frame thereof which can improve heat dissipation performance.
為達上揭目的，本發明揭露一種導線架式半導體裝置，係包括：一導線架，該導線架具有複數信號導腳及複數接地導腳，其中該些接地導腳共同構成一晶片接置區，該些信號導腳則分佈於該晶片接置區周圍，且該晶片接置區內之接地導腳尺寸大於該信號導腳尺寸；至少一半導體晶片，係接置於該些接地導腳之晶片接置區上；以及複數銲線，係供該半導體晶片電性連接至該信號導腳及接地導腳。該導線架復包括有分佈於該晶片接置區周圍之電源導腳，其中，該晶片接置區內之接地導腳尺寸大於該電源導腳尺寸，半導體晶片係透過複數銲線電性連接至該電源導腳，並形成有一包覆該導線架、半導體晶片及銲線之封裝膠體，且外露該信號導腳、電源導腳及接地導腳之外端。In order to achieve the above, a lead frame type semiconductor device includes: a lead frame having a plurality of signal pins and a plurality of ground pins, wherein the ground pins together form a wafer connection region The signal pins are distributed around the wafer connection region, and the ground lead size in the wafer connection region is larger than the signal pin size; at least one semiconductor chip is connected to the ground pins. And a plurality of bonding wires for electrically connecting the semiconductor chip to the signal pin and the ground pin. The lead frame includes a power supply pin distributed around the chip connection area, wherein a ground lead size of the wafer connection area is larger than the power supply lead size, and the semiconductor chip is electrically connected to the plurality of bonding wires to The power supply pin is formed with a package body covering the lead frame, the semiconductor chip and the bonding wire, and the signal pin, the power supply pin and the grounding pin are exposed.
本發明之導線架式半導體裝置另一較佳實施態樣係包括：一導線架，該導線架具有複數信號導腳及複數電源導腳，其中該些電源導腳共同構成一晶片接置區，該些信號導腳則分佈於該晶片接置區周圍，且該晶片接置區內之電源導腳尺寸大於該信號導腳尺寸；至少一半導體晶片，係接置於該些電源導腳之晶片接置區上；以及複數銲線，係供該半導體晶片電性連接至該信號導腳及電源導腳。該導線架復包括有分佈於該晶片接置區周圍之接地導腳，其中，該晶片接置區內之電源導腳尺寸大於該接地導腳尺寸，半導體晶片係透過複數銲線電性連接至該接地導腳，並形成有一包覆該導線架、半導體晶片及銲線之封裝膠體，且外露該信號導腳、電源導腳及接地導腳之外端。Another preferred embodiment of the lead frame type semiconductor device of the present invention includes: a lead frame having a plurality of signal pins and a plurality of power supply pins, wherein the power supply pins collectively constitute a wafer connection region, The signal pins are distributed around the chip placement area, and the power supply lead size in the wafer connection area is larger than the signal guide size; at least one semiconductor chip is connected to the chip of the power supply leads And a plurality of bonding wires for electrically connecting the semiconductor chip to the signal pin and the power pin. The lead frame includes a grounding lead disposed around the receiving area of the wafer, wherein a size of the power guiding pin in the connecting area of the wafer is larger than a size of the grounding lead, and the semiconductor chip is electrically connected to the plurality of bonding wires to The grounding lead is formed with a sealing gel covering the lead frame, the semiconductor wafer and the bonding wire, and the signal guiding pin, the power guiding pin and the grounding pin are exposed.
本發明復揭示一種導線架，係包括有：複數接地導腳，該些接地導腳共同構成一晶片接置區，以供接置半導體晶片；以及複數信號導腳，分佈於該晶片接置區周圍，其中該晶片接置區內之接地導腳尺寸大於該信號導腳尺寸。該導線架復包括有分佈於該晶片接置區周圍之電源導腳，其中，該晶片接置區內之接地導腳尺寸大於該電源導腳尺寸。The present invention further discloses a lead frame comprising: a plurality of ground lead pins, the ground lead pins collectively forming a wafer receiving area for receiving a semiconductor wafer; and a plurality of signal guiding legs distributed in the wafer receiving area Surrounding, wherein the grounding lead size in the wafer receiving area is larger than the signal guiding size. The lead frame includes a power supply pin distributed around the wafer connection area, wherein a ground lead size in the wafer connection area is larger than the power supply lead size.
本發明之導線架另一較佳實施態樣係包括：複數電源導腳，該些電源導腳共同構成一晶片接置區，以供接置半導體晶片；以及複數信號導腳，分佈於該晶片接置區周圍，其中該晶片接置區內之電源導腳尺寸大於該信號導腳尺寸。該導線架復包括有分佈於該晶片接置區周圍之接地導腳，其中，該晶片接置區內之電源導腳尺寸大於該接地導腳尺寸。Another preferred embodiment of the lead frame of the present invention includes: a plurality of power supply pins that collectively form a wafer connection region for receiving a semiconductor wafer; and a plurality of signal pins distributed on the wafer Around the connection area, wherein the power supply lead size in the wafer connection area is larger than the signal guide size. The lead frame includes a grounding lead distributed around the receiving area of the wafer, wherein a size of the power guiding pin in the wafer receiving area is larger than the size of the grounding lead.
本發明之導線架又一較佳實施態樣係包括：複數導腳，該些導腳共同構成一晶片接置區，以供接置半導體晶片；以及另一複數導腳，分佈於該晶片接置區周圍，其中該晶片接置區內之導腳尺寸大於該晶片接置區周圍之導腳尺寸。該晶片接置區內之導腳可選擇為接地導腳、或為電源導腳、亦或為接地導腳與電源導腳之組合(該接地導腳與電源導腳係相互分隔設置)，而該晶片接置區周圍之導腳則為信號導腳。A further preferred embodiment of the lead frame of the present invention includes: a plurality of lead pins collectively forming a wafer receiving area for receiving a semiconductor wafer; and another plurality of lead pins distributed over the wafer Around the set area, the lead size in the wafer attachment area is larger than the lead size around the wafer attachment area. The lead pin in the wafer connection area can be selected as a ground lead, or a power lead, or a combination of a ground lead and a power lead (the ground lead and the power lead are separated from each other), and The lead pins around the wafer attachment area are signal leads.
再者，本發明復可於前述之導線架中，對於構成晶片接置區之接地導腳及/或電源導腳中形成複數開孔，藉以增加半導體晶片與封裝膠體之接觸面積，強化接著力，防止發生脫層問題；另外，復可將構成晶片接置區之複數接地導腳及/或電源導腳相對低置於佈設於該晶片接置區周圍之信號導腳，以縮短半導體晶片電性連接至該信號導腳之銲線長度，藉以節省製程成本，避免發生銲線偏移(wire sweep)問題，同時改善半導體晶片與導線架之電性連接品質。Furthermore, the present invention is applicable to the above-mentioned lead frame, and a plurality of openings are formed in the ground lead and/or the power guiding pin constituting the wafer receiving area, thereby increasing the contact area between the semiconductor wafer and the encapsulant, and strengthening the bonding force. To prevent the occurrence of delamination; in addition, the plurality of grounding leads and/or power guiding pins constituting the wafer receiving area are relatively low placed on the signal guiding pins disposed around the wafer receiving area to shorten the semiconductor wafer power The length of the bonding wire connected to the signal lead is saved, thereby saving process cost, avoiding the problem of wire sweep, and improving the electrical connection quality between the semiconductor wafer and the lead frame.
因此，本發明之導線架式半導體裝置及其導線架係提供一具有複數信號導腳、接地導腳及電源導腳之導線架，並使複數之接地導腳(或電源導腳)共同構成一晶片接置區，且將其餘之該些信號導腳及電源導腳(或接地導腳)分佈於該晶片接置區周圍，藉以獨立該些接地導腳與電源導腳，以改善接地彈跳問題，強化電性功能，同時使該晶片接置區內之接地導腳(或電源導腳)尺寸大於設於該晶片接置區周圍之信號導腳及電源導腳(或接地導腳)尺寸，以提供設於該晶片接置區上之半導體晶片良好散熱功能。Therefore, the lead frame type semiconductor device of the present invention and the lead frame thereof provide a lead frame having a plurality of signal lead pins, a ground lead pin and a power lead pin, and a plurality of ground lead pins (or power lead pins) are combined to form a lead frame. a chip connection area, and distributing the remaining signal lead pins and power lead pins (or ground lead pins) around the chip attaching area to separate the ground lead pins and the power lead pins to improve the ground bounce problem The electrical function is enhanced, and the size of the grounding lead (or power guiding pin) in the wafer receiving area is larger than the size of the signal guiding pin and the power guiding pin (or grounding pin) disposed around the receiving area of the chip. To provide a good heat dissipation function of the semiconductor wafer disposed on the wafer placement area.
以下係藉由特定的具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention.
請參閱第2圖，係為本發明之導線架式平面示意圖。Please refer to FIG. 2, which is a plan view of the lead frame of the present invention.
該導線架係包括有複數接地導腳211，該些接地導腳211共同構成一晶片接置區210；複數信號導腳213，分佈於該晶片接置區210周圍；以及複數電源導腳212，分佈於該晶片接置區210周圍，且該晶片接置區210內之接地導腳211尺寸大於該信號導腳213及電源導腳212尺寸。The lead frame includes a plurality of grounding pins 211, which together form a wafer receiving area 210; a plurality of signal guiding pins 213 are distributed around the wafer receiving area 210; and a plurality of power guiding pins 212, The grounding lead 211 in the wafer receiving area 210 is larger than the signal guiding leg 213 and the power guiding pin 212.
亦即使該些接地導腳211與電源導腳212係相對獨立設置，以改善接地彈跳問題，強化電性功能，同時使該晶片接置區210內之接地導腳211尺寸大於設於該晶片接置區210周圍之信號導腳213及電源導腳212尺寸，進而提供後續設於該晶片接置區210上之半導體晶片良好之散熱功能。Even if the grounding pins 211 and the power guiding pins 212 are relatively independently disposed to improve the ground bounce problem, the electrical function is enhanced, and the grounding pin 211 in the wafer receiving area 210 is larger than the size of the grounding pin 211. The signal pin 213 and the power pin 212 around the cell 210 are sized to provide a good heat dissipation function for the semiconductor chip subsequently disposed on the die attach region 210.
另外，於另一實施態樣中，亦可將該導線架中之複數電源導腳共同構成一晶片接置區，且將該些信號導腳及接地導腳設於該晶片接置區周圍，且該晶片接置區內之電源導腳尺寸大於該信號導腳及接地導腳尺寸。另外，對應相同輸入電壓之電源導腳，可將該些電源導腳相互連接。In addition, in another implementation manner, the plurality of power supply pins in the lead frame may together form a wafer connection area, and the signal guiding pins and the ground guiding pins are disposed around the wafer receiving area. And the size of the power supply lead in the wafer connection area is larger than the size of the signal lead and the ground lead. In addition, the power leads of the same input voltage can be connected to each other.
再者，該導線架結構亦可設計為僅有構成晶片接置區之接地導腳與設於該晶片接置區周圍之信號導腳，或僅有構成晶片接置區之電源導腳與設於該晶片接置區周之信號導腳。Furthermore, the leadframe structure can also be designed to have only the grounding guide pins constituting the wafer receiving area and the signal guiding pins disposed around the wafer receiving area, or only the power guiding pins and the constituting the wafer receiving area. The signal leads on the periphery of the wafer attachment area.
此外，該晶片接置區內之導腳除可選擇為接地導腳或電源導腳外、亦可選擇為接地導腳與電源導腳之組合，並使該接地導腳與電源導腳係相互分隔設置，例如將接地導腳設於晶片接置區之一側，同時將電源導腳設於晶片接置區之另一側，並在該晶片接置區周圍佈設信號導腳。In addition, the lead pin in the wafer connection area can be selected as a ground lead or a power lead, or can be selected as a combination of a ground lead and a power lead, and the ground lead and the power lead are mutually connected. The separation arrangement is, for example, that the grounding pin is disposed on one side of the wafer receiving area, and the power guiding pin is disposed on the other side of the wafer receiving area, and the signal guiding pin is disposed around the wafer receiving area.
復請配合參閱第3A及3B圖，係為本發明之導線架式半導體裝置之平面及剖面示意圖。Please refer to FIGS. 3A and 3B for a plan view and a cross-sectional view of the lead frame type semiconductor device of the present invention.
提供一如第2圖所示之導線架，其接地導腳211共同構成一晶片接置區210，並於該晶片接置區210周圍分佈有複數之信號導腳213及電源導腳212，且該晶片接置區210內之接地導腳211尺寸大於該信號導腳213及電源導腳212尺寸，接著將至少一半導體晶片30接置於該些接地導腳211所構成之晶片接置區210；該半導體晶片30係間隔一絕緣膠帶(tape)33而接置於該晶片接置區210上，以避免該半導體晶片30直接接觸導腳而發生短路問題。A lead frame as shown in FIG. 2 is provided, and the grounding pins 211 together form a chip receiving area 210, and a plurality of signal guiding pins 213 and power guiding pins 212 are distributed around the chip receiving area 210, and The size of the grounding pin 211 in the wafer receiving area 210 is larger than the size of the signal guiding pin 213 and the power guiding pin 212, and then the at least one semiconductor chip 30 is placed in the wafer receiving area 210 formed by the grounding pins 211. The semiconductor wafer 30 is placed on the wafer contact region 210 by an insulating tape 33 to prevent the semiconductor wafer 30 from directly contacting the lead pins and causing a short circuit problem.
接著利用銲線32將該半導體晶片30電性連接至建構該晶片接置區210之接地導腳211內端以及佈設於該晶片接置區210周圍之信號導腳213及電源導腳212之內端，之後再以封裝膠體34包覆該半導體晶片30、銲線32及該些接地導腳211、信號導腳213及電源導腳212，並使該些接地導腳211、信號導腳213及電源導腳212之外端外露出該封裝膠體34。The semiconductor wafer 30 is electrically connected to the inner end of the grounding pin 211 of the wafer receiving area 210 and the signal guiding pin 213 and the power guiding pin 212 disposed around the wafer receiving area 210. Then, the semiconductor wafer 30, the bonding wires 32, the grounding pins 211, the signal guiding pins 213 and the power guiding pins 212 are covered by the encapsulant 34, and the grounding pins 211 and the signal guiding pins 213 are The encapsulant 34 is exposed outside the outer end of the power supply pin 212.
請參閱第4圖，係為本發明之導線架第二實施例之平面示意圖，本實施例與前述實施例大致相同，主要差異在於係可將構成該晶片接置區210之接地導腳211(或電源導腳)中形成複數開孔40，藉以增加後續半導體晶片與封裝膠體之接觸面積，強化接著力，防止發生脫層問題。4 is a schematic plan view of a second embodiment of the lead frame of the present invention. The present embodiment is substantially the same as the foregoing embodiment. The main difference is that the ground lead 211 constituting the wafer receiving area 210 can be Or a plurality of openings 40 are formed in the power supply lead, thereby increasing the contact area between the subsequent semiconductor wafer and the encapsulant, and strengthening the adhesion force to prevent delamination.
請參閱第5圖，係為本發明之導線架式半導體裝置第三實施例之剖面示意圖，本實施例與前述實施例大致相同，主要差異在於將構成晶片接置區之複數接地導腳511(或電源導腳)相對低置於佈設於該晶片接置區周圍之信號導腳513，以供將半導體晶片50接置於該接地導腳511之晶片接置區上，並以銲線52電性連接至該接地導腳511及信號導腳513，如此，將可明顯縮短半導體晶片50電性連接至該信號導腳513之銲線長度，不僅節省製程成本，且可避免於形成封裝膠體時易受到模流衝擊而發生銲線偏移(wire sweep)問題，同時改善半導體晶片與導線架之電性連接品質。5 is a schematic cross-sectional view of a third embodiment of a lead frame type semiconductor device according to the present invention. This embodiment is substantially the same as the foregoing embodiment, and the main difference is that a plurality of ground pins 511 constituting a wafer connection region are formed ( Or the power supply pin is relatively low, and is disposed on the signal guiding pin 513 disposed around the chip receiving area for the semiconductor wafer 50 to be placed on the wafer receiving area of the grounding pin 511, and is electrically connected by the bonding wire 52. The connection between the grounding pin 511 and the signal guiding pin 513 is performed, so that the length of the bonding wire of the semiconductor wafer 50 electrically connected to the signal guiding pin 513 can be significantly shortened, which not only saves the process cost, but also avoids forming the encapsulant. It is susceptible to mold flow impact and wire sweep problems, while improving the electrical connection quality between the semiconductor wafer and the lead frame.
因此，本發明之導線架式半導體裝置及其導線架係提供一具有複數信號導腳、接地導腳及電源導腳之導線架，並使複數之接地導腳(或電源導腳)共同構成一晶片接置區，且將其餘之該些信號導腳及電源導腳(或接地導腳)分佈於該晶片接置區周圍，藉以獨立該些接地導腳與電源導腳，以改善接地彈跳問題，強化電性功能，同時使該晶片接置區內之接地導腳(或電源導腳)尺寸大於設於該晶片接置區周圍之信號導腳及電源導腳(或接地導腳)尺寸，以提供設於該晶片接置區上之半導體晶片良好散熱功能。Therefore, the lead frame type semiconductor device of the present invention and the lead frame thereof provide a lead frame having a plurality of signal lead pins, a ground lead pin and a power lead pin, and a plurality of ground lead pins (or power lead pins) are combined to form a lead frame. a chip connection area, and distributing the remaining signal lead pins and power lead pins (or ground lead pins) around the chip attaching area to separate the ground lead pins and the power lead pins to improve the ground bounce problem The electrical function is enhanced, and the size of the grounding lead (or power guiding pin) in the wafer receiving area is larger than the size of the signal guiding pin and the power guiding pin (or grounding pin) disposed around the receiving area of the chip. To provide a good heat dissipation function of the semiconductor wafer disposed on the wafer placement area.
上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習該項技術之人士均可在不違背本發明之精神與範疇下，對上述實施例進行修飾與變化。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
11．．．信號導腳11. . . Signal pin
12．．．絕緣薄片12. . . Insulating sheet
13．．．半導體晶片13. . . Semiconductor wafer
14．．．黏著層14. . . Adhesive layer
15．．．銲線15. . . Welding wire
16．．．封裝膠體16. . . Encapsulant
210．．．晶片接置區210. . . Wafer placement area
211．．．接地導腳211. . . Grounding lead
212．．．電源導腳212. . . Power lead
213．．．信號導腳213. . . Signal pin
30．．．半導體晶片30. . . Semiconductor wafer
32．．．銲線32. . . Welding wire
33．．．絕緣膠帶33. . . Insulation Tape
34．．．封裝膠體34. . . Encapsulant
40．．．開孔40. . . Opening
50．．．半導體晶片50. . . Semiconductor wafer
511．．．接地導腳511. . . Grounding lead
513．．．信號導腳513. . . Signal pin
52．．．銲線52. . . Welding wire
第1A及1B圖係為習知未設有晶片座之導線架式半導體封裝件架之平面及剖面示意圖；第2圖係為本發明之導線架第一實施例之平面示意圖；第3A及3B圖係為本發明之導線架式半導體裝置第一實施例之平面及剖面示意圖；第4圖係為本發明之導線架第二實施例之平面示意圖；以及第5圖係為本發明之導線架式半導體裝置第三實施例之剖面示意圖。1A and 1B are schematic plan and cross-sectional views of a conventional lead frame type semiconductor package frame without a wafer holder; Fig. 2 is a plan view showing a first embodiment of the lead frame of the present invention; 3A and 3B The drawings are a plan view and a cross-sectional view of a first embodiment of a lead frame type semiconductor device of the present invention; FIG. 4 is a plan view showing a second embodiment of the lead frame of the present invention; and FIG. 5 is a lead frame of the present invention. A schematic cross-sectional view of a third embodiment of a semiconductor device.
211．．．接地導腳211. . . Grounding lead
212．．．電源導腳212. . . Power lead
213．．．信號導腳213. . . Signal pin
30．．．半導體晶片30. . . Semiconductor wafer
32．．．銲線32. . . Welding wire
Claims (27)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097100956A TWI424547B (en) | 2008-01-10 | 2008-01-10 | Leadframe-based semiconductor device and leadframe thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097100956A TWI424547B (en) | 2008-01-10 | 2008-01-10 | Leadframe-based semiconductor device and leadframe thereof |
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| TWI424547B true TWI424547B (en) | 2014-01-21 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5234866A (en) * | 1985-03-25 | 1993-08-10 | Hitachi, Ltd. | Semiconductor device and process for producing the same, and lead frame used in said process |
| TWI245399B (en) * | 2004-03-11 | 2005-12-11 | Advanced Semiconductor Eng | Leadframe with die pad |
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2008
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5234866A (en) * | 1985-03-25 | 1993-08-10 | Hitachi, Ltd. | Semiconductor device and process for producing the same, and lead frame used in said process |
| TWI245399B (en) * | 2004-03-11 | 2005-12-11 | Advanced Semiconductor Eng | Leadframe with die pad |
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