TW200931619A - Leadframe-based semiconductor device and leadframe thereof - Google Patents

Leadframe-based semiconductor device and leadframe thereof Download PDF

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Publication number
TW200931619A
TW200931619A TW097100956A TW97100956A TW200931619A TW 200931619 A TW200931619 A TW 200931619A TW 097100956 A TW097100956 A TW 097100956A TW 97100956 A TW97100956 A TW 97100956A TW 200931619 A TW200931619 A TW 200931619A
Authority
TW
Taiwan
Prior art keywords
lead
wafer
lead frame
pins
signal
Prior art date
Application number
TW097100956A
Other languages
Chinese (zh)
Other versions
TWI424547B (en
Inventor
Ya-Yi Lai
Shu-Chih Chiu
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW097100956A priority Critical patent/TWI424547B/en
Publication of TW200931619A publication Critical patent/TW200931619A/en
Application granted granted Critical
Publication of TWI424547B publication Critical patent/TWI424547B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leadframe-based semiconductor device and the leadframe thereof are proposed. The invention includes providing a leadframe having a plurality of signal pins, ground pins and power pins; forming a chip-attach region by using the ground pins (or power pins); distributing the remaining signal pins and power pins (or ground pins) on the periphery of the chip-attach region, such that the ground or power pins can be isolated to improve on the problem of ground-jumping and enhance electrical performance; and making the pins deposed in the chip-attach region bigger than those surrounding the chip-attach region, thereby providing good heat-dissipation function for the chip disposed thereon.

Description

200931619 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置，尤指一種導線架式 半導體裝置及其導線架。 【先前技術】 傳統導線架（Lead Frame)式之半導體封裝件，如美 國專利第 5, 793, 108、6, G72, 243、6, 2G8, G23、5, 623, 123 專利揭示纟係提供一包含有晶片座及多數設於該晶片 〇座：圍之導腳的導線架，並將一晶片黏置於該晶片座上， 復藉複數條銲線電性連接晶片表面上各晶片銲墊 j Electrode Pads)至對應導腳，再以一封裝膠體包覆該 晶片及銲線而形成一導線架式半導體封裝件。 惟前述傳統之導線架結構設計在對應各式功能及作 用不同之晶片電性需求時，可供彈性調整該導線架之導腳 佈局空間誠屬有限’尤其面對高度集積化且輕薄型之晶片 〇時，戶斤需之導腳間距及封裝件尺寸愈來愈小，該傳統導線 架可供強化電性表現之設計方式已大幅限制，不易有改盖 請參閱第1A及1B圖，蓉於前述傳統導線架設計之缺 失，美國專利第 4, 943, 843、4, 937, 656、5, 234, 866 遂揭 不一種未设有晶片座之導線牟式jk ^ Β» 4U. y, 守琢木式牛導體封裝件，其係包括 有：複數信號（signal)導腳u ; 一絕緣薄片12，係設置 於部分信號導腳11上；一半導艚曰H1Q ^如 干等體日日片13 ’係藉由黏著層 14而接置於該絕緣薄片12上·遴叙pp 々以上，複數鋅線15，係電性連接 110638 5 200931619 ' 該半導體晶月13及信號導腳11内端；以及封裝膠體16， ' 係包覆該信號導腳11内端、絕緣薄片12、半導體晶片13 及銲線15，並使該信號導腳11外端外露出該封裳膠體 16。俾藉由省去傳統導線架之晶片座設置，以提供信號導 腳具有較充足之布局空間。 然而在半導體晶片電性需求愈來愈高之情況下，對於 信號、電源、及接地之輸入/輸出（I/O)相互間的設計匹配 性愈來愈重要，因此前述之導線架結構已無法滿足現今電 Ο性之需求。 再者’前述導線架中延伸至晶片下方作為支樓晶片之 信號導腳設計，僅考慮該些信號導腳相對於晶片銲塾之佈 局，確已無法滿足現今高電性及高散熱性之電子商品需 求。尤其因目前高頻電子產品特性為信號的上升時間 (rise time)愈來愈短、積體電路（〗c)的輸入/輸出（1/〇) 接腳愈來愈多、接腳的接線密度（i nterc〇nnects dens i ty ) ◎愈來愈高，同時，IC雜散效應也日趨嚴重，通常對於上 升h•間在ns這個數量級時，當信號上升時間縮短時，或/ 及電流量增加時，電流的變化率就會增大，接地反彈的電 壓也就增加，此時接地平面已經不是理想的零電位，而電 源端也不是理想的直流電位。當系統的速度愈快，而且為 數眾多+的邏輯㈣時#換狀態時就愈容易造成嚴重的電 壓陷落（Power Drop)現t，或稱為接地彈跳（Gr〇und Bounce) ° 傳統為簡化處理問題，通常把電源和接地都當成理想 6 110638 200931619 .況來處理，但在高速設計中，這種簡化卻會造成越來 越難以預測電路系統在實現後的行為。儘管電路設計直接 可，結果是從信號完整性上表現出來的，但絕不= .f、略了電源完整性的設計，因為電源完整性被破壞後終 =會反映至信號的完整性’而且在很多情形下，影響信號 °變、擾動的主要原因是電源系統，例如：多電源/接地 平面的分割不理想、接地反彈雜訊太大、電流分配的不均 等。 Ο α此如何提供一種導線架結構與導線架式半導體封 裝^牛可有效強化電性功能、降低接地彈跳問題及提升散熱 效月匕貝已成為目前亟欲解決之課題。 【發明内容】 鑑於上述習知技術問題點，本發明之_目的係在提供 -種可強化電性功能之導線架式半導體裝置及其導線架。 、本發月之又一目的係提供一種可降低接地彈跳問題 ❹之導線架式半導體裝置及其導線架。 本發明之再一目的係提供一種可提升散熱效能之導 線架式半導體裝置及其導線架。 為達上揭目的，本發明揭露一種導線架式半導體裝 置，係包括：-導線架，該導線架具有複數信號導腳及複 數接地導腳，其中該些接地導腳共同構成一晶片接置區， 該些信號導腳則分佈於該晶片接置區周圍，且該晶月接置 區内之接地導腳尺寸大於該信號導腳尺寸；至少一半導體 晶片，係接置於該些接地導腳之晶片接置區上；以及複數 110638 7 200931619 *鮮線’係供該半導體日日日片電性連接至該信號導腳及接地導 ，腳。該導線架復包括有分佈於該晶片接置區周圍之電源導 腳，其中，該晶片接置區内之接地導腳尺寸大於該電源導 腳尺寸，半導體晶片係透過複數銲線電性連接至該電源導 腳，並形成有一包覆該導線架、半導體晶片及輝線之封裝 膠體，且外露該信號導腳、電源導腳及接地導腳之外端。 本發明之導線架式半導體裝置另一較佳實施態樣係 包括·導線架，該導線架具有複數信號導腳及複數電源 Ο導腳’其中該些電源導腳共同構成一晶片接置區，該些信 號導腳則分佈於該晶片接置區周圍，且該晶片接置區内之 電源導腳尺寸大於該信號導腳尺寸；至少一半導體晶片， 係接置於該些電源導腳之晶片接置區上；以及複數銲線， 係供該半導體晶片電性連接至該信號導腳及電源導腳^該 導線架復包括有分佈於該晶片接置區周圍之接地導腳其 中，該晶片接置區内之電源導腳尺寸大於該接地導腳尺 ❹寸，半導體晶片係透過複數銲線電性連接至該接地導腳， 並形成有一包覆該導線架、半導體晶片及銲線之封裝膠 體，且外露該信號導腳、電源導腳及接地導腳之外端。 本發明復揭示一種導線架，係包括有：複數接地導 腳，該些接地導腳共同構成一晶片接置區，以供接置半導 體晶片；以及複數信號導腳，分佈於該晶片接置區周圍， 其中該晶片接置區内之接地導腳尺寸大於該信號導腳尺 寸。該導線架復包括有分佈於該晶片接置區周圍之電源導 腳，其中，該晶片接置區内之接地導腳尺寸大於該電源導 110638 8 200931619 ' 腳尺寸。 * 本發明之導線架另一較佳實施態樣係包括：複數電源 導腳，該些電源導腳共同構成一晶片接置區，以供接置半 導體晶片；以及複數信號導腳，分佈於該晶片接置區周 _圍，其中該晶片接置區内之電源導腳尺寸大於該信號導腳 .尺寸。該導線架復包括有分佈於該晶片接置區周圍之接地 導腳，其中，該晶片接置區内之電源導腳尺寸大於該接地 導腳尺寸。 Ο 本發明之導線架又一較佳實施態樣係包括··複數導 腳，該些導腳共同構成一晶片接置區，以供接置半導體晶 片，以及另一複數導腳，分佈於該晶片接置區周圍，其中 該晶片接置區内之導腳尺寸大於該晶片接置區周圍之導 腳尺寸。該晶片接置區内之導腳可選擇為接地導腳、或為 電源導腳、亦或為接地導腳與電源導腳之組合（該接地導 腳與電源導腳係相互分隔設置），而該晶片接置區周圍之 ❹導腳則為信號導腳。 再者，本發明復可於前述之導線架中，對於構成晶片 接置區之接地導腳及/或電源導腳中形成複數開孔，藉以 增加半導體晶片與封裝膠體之接觸面積，強化接著力，防 止發生脫層問題；另外，復可將構成晶片接置區之複數接 地導腳及/或電源導腳相對低置於佈設於該晶片接置區周 圍之信號導腳’以縮短半導體晶片電性連接至該信號導腳 之鲜線長度’藉以節省製程成本，避免發生銲線偏移（wire sweep)問題’同時改善半導體晶片與導線架之電性連接品 9 110638 200931619 •質。 ' 因此，本發明之導線架式半導體裝置及其導線架係提 供一具有複數信號導腳、接地導腳及電源導腳之導線架， 並使複數之接地導腳（或電源導腳）共同構成一晶片技置 區’且將其餘之該些信號導腳及電源導腳（或接地導腳） 分佈於該晶片接置區周圍，藉以獨立該些接地導腳與電源 導腳’以改善接地彈跳問題’強化電性功能，同時使該晶 片接置區内之接地導腳（或電源導腳）尺寸大於設於該晶 G片接置區周圍之信號導腳及電源導腳（或接地導腳）尺 寸’以提供設於該晶片接置區上之半導體晶片良好散熱功 能。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可.由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 Q 請參閱第2圖，係為本發明之導線架式平面示意圖。 該導線架係包括有複數接地導腳211，該些接地導腳 211共同構成一晶片接置區210;複數信號導腳213，分 佈於該晶片接置區210周圍；以及複數電源導腳212，分 佈於該晶片接置區210周圍，且該晶片接置區210内之接 地導腳211尺寸大於該信號導腳213及電源導腳212尺 寸。 亦即使該些接地導腳211與電源導腳212係相對獨立 設置’以改善接地彈跳問題，強化電性功能，同時使該晶 10 110638 200931619 片接置區210内之接地導腳211尺寸大於設於該晶片接置 ’區210周圍之信號導腳213及電源導腳212尺寸，進而提 供後績0交於€亥晶片接置區210上之半導體晶片良好之散 熱功能。 另外，於另一實施態樣中’亦可將該導線架中之複數 電源導腳共同構成一晶片接置區’且將該些信號導腳及接 地導腳設於該晶片接置區周圍，且該晶片接置區内之電源 導腳尺寸大於該信號導腳及接地導腳尺寸。另外，對應相 Ο同輸入電壓之電源導腳’可將該些電源導腳相互連接。 再者’該導線架結構亦可設計為僅有構成晶片接置區 之接地導腳與設於該晶片接置區周圍之信號導腳，或僅有 構成晶片接置區之電源導腳與設於該晶片接置區周之信 號導腳。 此外’該晶片接置區内之導腳除可選擇為接地導腳或 電源導腳外'亦可選擇為接地導腳與電源導腳之組合，並 〇使該接地導腳與電源導腳係相互分隔設置，例如將接地導 腳設於晶片接置區之一侧，同時將電源導腳設於晶片接置 區之另一侧’並在該晶片接置區周圍佈設信號導腳。 復請配合參閱第3A及3B圖，係為本發明之導線架式 半導體裝置之平面及剖面示意圖。 提供一如第2圖所示之導線架，其接地導腳211共同 構成一晶片接置區210，並於該晶片接置區210周圍分佈 有複數之信號導腳213及電源導腳212,且該晶片接置區 210内之接地導腳211尺寸大於該信號導腳213及電源導 11 110638 200931619 ’ 腳212尺寸，接著將至少一半導體晶片30接置於該些接 地導腳211所構成之晶片接置區210，該半導體晶片30 係間隔一絕緣膠帶（tape)33而接置於該晶片接置區210 上’以避免該半導體晶片30直接接觸導腳而發生短路問 題。 接著利用銲線32將該半導體晶片30電性連接至建構 該晶片接置區210之接地導腳211内端以及佈設於該晶片 接置區210周圍之信號導腳213及電源導腳212之内端， Ο之後再以封裝膠體34包覆該半導體晶片30、銲線32及 該些接地導腳211、信號導腳213及電源導腳212，並使 該些接地導腳211、信號導腳213及電源導腳212之外端 外露出該封裝膠體34。 請參閱第4圖，係為本發明之導線架第二實施例之平 面示意圖，本實施例與前述實施例大致相同，主要差異在 於係可將構成該晶片接置區210之接地導腳211 (或電源 ❹導腳）中形成複數開孔40，藉以增加後續半導體晶片與封 裝膠體之接觸面積，強化接著力，防止發生脫層問題。 5月參閱第5圖，係為本發明之導線架式半導體裝置第 三實施例之剖面示意圖，本實施例與前述實施例大致相 同，主要差異在於將構成晶片接置區之複數接地導腳200931619 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a lead frame type semiconductor device and a lead frame thereof. [Prior Art] A conventional lead frame type semiconductor package, such as U.S. Patent Nos. 5,793,108, 6, G72, 243, 6, 2G8, G23, 5, 623, 123 The utility model comprises a wafer holder and a plurality of lead frames disposed on the lead legs of the wafer holder: a wafer is adhered to the wafer holder, and a plurality of bonding wires are electrically connected to each of the wafer pads on the surface of the wafer. Electrode Pads) to the corresponding lead pins, and then encapsulating the wafer and the bonding wires with a package of glue to form a lead frame type semiconductor package. However, when the conventional lead frame structure is designed to meet the electrical requirements of various functions and functions, the space for guiding the lead frame of the lead frame can be flexibly adjusted, especially for highly integrated and thin wafers. At the same time, the distance between the guide pins and the package size of the households is getting smaller and smaller. The design method of the traditional lead frame for enhancing the electrical performance has been greatly limited. It is not easy to change the cover. Please refer to Figures 1A and 1B. In the absence of the aforementioned conventional lead frame design, U.S. Patent Nos. 4,943,843, 4,937,656, 5,234, 866, the disclosure of which is incorporated herein by reference. The beech type cattle conductor package comprises: a plurality of signal guide pins u; an insulating sheet 12 is disposed on the partial signal guide pins 11; a half guide 艚曰 H1Q ^ such as a dry body day piece 13 ' is attached to the insulating sheet 12 by the adhesive layer 14 · 遴 pp 々 above, a plurality of zinc lines 15, electrically connected 110638 5 200931619 'the semiconductor crystal 13 and the signal pin 11 inner end; And encapsulating the body 16, 'covering the inner end of the signal pin 11 Edge of the sheet 12, the semiconductor wafer 13 and the bonding wire 15, and the signal of the leads exposed to the outer end 11 of the outer seal body 16 Sang.俾 By eliminating the need for a conventional lead frame wafer holder, the signal pin has ample layout space. However, as the electrical requirements of semiconductor wafers become higher and higher, the design matching between the input/output (I/O) of signals, power supplies, and grounding is becoming more and more important, so the aforementioned leadframe structure cannot be used. Meet the needs of today's power. Furthermore, the design of the signal guide leg extending from the lead frame to the underside of the wafer as a support wafer only considers the layout of the signal guide pins relative to the wafer soldering, and thus cannot meet the current high-electricity and high-heat dissipation electrons. Product demand. In particular, due to the current high-frequency electronic product characteristics, the rise time of the signal is getting shorter and shorter, and the input/output (1/〇) pin of the integrated circuit (〗 〖) is getting more and more, and the wiring density of the pin is increased. (i nterc〇nnects dens i ty ) ◎ Increasingly higher, at the same time, IC spurs are also becoming more and more serious. Generally, when the rise h• is in the order of ns, when the signal rise time is shortened, or / and the current amount is increased When the current changes rate, the voltage of the ground bounce increases, and the ground plane is not the ideal zero potential, and the power supply terminal is not the ideal DC potential. When the speed of the system is faster and the number of logics (4) is a large number of +, the more it is changed, the more likely it is to cause a serious voltage drop (Power Drop), or the ground bounce (Gr〇und Bounce). The problem is that power and ground are usually treated as ideals, but in high-speed designs, this simplification makes it increasingly difficult to predict the behavior of the system after implementation. Although the circuit design is straightforward, the result is expressed in terms of signal integrity, but never = .f, the design of the power integrity is abrupt, because the power integrity is destroyed and the final = will reflect the integrity of the signal' In many cases, the main cause of the influence of signal variation and disturbance is the power supply system. For example, the division of multiple power/ground planes is not ideal, the ground bounce noise is too large, and the current distribution is uneven. Ο α How to provide a lead frame structure and lead frame type semiconductor package ^ Niu can effectively enhance the electrical function, reduce the ground bounce problem and improve the heat dissipation effect. The mussel has become a problem to be solved. SUMMARY OF THE INVENTION In view of the above technical problems, the present invention is directed to providing a lead frame type semiconductor device capable of enhancing electrical functions and a lead frame thereof. Another object of this month is to provide a lead frame type semiconductor device and a lead frame thereof which can reduce the ground bounce problem. Still another object of the present invention is to provide a lead frame type semiconductor device and a lead frame thereof which can improve heat dissipation performance. In order to achieve the above, a lead frame type semiconductor device includes: a lead frame having a plurality of signal pins and a plurality of ground pins, wherein the ground pins together form a wafer connection region The signal guiding pins are distributed around the chip receiving area, and the grounding lead size in the crystal moon receiving area is larger than the signal guiding pin size; at least one semiconductor chip is connected to the ground guiding pins. On the wafer receiving area; and a plurality of 110638 7 200931619 * fresh line 'for the semiconductor day and day is electrically connected to the signal pin and the grounding guide, the foot. The lead frame includes a power supply pin distributed around the chip connection area, wherein a ground lead size of the wafer connection area is larger than the power supply lead size, and the semiconductor chip is electrically connected to the plurality of bonding wires to The power supply pin is formed with a package encapsulation covering the lead frame, the semiconductor chip and the glow wire, and the signal pin, the power supply pin and the ground pin are exposed. Another preferred embodiment of the lead frame type semiconductor device of the present invention includes a lead frame having a plurality of signal pins and a plurality of power supply pins, wherein the power supply pins collectively constitute a wafer connection region. The signal pins are distributed around the wafer connection region, and the power supply lead size in the wafer connection region is larger than the signal guide pin size; at least one semiconductor chip is connected to the chip disposed on the power supply pins. And a plurality of bonding wires for electrically connecting the semiconductor chip to the signal pin and the power guiding pin. The lead frame includes a grounding pin distributed around the chip receiving area, the chip The size of the power supply lead in the connection area is larger than the ground lead size, and the semiconductor chip is electrically connected to the ground lead through a plurality of bonding wires, and a package covering the lead frame, the semiconductor wafer and the bonding wire is formed. The gel is exposed to the outside of the signal pin, the power pin, and the ground pin. The present invention further discloses a lead frame comprising: a plurality of ground lead pins, the ground lead pins collectively forming a wafer receiving area for receiving a semiconductor wafer; and a plurality of signal guiding legs distributed in the wafer receiving area Surrounding, wherein the grounding lead size in the wafer receiving area is larger than the signal guiding size. The lead frame includes a power supply pin distributed around the wafer connection area, wherein the ground lead size in the wafer connection area is larger than the power supply 110638 8 200931619' foot size. * Another preferred embodiment of the lead frame of the present invention includes: a plurality of power supply pins, the power supply pins collectively forming a wafer connection region for receiving a semiconductor wafer; and a plurality of signal pins disposed thereon The wafer connection area is circumferentially surrounding, wherein the power supply lead size in the wafer connection area is larger than the signal lead size. The lead frame includes a grounding lead distributed around the receiving area of the wafer, wherein a size of the power guiding pin in the wafer receiving area is larger than the size of the grounding lead. A further preferred embodiment of the lead frame of the present invention includes a plurality of lead pins, which together form a wafer receiving area for receiving a semiconductor wafer, and another plurality of lead pins distributed over the plurality of leads Around the wafer attachment region, wherein the size of the lead within the wafer attachment region is greater than the size of the guide pin around the wafer attachment region. The lead pin in the wafer connection area can be selected as a ground lead, or a power lead, or a combination of a ground lead and a power lead (the ground lead and the power lead are separated from each other), and The guide pin around the wafer attachment area is a signal pin. Furthermore, the present invention is applicable to the above-mentioned lead frame, and a plurality of openings are formed in the ground lead and/or the power guiding pin constituting the wafer receiving area, thereby increasing the contact area between the semiconductor wafer and the encapsulant, and strengthening the bonding force. To prevent the occurrence of delamination; in addition, the plurality of grounding leads and/or power guiding pins constituting the wafer receiving area are relatively low placed on the signal guiding pins disposed around the wafer receiving area to shorten the semiconductor wafer The length of the fresh wire connected to the signal pin 'to save process cost and avoid the wire sweep problem' while improving the electrical connection between the semiconductor wafer and the lead frame 9 110638 200931619. Therefore, the lead frame type semiconductor device and the lead frame thereof of the present invention provide a lead frame having a plurality of signal lead pins, a ground lead pin and a power lead pin, and a plurality of ground lead pins (or power lead pins) are combined a chip technology area' and distributing the remaining signal pins and power leads (or ground pins) around the wafer contact area, thereby independently connecting the ground pins and the power pin 'to improve the ground bounce The problem 'intensifies the electrical function, and at the same time, the size of the grounding lead (or power guiding pin) in the wafer receiving area is larger than the signal guiding pin and the power guiding pin (or the grounding guiding pin) disposed around the connecting area of the crystal G piece. The size 'to provide a good heat dissipation function for the semiconductor wafers disposed on the wafer attachment regions. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily understand the other advantages and advantages of the present invention from the disclosure. Q Please refer to Fig. 2, which is a plan view of the lead frame of the present invention. The lead frame includes a plurality of grounding pins 211, which together form a wafer receiving area 210; a plurality of signal guiding pins 213 are distributed around the wafer receiving area 210; and a plurality of power guiding pins 212, The grounding lead 211 in the wafer receiving area 210 is larger than the signal guiding leg 213 and the power guiding pin 212. Even if the grounding pins 211 and the power guiding pins 212 are relatively independently disposed to improve the ground bounce problem, the electrical function is enhanced, and the grounding pin 211 in the chip receiving area 210 of the crystal 10 110638 200931619 is larger than the setting. The size of the signal pin 213 and the power pin 212 around the 'area 210' is connected to the wafer, thereby providing a good heat dissipation function of the semiconductor chip that has been transferred to the wafer receiving area 210. In another embodiment, the plurality of power supply pins in the lead frame may also form a chip connection region, and the signal pins and ground pins are disposed around the wafer connection region. And the size of the power supply lead in the wafer connection area is larger than the size of the signal lead and the ground lead. In addition, the power leads can be connected to each other corresponding to the power supply pins of the same input voltage. Furthermore, the lead frame structure can also be designed such that only the ground lead pins constituting the wafer connection region and the signal guide pins disposed around the wafer connection region, or only the power supply pins and devices constituting the wafer connection region The signal leads on the periphery of the wafer attachment area. In addition, the 'leading pin in the wafer connection area can be selected as a grounding pin or a power guiding pin', and can also be selected as a combination of a grounding pin and a power guiding pin, and the grounding pin and the power guiding pin are Separately disposed, for example, the grounding lead is disposed on one side of the wafer receiving area, and the power guiding pin is disposed on the other side of the wafer receiving area', and a signal guiding pin is disposed around the wafer receiving area. Referring to Figures 3A and 3B, it is a plan view and a cross-sectional view of the lead frame type semiconductor device of the present invention. A lead frame as shown in FIG. 2 is provided, and the grounding pins 211 together form a chip receiving area 210, and a plurality of signal guiding pins 213 and power guiding pins 212 are distributed around the chip receiving area 210, and The size of the grounding pin 211 in the chip receiving area 210 is larger than the size of the signal guiding pin 213 and the power guiding 11 110638 200931619', and then the at least one semiconductor chip 30 is placed on the chip formed by the grounding pins 211. In the connection region 210, the semiconductor wafer 30 is placed on the wafer connection region 210 by an insulating tape 33 to prevent the semiconductor wafer 30 from directly contacting the lead pins to cause a short circuit problem. The semiconductor wafer 30 is electrically connected to the inner end of the grounding pin 211 of the wafer receiving area 210 and the signal guiding pin 213 and the power guiding pin 212 disposed around the wafer receiving area 210. The semiconductor wafer 30, the bonding wires 32, the grounding pins 211, the signal guiding pins 213 and the power guiding pins 212 are covered by the encapsulant 34, and the grounding pins 211 and the signal guiding pins 213 are grounded. The encapsulant 34 is exposed outside the outer end of the power supply pin 212. 4 is a schematic plan view of a second embodiment of the lead frame of the present invention. The present embodiment is substantially the same as the foregoing embodiment. The main difference is that the ground lead 211 constituting the wafer receiving area 210 can be Or a plurality of openings 40 are formed in the power supply lead, thereby increasing the contact area between the subsequent semiconductor wafer and the encapsulant, and strengthening the adhesion to prevent delamination. Referring to Fig. 5, a cross-sectional view of a third embodiment of the lead frame type semiconductor device of the present invention is substantially the same as the foregoing embodiment, and the main difference is that a plurality of ground lead pins constituting the wafer attaching region are formed.

腳511及信號導腳513，如此， -電性連接至該接地導 將可明顯縮短半導體晶片 110638 12 200931619 • 50電性連接至該信號導腳5i3之銲線長度，不僅節省製 程成本，且可避免於形成封裝膠體時易受到模流衝擊而發 生銲線偏移（wire sweep)問題，同時改善半導體晶片與導 線架之電性連接品質。 因此，本發明之導線架式半導體裝置及其導線架係提 供一具有複數信號導腳、接地導腳及電源導腳之導線架， 並使複數之接地導腳（或電源導腳）共同構成一晶片接置 區’且將其餘之該些信號導腳及電源導腳（或接地導腳） Ο分佈於該晶片接置區周圍，藉以獨立該些接地導腳與電源 導腳，以改善接地彈跳問題，強化電性功能，同時使該晶 片接置區内之接地導腳（或電源導腳）尺寸大於設於該晶 片接置區周圍之信號導腳及電源導腳（或接地導腳）尺 寸’以提供設於該晶片接置區上之半導體晶片良好散執功 能。 上述實施例僅為例示性說明本發明之原理及其功 ❹效，而非用於限制本發明。任何熟習該項技術之人士均可 在不違背本發明之精神與範嘴下，對上述實施例進行修飾 與變化。因此，本發明之權利保護範圍，應如後述之申請 專利範圍所列。 【圖式簡單說明】 片座之導線架式半導 第1A及1B圖係為習知未設有晶 體封裝件架之平面及剖面示意圖；The foot 511 and the signal guiding pin 513, as such, electrically connected to the grounding conductor can significantly shorten the length of the bonding wire of the semiconductor wafer 110638 12 200931619 • 50 electrically connected to the signal guiding pin 5i3, thereby saving process cost and It avoids the problem of wire sweep caused by the impact of the mold flow when forming the encapsulant, and improves the electrical connection quality between the semiconductor wafer and the lead frame. Therefore, the lead frame type semiconductor device of the present invention and the lead frame thereof provide a lead frame having a plurality of signal lead pins, a ground lead pin and a power lead pin, and a plurality of ground lead pins (or power lead pins) are combined to form a lead frame. The chip connection area 'and the remaining signal pins and the power supply pins (or ground pins) are distributed around the wafer connection area, so as to separate the ground pins and the power supply pins to improve the ground bounce The problem is to strengthen the electrical function, and at the same time, the size of the grounding lead (or power guiding pin) in the receiving area of the wafer is larger than the size of the signal guiding pin and the power guiding pin (or grounding pin) disposed around the connecting area of the chip. 'To provide a good dispersion function of the semiconductor wafers disposed on the wafer placement area. The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application to be described later. [Simple diagram of the diagram] The lead frame type semi-conductor of the pedestal 1A and 1B is a plan view and a cross-sectional view of a conventional crystal package holder;

第 圖係為本發明之導線架第 一實施例之平面示意 110638 13 200931619 • 第3A及3B圖係為本發明之導線架式半導體裝置第一 貫施例之平面及剖面示意圖； 弟4圖係為本發明之導線fk弟一貫施例之平面示意 圖；以及 第5圖係為本發明之導線架式半導體裝置第三實施 - 例之剖面示意圖。 、 【主要元件符號說明】 11 信號導腳 12 絕緣薄片 13 半導體晶片 14 黏著層 15 銲線 16 封裝膠體 210 晶片接置區 211 接地導腳 212 電源導腳 213 信號導腳 30 半導體晶片 32 銲線 33 絕緣膠帶 34 封裝膠體 40 開孔 50 半導體晶片 511 接地導腳 513 信號導腳 52 銲線 110638 14The figure is a plan view of a first embodiment of the lead frame of the present invention. 110638 13 200931619. The drawings 3A and 3B are a plan view and a cross-sectional view of a first embodiment of the lead frame type semiconductor device of the present invention; A schematic plan view of a conventional embodiment of the wire fk of the present invention; and FIG. 5 is a schematic cross-sectional view showing a third embodiment of the lead frame type semiconductor device of the present invention. [Major component symbol description] 11 Signal pin 12 Insulating foil 13 Semiconductor wafer 14 Adhesive layer 15 Solder wire 16 Package colloid 210 Wafer connection area 211 Grounding pin 212 Power supply pin 213 Signal pin 30 Semiconductor wafer 32 Solder wire 33 Insulating tape 34 Encapsulant 40 Opening 50 Semiconductor wafer 511 Grounding pin 513 Signal pin 52 Bonding wire 110638 14

Claims (1)

200931619 '十、申請專利範圍： 1. 一種導線架式半導體裝置，係包括： 一導線架，該導線架具有複數信號導腳及複數接 地導腳，其中該些接地導腳共同構成一晶片接置區， 該些信號導腳則分佈於該晶片接置區周圍，且該晶片 接置區内之接地導腳尺寸大於該信號導腳尺寸； 至少一半導體晶片，係接置於該些接地導腳之晶 片接置區上；以及 ❹ 複數銲線’係用以電性連接該半導體晶片至該信 號導腳及接地導腳。 2·如申請專利範圍第1項之導線架式半導體裝置，其 中’該導線架復包括有分佈於該晶片接置區周圍之電 源導腳。 3. 如申請專利範圍第2項之導線架式半導體裝置，其 中’該晶片接置區内之接地導腳尺寸大於該電源導腳 λ 尺寸0 〇 4. 如申請專利範圍第2項之導線架式半導體裝置，其 中’該半導體晶片係透過複數銲線電性連接至該電源 導腳。 5. 如申請專利範圍第4項之導線架式半導體裝置，包括 有一包覆該導線架、半導體晶片及銲線之封裝朦體， 並外露該信號導腳、電源導腳及接地導腳之外端。 6. 如申請專利範圍第1項之導線架式半導體裝置，其 中，該晶片接置區之接地導腳形成有複數開孔。 15 110638 200931619 .7.如申請專利範圍第丨項之導線架式半導體裝置，其 中，該晶片接置區之接地導腳相對低置於佈設於該晶 片接置區周圍之信號導腳。 8. 如申請專利範圍第1項之導線架式半導體裝置，其 .中，s亥半導體晶片係間隔一絕緣膠帶（tape )而接置於 该晶片接置區。 9. 一種導線架式半導體裝置，係包括： 一導線架，該導線架具有複數信號導腳及複數電 〇 源導腳’其中該些電源導腳共同構成一晶片接置區， 該些信號導腳則分佈於該晶片接置區周圍，且該晶片 接置區内之電源導腳尺寸大於該信號導腳尺寸； 至少一半導體晶片’係接置於該些電源導腳之晶 片接置區上；以及 複數銲線，係用以電性連接該半導體晶片至該信 说導腳及電源導腳。 ❹10.如申請專利範圍第9項之導線架式半導體裝置，其 中’該導線架復包括有分佈於該晶片接置區周圍之接 地導腳。 11_如申請專利範圍第10項之導線架式半導體裝置其 中’該晶片接置區内之電源導腳尺寸大於該接地導腳 尺寸。 12.如申请專利範圍第1〇項之導線架式半導體裝置其 中，该半導體晶片係透過複數銲線電性連接至該接地 導腳。 16 110638 200931619 13. 如申請專利範圍第丨2項之導線架式半導體裝置，包 ， 括有一包覆該導線架、半導體晶片及銲線之封裝^ 體，並外露該信號導腳、電源導腳及接地導腳之外端二 14. 如申請專利範圍第9項之導線架式半導體裝置，其 .中，該晶片接置區之電源導腳形成有複數開孔。 15. 如申請專利範圍第9項之導線架式半導體裝置，其 中該曰曰片接置區之電源導腳相對低置於佈設於該晶 片接置區周圍之信號導腳。 ❹16.如申請專利範圍第9項之導線架式半導體裝置，其 中，該半導體晶片係間隔一絕緣勝帶而接置於該晶片 接置區。 17· —種導線架，係包括： 複數導腳’該些導腳共同構成一晶片接置區，以 供接置半導體晶片；以及 另一複數導腳’分佈於該晶片接置區周圍，其中 〇 該晶片接置區之導腳尺寸大於該晶片接置區周圍之 導腳尺寸。 18.如申請專利範圍第17項之導線架，其中，該晶片接 置區之導腳為接地導腳。 it如申請專利範圍第18項之導線架其中’該晶片接 置區周圍之導腳為信號導腳。 20.如申請專利範圍第17項之導線架，其中，該晶片接 置區之導腳為電源導腳。 21·如申請專利範圍第2〇項之導線架，其中，該晶片接 17 110638 200931619 / 置區周圍之導腳為信號導腳。 22.如申請專利範圍第17項之導線架，其中，該晶片接 置區之導腳形成有複數開孔。 23·如中請專利範圍第17項之導線架，其中，該晶片接 .置區之導腳相對低置於佈設於該晶片接置區周圍之 導腳。 2 4. —種導線架，係包括： 複數電源導腳及複數接地導腳，該些電源導腳及 〇 接地導腳共同構成一晶片接置區，以供接置半導體晶 片；以及 複數信號導腳，分佈於該晶片接置區周圍，其中 該晶片接置區内之電源導腳及接地導腳尺寸大於該 信號導腳尺寸。 25.如申請專利範圍第24項之導線架，其中，該晶片接 置區之電源導腳及接地導腳形成有複數開孔。 ❹26.如申請專利範圍第24項之導線架，其中，該晶片接 置區之電源導腳及接地導腳相對低置於佈設於該晶 片接置區周圍之信號導腳。 27.如申請專利範圍第24項之導線架，其中，該接地導 腳設於晶片接置區之一側，該電源導腳設於晶片接置 區之另一侧。 18 110638200931619 '10. Patent application scope: 1. A lead frame type semiconductor device comprising: a lead frame having a plurality of signal pins and a plurality of ground pins, wherein the ground pins together form a wafer connection The signal guiding pins are distributed around the chip receiving area, and the grounding lead size in the wafer receiving area is larger than the signal guiding pin size; at least one semiconductor chip is connected to the ground guiding pins. And the plurality of bonding wires are electrically connected to the semiconductor wafer to the signal pin and the ground pin. 2. The lead frame type semiconductor device of claim 1, wherein the lead frame comprises a power supply lead distributed around the wafer attachment area. 3. The lead frame type semiconductor device of claim 2, wherein the size of the grounding lead in the mounting area of the wafer is larger than the size of the power lead λ 0 〇 4. The lead frame of claim 2 A semiconductor device in which the semiconductor wafer is electrically connected to the power supply lead through a plurality of bonding wires. 5. The lead frame type semiconductor device of claim 4, comprising a package body covering the lead frame, the semiconductor wafer and the bonding wire, and exposing the signal guiding pin, the power guiding pin and the grounding pin end. 6. The lead frame type semiconductor device of claim 1, wherein the ground lead of the wafer attachment region is formed with a plurality of openings. A lead frame type semiconductor device according to the invention of claim 1, wherein the grounding lead of the wafer receiving area is relatively low placed on a signal lead disposed around the wafer receiving area. 8. The lead frame type semiconductor device according to claim 1, wherein the semiconductor wafer is placed in the wafer contact region by an insulating tape. 9. A lead frame type semiconductor device, comprising: a lead frame having a plurality of signal lead pins and a plurality of power source lead pins, wherein the power lead pins collectively constitute a wafer connection region, and the signal guides The foot is distributed around the wafer connection area, and the power supply lead size in the wafer connection area is larger than the signal guide size; at least one semiconductor chip is connected to the wafer connection area of the power supply pins. And a plurality of bonding wires for electrically connecting the semiconductor chip to the signal guiding pin and the power guiding pin. The lead frame type semiconductor device of claim 9, wherein the lead frame includes a ground lead disposed around the wafer receiving area. 11_ The lead frame type semiconductor device of claim 10, wherein the size of the power supply lead in the wafer attachment region is larger than the size of the ground lead. 12. The lead frame type semiconductor device of claim 1, wherein the semiconductor wafer is electrically connected to the ground lead via a plurality of bonding wires. 16 110638 200931619 13. The lead frame type semiconductor device according to claim 2, comprising a package covering the lead frame, the semiconductor wafer and the bonding wire, and exposing the signal guiding pin and the power guiding pin And a grounding lead external end. 14. The lead frame type semiconductor device according to claim 9, wherein the power guiding leg of the wafer receiving area is formed with a plurality of openings. 15. The lead frame type semiconductor device of claim 9, wherein the power supply pin of the die attaching region is relatively low placed on a signal pin disposed around the chip attaching region. The lead frame type semiconductor device of claim 9, wherein the semiconductor wafer is interposed between the semiconductor chip and the wafer contact region. 17. A type of lead frame comprising: a plurality of lead legs collectively forming a wafer attachment area for receiving a semiconductor wafer; and another plurality of lead pins 'distributed around the wafer attachment area, wherein The lead size of the wafer attachment area is larger than the size of the lead around the wafer attachment area. 18. The lead frame of claim 17, wherein the lead of the wafer contact area is a ground lead. It is the lead frame of claim 18, wherein the guide pin around the wafer attachment area is a signal pin. 20. The lead frame of claim 17, wherein the lead of the wafer contact area is a power lead. 21. The lead frame of claim 2, wherein the lead is connected to a signal guide pin around the 110 110638 200931619 / area. 22. The lead frame of claim 17, wherein the lead of the wafer attachment region is formed with a plurality of openings. 23. The lead frame of claim 17, wherein the lead of the wafer receiving area is relatively low and disposed on a lead disposed around the receiving area of the wafer. 2 4. A lead frame comprising: a plurality of power supply pins and a plurality of ground pins, the power pins and the ground pins together forming a wafer connection region for receiving the semiconductor wafer; and the plurality of signal guides The foot is distributed around the wafer receiving area, wherein the power guiding pin and the grounding lead in the wafer receiving area are larger than the signal guiding size. 25. The lead frame of claim 24, wherein the power supply lead and the ground lead of the wafer connection area are formed with a plurality of openings.导线26. The lead frame of claim 24, wherein the power lead and the ground lead of the wafer connection area are relatively low placed on signal leads disposed around the wafer attachment area. 27. The lead frame of claim 24, wherein the grounding pin is disposed on one side of the wafer receiving area, and the power guiding pin is disposed on the other side of the wafer receiving area. 18 110638
TW097100956A 2008-01-10 2008-01-10 Leadframe-based semiconductor device and leadframe thereof TWI424547B (en)

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US5234866A (en) * 1985-03-25 1993-08-10 Hitachi, Ltd. Semiconductor device and process for producing the same, and lead frame used in said process
TWI245399B (en) * 2004-03-11 2005-12-11 Advanced Semiconductor Eng Leadframe with die pad

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