TWI420279B - Network ultra frequency control circuit - Google Patents

Description

Network overclocking control circuit

The present invention relates to a network overclocking control circuit.

CPU (Center processor unit) often needs to process a large amount of data when performing network games or other network operations. The traditional technology CPU uses the rated clock frequency. When the load increases, the computer execution performance will decrease. In order to make the computer program run smoothly, it is necessary to increase the operating frequency of the CPU, that is, the CPU frequency adjustment.

Conventional techniques usually have two ways to achieve the purpose of frequency adjustment. The first is to change the FSB. The FSB is the frequency at which the CPU communicates with the external peripheral circuit components of the CPU. If the FSB is changed, the frequency of communication between the CPU and the outside world can be changed. , that is, changing the speed of the bus. The second is to change the multiplier, the internal frequency is the internal working frequency of the CPU, and the internal frequency is the product of the FSB and the multiplier, so the CPU multiplier is changed, and the internal frequency can be changed accordingly, and the CPU can achieve the frequency adjustment. purpose.

At present, when the operating frequency of the CPU is adjusted by setting the jumper overclocking, the user needs to manually change the jumper to adjust the working frequency of the CPU. Before adjusting the working frequency, the user needs to refer to the manual for the frequency modulation, and the operation is cumbersome. And it is easy to cause errors, which causes unnecessary loss of related hardware circuits and reduces the service life.

In view of the above, it is necessary to provide a network overclocking control circuit that automatically adjusts the CPU frequency.

A network overclocking control circuit is applied to a computer, comprising an integrating circuit, a first comparing circuit, a second comparing circuit, a first switching circuit and a second switching circuit, and one of the computers works in a network The indicator signal pins are respectively connected to the input ends of the first comparison circuit and the second comparison circuit through the integration circuit, and the output end of the first comparison circuit is transmitted through the first switch circuit and the clock chip of the computer a clock control pin is connected, and an output end of the second comparison circuit is connected to a second clock control pin of the clock chip through the second switch circuit, and the integration circuit outputs the network operation indicator signal pin to the network The road state pulse signal is integrated and transmitted to the first and second comparison circuits. When the network is idle, the first and second comparison circuits respectively output a level signal to control the first and second switch circuits to output low power. Ping the clock chip, the clock chip controls the CPU in the computer not to overclock; when the network is lightly loaded, the first and second comparison circuits respectively output a level signal to control the first The second switch circuit respectively outputs a high level and a low level to the clock chip, and the clock chip controls the CPU in the computer to automatically perform a small amplitude overclocking; when the network is reloaded, the first and second comparison circuits respectively Outputting a level signal controls the first and second switching circuits to output a high level to the clock chip, and the clock chip controls the CPU in the computer to automatically perform a large overclocking.

Compared with the prior art, the network overclocking control circuit converts the signal outputted by the network working indicator signal pin into a constant voltage through the integrating circuit, and outputs a control signal after comparing with the voltage of the comparator circuit. At the input end of the switch circuit, the output signal of the switch circuit is supplied to a clock control pin of the clock chip of the computer to control whether the computer system is overclocked.

10‧‧‧Integral Circuit

20,30‧‧‧Comparative circuit

40,50‧‧‧Switch circuit

Vcc1~Vcc4‧‧‧voltage source

R1~R11‧‧‧ resistor

U1, U2‧‧‧ comparator

Q1, Q2‧‧‧ field effect transistor

Q10, Q20‧‧‧O crystal

C1‧‧‧ capacitor

1 is a circuit diagram of a preferred embodiment of a network overclocking control circuit of the present invention.

Referring to FIG. 1, the network overclocking control circuit of the present invention is applied to a computer (not shown). The preferred embodiment includes a first voltage source Vcc1, a second voltage source Vcc2, and a third voltage source Vcc3. a fourth voltage source Vcc4, a first comparator U1, a second comparator U2, a first field effect transistor Q1, a second field effect transistor Q2, a first transistor Q10, and a second The crystal Q20, a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a The eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11. The first and second field effect transistors are all N-channel field effect transistors, and the first and second transistors are both NPN type transistors.

The inverting input end of the first comparator U1 is grounded via the capacitor C1 and connected to the network working indicator signal pin LED_LAN_ACTJ of the computer via the first resistor R1 to receive a network state pulse signal of the computer, the first The voltage source Vcc1 is grounded through the second resistor R2 and the third resistor R3. The non-inverting input terminal of the first comparator U1 is connected to the node between the second resistor R2 and the third resistor R3, and the positive power terminal thereof Connecting the second voltage source Vcc2, the negative power terminal thereof is grounded, and the output end thereof is connected to the gate of the first field effect transistor Q1 via the sixth resistor R6, and the drain of the first field effect transistor Q1 is connected to the first a base of the transistor Q10 is connected to the third voltage source Vcc3 via the seventh resistor R7, a source thereof is connected to the emitter of the first transistor Q10 and grounded, and the collector of the first transistor Q10 is connected to the anode a first clock control pin TURB_CLK1 of the clock chip for controlling the CPU frequency of the computer and a fourth voltage source Vcc4 connected via the eighth resistor R8, wherein the inverting input terminal of the second comparator U2 is connected to the First comparator U1 The inverting input terminal, the first voltage source Vcc1 is grounded through the fourth resistor R4 and the fifth resistor R5, and the non-inverting input terminal of the second comparator U2 is connected to the fourth resistor R4 and the fifth resistor R5. The node between the positive power terminal is connected to the second voltage source Vcc2, the negative power terminal is grounded, and the output terminal is connected to the gate of the second field effect transistor Q2 via the ninth resistor R9, the second field effect electric The drain of the crystal Q2 is connected to the base of the second transistor Q20 and is connected to the third voltage source Vcc3 via the tenth resistor R10. The source of the second field effect transistor Q2 is connected to the second transistor Q20. The collector of the second transistor Q20 is connected to the second clock control pin TURBO_CLK2 of the clock chip and the fourth voltage source Vcc4 is connected via the eleventh resistor R11. In order to further save the cost, the sixth, seventh, eighth, ninth, tenth and eleventh resistors can be deleted, that is, the output end of the first comparator U1 and the first field effect transistor Q1 are directly directly connected. The gate of the first field effect transistor Q1 is directly connected to the third voltage source Vcc3, and the collector of the first transistor Q10 is directly connected to the fourth voltage source Vcc4, and the second comparator U2 is The output terminal is directly connected to the gate of the second field effect transistor Q2, the drain of the second field effect transistor Q2 is directly connected to the third voltage source Vcc3, and the collector of the second transistor Q20 is directly connected to the first Four voltage source Vcc4.

In this embodiment, the first resistor R1 and the capacitor C1 form an integrating circuit 10, and the network state pulse signal of the alternating network signal indicator LED_LAN_ACTJ output is converted into a constant voltage Vdc. The first voltage source Vcc1, the second voltage source Vcc2, the second resistor R2, the third resistor R3, and the first comparator U1 form a first comparison circuit 20. The first voltage source Vcc1, the second voltage source Vcc2, the fourth resistor R4, the fifth resistor R5, and the second comparator U2 form a second comparison circuit 30. The third voltage source Vcc3, the fourth voltage source Vcc4, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the first field effect transistor Q1 and the first transistor Q10 form a first A switching circuit 40. The third voltage source Vcc3, the fourth voltage source Vcc4, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the second field effect transistor Q2 and the second transistor Q20 form a second switch circuit 50. . The non-inverting input terminal of the first comparator U1 is divided by the second resistor R2 and the third resistor R3 to obtain a reference voltage Vref1, and the resistor value is changed by selecting the second resistor R2 and the third resistor R3. The reference voltage Vref1 is used, and the non-inverting input terminal of the second comparator U2 is divided by the fourth resistor R4 and the fifth resistor R5 to obtain a reference voltage Vref2, and the fourth resistor R4 and the fifth resistor are selected. The different resistance value of R5 changes the value of the reference voltage Vref2, and the value of the reference voltage Vref1 is greater than the value of the reference voltage Vref2.

When the network is in an idle state, the indicator signal pin LED_LAN_ACTJ always outputs a high level signal, the voltage of the inverting input terminal of the first comparator U1 is greater than the reference voltage Vref1 of the non-inverting input terminal, and the output end of the output terminal is low. Ping, the first field effect transistor Q1 is turned off, the first transistor Q10 is turned on, and the collector thereof is turned to a low level, and the first clock control pin TURBO_CLK1 of the clock chip receives a low level signal; The voltage of the inverting input terminal of the second comparator U2 is also greater than the reference voltage Vref2 of the non-inverting input terminal, the output terminal outputs a low level, the second field effect transistor Q2 is turned off, and the second transistor Q20 is turned on, and the set thereof When the pole is low, the second clock control pin TURBO_CLK2 of the clock chip also receives a low level signal. That is, when the first clock control pin TURBO_CLK1 and the second clock control pin TURBO_CLK2 of the clock chip receive the low level signal, the CPU in the computer is not overclocked.

When the network is in a light load state, the network indicator flashes slowly, the pulse signal width is large, and the voltage Vdc after the integration circuit 10 is lowered, and the voltage of the inverting input terminal of the first comparator U1 is smaller than The reference voltage Vref1 of the non-inverting input terminal The first output transistor Q1 is turned on, the first transistor Q10 is turned off, the first clock control pin TURBO_CLK1 of the clock chip receives a high level signal; and the second comparator U2 The voltage of the inverting input terminal is greater than the reference voltage Vref2 of the non-inverting input terminal, the output terminal outputs a low level, the second field effect transistor Q2 is turned off, the second transistor Q20 is turned on, and the collector thereof becomes a low level. The second clock control pin TURBO_CLK2 of the clock chip receives a low level signal. That is, when the first clock control pin TURBO_CLK1 of the clock chip is a high level signal and the second clock control pin TURBO_CLK2 is a low level signal, the CPU in the computer will automatically perform a small amplitude overclocking.

When the network is in a heavy load state, the network indicator flashes fast, the pulse signal width is small, and the voltage Vdc after the integration circuit 10 is small, and the voltage of the inverting input terminal of the first comparator U1 is smaller than The first phase effect transistor Q1 is turned on, the first transistor Q10 is turned off, and the first clock control pin TURBO_CLK1 of the clock chip receives a high voltage. At the same time, the voltage of the inverting input terminal of the second comparator U2 is also smaller than the reference voltage Vref2 of the non-inverting input terminal, and the output terminal outputs a high level, and the second field effect transistor Q2 is turned on, the second transistor When Q20 is turned off, the second clock control pin TURBO_CLK2 of the clock chip receives a high level signal. That is, when the first clock control pin TURBO_CLK1 and the second clock control pin TURBO_CLK2 of the clock chip are high level signals, the CPU in the computer will automatically perform a large overclocking.

The user can set the on/off function of the network overclocking control circuit in the BIOS interface. When the function is turned on, the frequency of the CPU is automatically adjusted according to the state of the network load of the system. The network overclocking control circuit is simple and low in cost.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. but The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

10‧‧‧Integral Circuit

20,30‧‧‧Comparative circuit

40,50‧‧‧Switch circuit

Vcc1~Vcc4‧‧‧voltage source

R1~R11‧‧‧ resistor

U1, U2‧‧‧ comparator

Q1, Q2‧‧‧ field effect transistor

Q10, Q20‧‧‧O crystal

C1‧‧‧ capacitor

Claims (10)

A network overclocking control circuit is applied to a computer, comprising an integrating circuit, a first comparing circuit, a second comparing circuit, a first switching circuit and a second switching circuit, and one of the computers works in a network The indicator signal pins are respectively connected to the input ends of the first comparison circuit and the second comparison circuit through the integration circuit, and the output end of the first comparison circuit is transmitted through the first switch circuit and the clock chip of the computer a clock control pin is connected, and an output end of the second comparison circuit is connected to a second clock control pin of the clock chip through the second switch circuit, and the integration circuit outputs the network operation indicator signal pin to the network The road state pulse signal is integrated and transmitted to the first and second comparison circuits. When the network is idle, the first and second comparison circuits respectively output a level signal to control the first and second switch circuits to output low power. Ping the clock chip, the clock chip controls the CPU in the computer not to overclock; when the network is lightly loaded, the first and second comparison circuits respectively output a level signal to control the first The second switch circuit respectively outputs a high level and a low level to the clock chip, and the clock chip controls the CPU in the computer to automatically perform a small amplitude overclocking; when the network is reloaded, the first and second comparison circuits respectively Outputting a level signal controls the first and second switching circuits to output a high level to the clock chip, and the clock chip controls the CPU in the computer to automatically perform a large overclocking. The network overclocking control circuit according to claim 1, wherein the integrating circuit comprises a first resistor and a capacitor, and the network working indicator signal pin is grounded through the first resistor and the capacitor in sequence, and The first resistor is coupled to the input terminals of the first and second comparison circuits. The network overclocking control circuit of claim 2, wherein the first comparison circuit comprises a first voltage source, a second voltage source, a second resistor, a third resistor, and a first comparator. The first voltage source is grounded through the second resistor and the third resistor, and the non-inverting input terminal of the first comparator is connected to a node between the second resistor and the third resistor, and the reverse phase is input. The input end is connected to the node between the first resistor and the capacitor, the positive voltage end is connected to the second voltage source, the negative voltage end is grounded, and the output end is connected to the first switch circuit. The network overclocking control circuit of claim 3, wherein the first switching circuit comprises a third voltage source, a fourth voltage source, a first field effect transistor and a first transistor, a gate of the first field effect transistor is connected to an output end of the first comparator, and a drain is respectively connected to the third voltage source and a base of the first transistor, and a source thereof is connected to the first transistor. The poles of the first transistor are respectively connected to the fourth voltage source and the first clock control pin of the clock chip. The network overclocking control circuit of claim 4, wherein a sixth resistor is further connected in series between the gate of the first field effect transistor and the output end of the first comparator, the first field A seventh resistor is further connected in series between the drain of the effect transistor and the third voltage source, and an eighth resistor is further connected in series between the collector of the first transistor and the fourth voltage source. The network overclocking control circuit according to claim 4, wherein the first field effect transistor is an N channel field effect transistor, and the first transistor is an NPN type transistor. The network overclocking control circuit of claim 2, wherein the second comparison circuit comprises a first voltage source, a second voltage source, a fourth resistor, a fifth resistor, and a second comparator. The first voltage source is grounded through the fourth resistor and the fifth resistor, and the non-inverting input terminal of the first comparator is connected to the node between the fourth resistor and the fifth resistor, and the inverting input terminal is connected The inverting input terminal of the first comparator has a positive voltage terminal connected to the second voltage source, a negative voltage terminal connected to the ground, and an output terminal connected to the second switch circuit. The network overclocking control circuit of the seventh aspect of the invention, wherein the second switching circuit comprises a third voltage source, a fourth voltage source, a second field effect transistor and a second transistor. a gate of the second field effect transistor is connected to the output end of the second comparator, and a drain is respectively connected to the third voltage source and a base of the second transistor, and a source thereof is connected to the second transistor Extremely grounded, the collectors of the second transistor are respectively connected to the fourth voltage source and the clock chip The second clock control pin. The network overclocking control circuit of claim 8, wherein a gate of the second field effect transistor and an output of the second comparator are further connected in series with a ninth resistor, the second field A tenth resistor is further connected in series between the drain of the effect transistor and the third voltage source, and an eleventh resistor is further connected in series between the collector of the second transistor and the fourth voltage source. The network overclocking control circuit according to claim 8, wherein the second field effect transistor is an N channel field effect transistor, and the second transistor is an NPN type transistor.