200928665 ' 九、發明說明： *【發明所屬之技術領域】 本發明係關於一種網路超頻控制電路。 【先前技術】 CPU ( Center processor unit，中央處理單元）在執 網路遊戲或其他網路操作時，往往需要處理大量之資料， 傳統技術使賴定之時鐘頻率，負載增切將造成電 月^執行效能下降，所以為使電腦程式㈣之執行，必須提 尚CPU之工作頻率，即CPU頻率調整。 習知技術通常有兩種方式來達到頻率調整之目的，第 一種為改變外頻’外頻是CPU》CPU外部週邊電路元件 通訊之頻率，如果改變外頻即可改變CPU與外界通訊之頻 率，亦即改變匯流排之速度。第二種為改變倍頻，内頻是 Y之内#工作頻率’而内頻是外頻與倍頻之乘積，因此 改變CPU之倍頻，進而内頻可隨之改變，cpu可達到 ❹調整之目的。 …目則在透過没置跳線超頻之方式來調整CPU之工作 頻率時，需要使用者以手動方式將跳線更動從而調整CPU ^作頻率，凋整工作頻率前使用者需要參考手冊說明才 I進仃_ ’操作繁璃且容易造成錯誤，而造成相關硬體 電路不必要之損耗，減少使用壽命。 【發明内容】 鑒於上述内容，有必要提供一種可自動調整CPU頻率 之網路超頻控制電路。 200928665 -.-種網路超頻控制電路’其應用於一電腦中，包括一 .積分電路、一第一比較電路、—第二比較電路、—第 關電路及-第二開關電路，該電腦之一網路工作指示^ 號引腳透過該積分電路分別與該第一比較電路及該第二 車交電路之輸入端相連，該第一比較電路之輸出端透㈣ 一開關電路與該電腦之-時鐘晶片之第—時鐘控制引腳相 連，該第二比較電路之輸出端透過該第二開關電路盘該時 鐘晶片之第二時鐘控制引腳相連，該積分電路將該網路工 作=示燈訊號引腳輸出之網路狀態脈衝訊號積分後傳送給 該第一及第二比較電路，當網路空閒時，該第一及第二^ 較電路分別輸出一電平訊號控制該第一與第二開關電路均 輸出低電平；當網路輕載時，該第一及第二比較電路分別 輸出一電平訊號控制該第一與第二開關電路分別輪出高電 平與低電平；當網路重載時，該第一及第二比較電路分別 輸出一電平訊號控制該第一及第二開關電路均輸出高電 ©平’該時鐘晶片根據接收到之電平情況控制超頻。 相較習知技術，該網路超頻控制電路透過該積分電路 將該網路工作指示燈訊號引腳輸出之訊號轉換為恒定之電 壓，並與該比較器電路之電壓比較後輸出一控制訊號給該 開關電路之輸入端，該開關電路之輸出訊號提供給該電腦 之時鐘晶片之時鐘控制引腳來控制該電腦系統是否超頻。 【實施方式】 請參考圖1，本發明網路超頻控制電路應用於—電腦 (未示出）中，其較佳實施方式包括一第一電壓源Vcci、 200928665 -一第二電壓源Vcc2、一第三電壓源Vcc3、一第四電壓源 .Vcc4、一第一比較器U1、一第二比較器U2、一第一場效 應電晶體Q1、一第二場效應電晶體Q2、一第一電晶體 Q10、一第二電晶體Q20、一電容C1、一第一電阻R1、一 第二電阻R2、一第三電阻R3、一第四電阻R4、一第五電 阻R5、一第六電阻R6、一第七電阻R7、一第八電阻R8、 一第九電阻R9、一第十電阻R10及一第十一電阻R11。該 第一及第二場效應電晶體均為N溝道場效應電晶體，第一 ®及第二電晶體均為NPN型電晶體。 該第一比較器U1之反相輸入端經該電容C1接地及經 該第一電阻R1連接該電腦之網路工作指示燈訊號引腳 LED一LAN—ACTJ，以接收電腦之網路狀態脈衝訊號，該第 一電壓源Vccl依次經該第二電阻R2及該第三電阻R3接 地，該第一比較器U1之同相輸入端連接於該第二電阻R2 與該第三電阻R3之間之節點，其正電源端連接該第二電 ❿壓源Vcc2，其負電源端接地，其輸出端經該第六電阻R6 連接該第一場效應電晶體Q1之閘極，該第一場效應電晶 體Q1之汲極連接該第一電晶體Q10之基極及經該第七電 阻R7連接該第三電壓源Vcc3，其源極連接該第一電晶體 Q10之射極並接地，該第一電晶體Q10之集極連接於該電 腦中之一用於控制該電腦CPU頻率之時鐘晶片之第一時 鐘控制引腳TURB—CLK1及經該第八電阻R8連接該第四 電壓源Vcc4，該第二比較器U2之反相輸入端連接該第一 比較器U1之反相輸入端，該第一電壓源Vccl依次經該第 200928665 四電阻R4及該第五電阻R5接地，該第二比較器U2之同 . 相輸入端連接於該第四電阻R4與該第五電阻R5之間之節 點，其正電源端連接該第二電壓源Vcc2，其負電源端接 地，其輸出端經該第九電阻R9連接該第二場效應電晶體 Q2之閘極，該第二場效應電晶體Q2之汲極連接該第二電 晶體Q20之基極及經該第十電阻R10連接該第三電壓源 Vcc3，該第二場效應電晶體Q2之源極連接該第二電晶體 Q20之射極並接地，該第二電晶體Q20之集極連接該時鐘 ® 晶片之第二時鐘控制引腳TURBO—CLK2及經該第十一電 阻R11連接該第四電壓源Vcc4。為進一步節省成本，該第 六、第七、第八、第九、第十及第十一電阻均可刪除，即 直接將該第一比較器U1之輸出端與該第一場效應電晶體 Q1之閘極相連，該第一場效應電晶體Q1之汲極直接連接 該第三電壓源Vcc3，該第一電晶體Q10之集極直接連接 該第四電壓源Vcc4，該第二比較器U2之輸出端直接與該 ❹第二場效應電晶體Q2之閘極相連，該第二場效應電晶體 Q2之汲極直接連接該第三電壓源Vcc3，該第二電晶體Q20 之集極直接連接該第四電壓源Vcc4。 本實施方式中，該第一電阻R1與該電容C1組成一積 分電路10,將該網路工作指示燈訊號引腳LED_LAN_ACTJ 輸出之交替變化之網路狀態脈衝訊號轉換成一恒定不變之 電壓Vdc。該第一電壓源Vccl、該第二電壓源Vcc2、該 第二電阻R2、該第三電阻R3及該第一比較器U1組成一 第一比較電路20。該第一電壓源Vccl、該第二電壓源 200928665 .‘ Vcc2、該第四電阻R4、該第五電阻R5及該第二比較器 .U2組成一第二比較電路30。該第三電壓源Vcc3、該第四 電壓源Vcc4、該第六電阻R6、該第七電阻R7、該第八電 阻R8、該第一場效應電晶體Q1及該第一電晶體Q10組成 一第一開關電路40。該第三電壓源Vcc3、該第四電壓源 Vcc4、該第九電阻R9、該第十電阻R10、該第十一電阻 R11、該弟二場效應電晶體Q2及該第二電晶體Q20組成一 第二開關電路50。該第一比較器U1之同相輸入端以該第 ❹二電阻R2及該第三電阻R3分壓來獲得一參考電壓 VreH，透過選擇該第二電阻R2及該第三電阻R3不同之 電阻值改變該參考電壓Vref 1之值，同時該第二比較器U2 之同相輸入端以該第四電阻R4及該第五電阻R5分壓來獲 得一參考電壓Vref2，透過選擇該第四電阻R4及該第五電 阻R5不同之電阻值改變該參考電壓Vref2之值，並使該參 考電壓Vref 1之值大於該參考電壓Vref2之值。 φ 當網路處於空閒狀態時，該指示燈訊號引腳 LED_LAN 一 ACTJ —直輸出高電平訊號，該第一比較器U1 之反相輸入端電壓大於其同相輸入端之參考電壓Vref 1， 其輸出端輸出低電平，該第一場效應電晶體Q1截止，該 第一電晶體Q10導通5其集極變為低電平，則該時鐘晶片 之第一時鐘控制引腳TURB0_CLK1接收一低電平訊號； 同時該第二比較器U2之反相輸入端電壓亦大於其同相輸 入端之參考電壓Vref2，其輸出端輸出低電平，該第二場 效應電晶體Q2截止，該第二電晶體Q20導通，其集極變 11 200928665 .為低電平，則該時鐘晶片之第二時鐘控制引腳 .TURBO一CLK2亦接收一低電平訊號。即該時鐘晶片之第一 時鐘控制引腳TURB0_CLK1及第二時鐘控制引腳 TURBO_CLK2均接收到低電平訊號時，此時該電腦中之 CPU不超頻。 當網路處於輕載狀態時，該網路指示燈閃爍之頻率 慢，其脈衝訊號寬度大，透過該積分電路10後之電壓Vdc 降低，該第一比較器U1之反相輸入端電壓小於其同相輸 ®入端之參考電壓Vref 1，其輸出端輸出高電平，該第一場 效應電晶體Q1導通，該第一電晶體Q10截止，該時鐘晶 片之第一時鐘控制引腳TURB0_CLK1接收一高電平訊 號；同時該第二比較器U2之反相輸入端電壓大於其同相 輸入端之參考電壓Vref2，其輸出端輸出低電平，該第二 場效應電晶體Q2截止，該第二電晶體Q20導通，其集極 變為低電平，該時鐘晶片之第二時鐘控制引腳 φ TURBO—CLK2接收一低電平訊號。即該時鐘晶片之第一時 鐘控制引腳TURB0_CLK1為高電平訊號而第二時鐘控制 引腳TURB0_CLK2為低電平訊號時，該電腦中之CPU將 自動進行小幅度之超頻。 當網路處於重載狀態時，該網路指示燈閃爍之頻率 快，其脈衝訊號寬度小，透過該積分電路10後之電壓Vdc 較小，該第一比較器U1之反相輸入端電壓小於其同相輸 入端之參考電壓VreH，其輸出端輸出高電平，該第一場 效應電晶體Q1導通，該第一電晶體Q10截止，該時鐘晶 12 200928665 ‘·.片之第一時鐘控制引腳TURB0_CLK1接收一高電平訊 , 號；同時該第二比較器U2之反相輸入端電壓亦小於其同 相輸入端之參考電壓Vref2，其輸出端輸出高電平，該第 二場效應電晶體Q2導通，該第二電晶體Q20截止，該時 鐘晶片之第二時鐘控制引腳TURBO_CLK2接收一高電平 訊號。即該時鐘晶片之第一時鐘控制引腳TURB0_CLK1 及第二時鐘控制引腳TURBO_CLK2均為高電平訊號時， 此時該電腦中之CPU將自動進行大幅度之超頻。 ® 用戶可在BIOS介面中設置該網路超頻控制電路之開 啟或關閉功能，當該功能開啟後，根據系統網路負載之輕 重狀態，自動調節CPU之頻率。該網路超頻控制電路簡 單、成本低。 綜上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之具體實施方式，舉 凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修 D飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1為本發明網路超頻控制電路之較佳實施方式之電 路圖。 【主要元件符號說明】 積分電路 10 比較電路 20，30 開關電路 40，50 電壓源 Vccl〜Vcc4 電阻 R1〜R11 比較器 Ul，U2 場效應電晶體Ql，Q2 電晶體 Q10, Q20 13 200928665200928665 ' IX. Description of the invention: * [Technical field to which the invention pertains] The present invention relates to a network overclocking control circuit. [Prior Art] CPU (Central Processing Unit) often needs to process a large amount of data when performing online games or other network operations. Traditional technology makes Lading's clock frequency and load increase will cause electricity to be executed. The performance is degraded, so in order to implement the computer program (4), it is necessary to increase the operating frequency of the CPU, that is, the CPU frequency adjustment. Conventional technology usually has two ways to achieve the purpose of frequency adjustment. The first one is to change the frequency of the external frequency circuit component of the CPU of the external frequency 'FSB is CPU'. If the FSB is changed, the frequency of communication between the CPU and the outside world can be changed. , that is, changing the speed of the bus. The second is to change the multiplier, the internal frequency is the working frequency of Y and the internal frequency is the product of the FSB and the multiplier, so the CPU multiplier is changed, and the internal frequency can be changed accordingly, and the cpu can be adjusted. The purpose. ... The purpose is to adjust the CPU's working frequency by overclocking without skipping. It is necessary for the user to manually change the jumper to adjust the CPU frequency. Before the operating frequency is cleared, the user needs to refer to the manual description.仃 _ 'Operational glass and easy to cause errors, resulting in unnecessary loss of related hardware circuits, reducing the service life. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a network overclocking control circuit that automatically adjusts the CPU frequency. 200928665 - A network overclocking control circuit is applied to a computer, comprising: an integrating circuit, a first comparing circuit, a second comparing circuit, a first closing circuit and a second switching circuit, the computer A network operation indicator pin is connected to the input end of the first comparison circuit and the second vehicle circuit through the integration circuit, and the output end of the first comparison circuit is transparent to (4) a switch circuit and the computer - The clock chip is connected to the clock control pin, and the output end of the second comparison circuit is connected to the second clock control pin of the clock chip through the second switch circuit board, and the integration circuit operates the network = indicator light The network state pulse signal of the pin output is integrated and transmitted to the first and second comparison circuits. When the network is idle, the first and second comparison circuits respectively output a level signal to control the first and second The switch circuit outputs a low level; when the network is lightly loaded, the first and second comparison circuits respectively output a level signal to control the first and second switch circuits to respectively emit a high level and a low level; Network weight When the first and the second comparator circuit outputs a signal for controlling the level of the first and second switching circuits are © outputs a high level 'of the clock control OC wafer according to the reception level. Compared with the prior art, the network overclocking control circuit converts the signal outputted by the network working indicator signal pin into a constant voltage through the integrating circuit, and outputs a control signal after comparing with the voltage of the comparator circuit. At the input end of the switch circuit, the output signal of the switch circuit is supplied to a clock control pin of the clock chip of the computer to control whether the computer system is overclocked. [Embodiment] Referring to FIG. 1, the network overclocking control circuit of the present invention is applied to a computer (not shown). The preferred embodiment includes a first voltage source Vcci, 200928665 - a second voltage source Vcc2. a third voltage source Vcc3, a fourth voltage source .Vcc4, a first comparator U1, a second comparator U2, a first field effect transistor Q1, a second field effect transistor Q2, a first power a crystal Q10, a second transistor Q20, a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, A seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11. The first and second field effect transistors are all N-channel field effect transistors, and the first and second transistors are both NPN type transistors. The inverting input end of the first comparator U1 is grounded via the capacitor C1 and connected to the network working indicator signal pin LED-LAN-ACTJ of the computer via the first resistor R1 to receive the network state pulse signal of the computer. The first voltage source Vccl is grounded through the second resistor R2 and the third resistor R3. The non-inverting input terminal of the first comparator U1 is connected to the node between the second resistor R2 and the third resistor R3. The positive power supply terminal is connected to the second electric voltage source Vcc2, the negative power supply terminal is grounded, and the output end thereof is connected to the gate of the first field effect transistor Q1 via the sixth resistor R6, the first field effect transistor Q1 The drain is connected to the base of the first transistor Q10 and connected to the third voltage source Vcc3 via the seventh resistor R7, and the source thereof is connected to the emitter of the first transistor Q10 and grounded, the first transistor Q10 The collector is connected to the first clock control pin TURB_CLK1 of the clock chip for controlling the CPU frequency of the computer, and the fourth voltage source Vcc4 is connected to the fourth voltage source V8 via the eighth resistor R8, the second comparator The inverting input of U2 is connected to the inverting input of the first comparator U1. The first voltage source Vccl is grounded through the fourth resistor R4 and the fifth resistor R5 in turn, and the phase input terminal of the second comparator U2 is connected between the fourth resistor R4 and the fifth resistor R5. a node, the positive power terminal is connected to the second voltage source Vcc2, the negative power terminal is grounded, and the output end thereof is connected to the gate of the second field effect transistor Q2 via the ninth resistor R9, the second field effect transistor The drain of Q2 is connected to the base of the second transistor Q20 and is connected to the third voltage source Vcc3 via the tenth resistor R10. The source of the second field effect transistor Q2 is connected to the emitter of the second transistor Q20. And grounded, the collector of the second transistor Q20 is connected to the second clock control pin TURBO_CLK2 of the clock® chip and the fourth voltage source Vcc4 is connected via the eleventh resistor R11. In order to further save the cost, the sixth, seventh, eighth, ninth, tenth and eleventh resistors can be deleted, that is, the output end of the first comparator U1 and the first field effect transistor Q1 are directly directly connected. The gate of the first field effect transistor Q1 is directly connected to the third voltage source Vcc3, and the collector of the first transistor Q10 is directly connected to the fourth voltage source Vcc4, and the second comparator U2 is The output terminal is directly connected to the gate of the second field effect transistor Q2, and the drain of the second field effect transistor Q2 is directly connected to the third voltage source Vcc3, and the collector of the second transistor Q20 is directly connected to the gate The fourth voltage source Vcc4. In this embodiment, the first resistor R1 and the capacitor C1 form an integration circuit 10, and the network state pulse signal of the alternately changed network output signal signal LED_LAN_ACTJ output is converted into a constant voltage Vdc. The first voltage source Vccl, the second voltage source Vcc2, the second resistor R2, the third resistor R3, and the first comparator U1 form a first comparison circuit 20. The first voltage source Vccl, the second voltage source 200928665. The Vcc2, the fourth resistor R4, the fifth resistor R5 and the second comparator .U2 form a second comparison circuit 30. The third voltage source Vcc3, the fourth voltage source Vcc4, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the first field effect transistor Q1 and the first transistor Q10 form a first A switching circuit 40. The third voltage source Vcc3, the fourth voltage source Vcc4, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the second field effect transistor Q2 and the second transistor Q20 form a The second switching circuit 50. The non-inverting input terminal of the first comparator U1 is divided by the second resistor R2 and the third resistor R3 to obtain a reference voltage VreH, and the resistance value is changed by selecting the second resistor R2 and the third resistor R3. The reference voltage Vref 1 is at the same time, and the non-inverting input terminal of the second comparator U2 is divided by the fourth resistor R4 and the fifth resistor R5 to obtain a reference voltage Vref2, and the fourth resistor R4 and the first The different resistance values of the five resistors R5 change the value of the reference voltage Vref2, and the value of the reference voltage Vref 1 is greater than the value of the reference voltage Vref2. φ When the network is in an idle state, the indicator signal pin LED_LAN_ACTJ directly outputs a high level signal, and the voltage of the inverting input terminal of the first comparator U1 is greater than the reference voltage Vref1 of the non-inverting input terminal thereof. The output terminal outputs a low level, the first field effect transistor Q1 is turned off, the first transistor Q10 is turned on 5 and its collector becomes a low level, and the first clock control pin TURB0_CLK1 of the clock chip receives a low power. At the same time, the voltage of the inverting input terminal of the second comparator U2 is also greater than the reference voltage Vref2 of the non-inverting input terminal, the output terminal outputs a low level, and the second field effect transistor Q2 is turned off, the second transistor Q20 is turned on, and its collector is changed to 11200928665. When the level is low, the second clock control pin of the clock chip, TURBO_CLK2, also receives a low level signal. That is, when the first clock control pin TURB0_CLK1 and the second clock control pin TURBO_CLK2 of the clock chip receive the low level signal, the CPU in the computer is not overclocked. When the network is in a light load state, the network indicator flashes slowly, the pulse signal width is large, and the voltage Vdc after the integration circuit 10 is lowered, and the voltage of the inverting input terminal of the first comparator U1 is smaller than The reference voltage Vref1 of the in-phase input terminal is outputted to a high level, the first field effect transistor Q1 is turned on, the first transistor Q10 is turned off, and the first clock control pin TURB0_CLK1 of the clock chip receives one a high level signal; at the same time, the voltage of the inverting input terminal of the second comparator U2 is greater than the reference voltage Vref2 of the non-inverting input terminal, the output terminal outputs a low level, and the second field effect transistor Q2 is turned off, the second electric The crystal Q20 is turned on, and its collector becomes low. The second clock control pin φ TURBO_CLK2 of the clock chip receives a low level signal. That is, when the first clock control pin TURB0_CLK1 of the clock chip is a high level signal and the second clock control pin TURB0_CLK2 is a low level signal, the CPU in the computer will automatically perform a small amplitude overclocking. When the network is in a heavy load state, the network indicator flashes fast, the pulse signal width is small, and the voltage Vdc after the integration circuit 10 is small, and the voltage of the inverting input terminal of the first comparator U1 is smaller than The reference voltage VreH of the non-inverting input terminal thereof outputs a high level at the output end, the first field effect transistor Q1 is turned on, the first transistor Q10 is turned off, and the clock crystal 12 200928665 '·. The pin TURB0_CLK1 receives a high level signal, and the voltage of the inverting input terminal of the second comparator U2 is also smaller than the reference voltage Vref2 of the non-inverting input terminal, and the output terminal outputs a high level, the second field effect transistor Q2 is turned on, the second transistor Q20 is turned off, and the second clock control pin TURBO_CLK2 of the clock chip receives a high level signal. That is, when the first clock control pin TURB0_CLK1 and the second clock control pin TURBO_CLK2 of the clock chip are high level signals, the CPU in the computer will automatically perform a large overclocking. The user can set the on/off function of the network overclocking control circuit in the BIOS interface. When this function is enabled, the CPU frequency is automatically adjusted according to the weight of the system network load. The network overclocking control circuit is simple and low in cost. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only for the specific embodiments of the present invention, and those skilled in the art that are skilled in the art will be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a preferred embodiment of a network overclocking control circuit of the present invention. [Main component symbol description] Integral circuit 10 Comparison circuit 20, 30 Switch circuit 40, 50 Voltage source Vccl~Vcc4 Resistor R1~R11 Comparator Ul, U2 Field effect transistor Ql, Q2 transistor Q10, Q20 13 200928665