TWI599179B - Electronic device and input voltage compensation method - Google Patents
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本案是關於一種電子裝置,特別是關於一種具有輸入電壓補償功能的電子裝置及輸入電壓補償方法。 The present invention relates to an electronic device, and more particularly to an electronic device having an input voltage compensation function and an input voltage compensation method.
當電子裝置配置於電路基板(如PCB板)時,電子裝置的一電路接腳耦接於電壓調節器的輸出端,以接收電壓調節器所提供的輸出電壓。對於以積體電路(integrated circuit,IC)製成的電子裝置而言,當系統啟動時,電子裝置的電路接腳接收電壓調節器提供的輸出電壓。然而,在傳統實作中,電壓調節器的輸出端耦接於自身的回授端,藉以調節輸出電壓。因此,電路基板上的走線路徑及電子裝置內部打線接合(wire bonding)產生的寄生阻抗將導致電壓衰退(IR drop)之現象,容易造成電子裝置內部接收的電源電壓遠低於電壓調節器的輸出電壓,使得電子裝置無法正常工作。 When the electronic device is disposed on a circuit board (such as a PCB), a circuit pin of the electronic device is coupled to the output end of the voltage regulator to receive the output voltage provided by the voltage regulator. For an electronic device made of an integrated circuit (IC), when the system is started, the circuit pin of the electronic device receives the output voltage provided by the voltage regulator. However, in conventional implementations, the output of the voltage regulator is coupled to its feedback terminal to regulate the output voltage. Therefore, the trace path on the circuit substrate and the parasitic impedance generated by the internal wire bonding of the electronic device will cause an IR drop phenomenon, which is likely to cause the power supply voltage received inside the electronic device to be much lower than that of the voltage regulator. The output voltage makes the electronic device not working properly.
因此,為確保電子裝置(IC)的正常工作,往往會提高電壓調節器所提供的輸出電壓,藉以抵銷電壓衰退的影響。但在電子裝置操作於低效能模式的情況下,過高的電源電壓會造成額外的靜態功耗損失。有鑑於此,如何有效抵銷電壓衰退的影響,並且降低電子裝置於低效能模式下的靜態功耗損失,確為所屬領域亟需解決之問題。 Therefore, in order to ensure the normal operation of the electronic device (IC), the output voltage provided by the voltage regulator is often increased, thereby offsetting the influence of voltage decay. However, in the case of an electronic device operating in a low-performance mode, excessive power supply voltage can cause additional static power loss. In view of this, how to effectively offset the influence of voltage decay and reduce the static power loss of the electronic device in the low-efficiency mode is an urgent problem to be solved in the field.
本案提供一種電子裝置,所述電子裝置包括第一電路接腳、第二電路接腳及處理電路。第一電路接腳耦接於電壓調節器的輸出端,並用以接收電壓調節器的輸出端所提供的第一電源電壓,使得第一電路接腳具有第二電源電壓。第二電路接腳耦接於電壓調節器的回授端。處理電路耦接於第一電路接腳及第二電路接腳,並用以根據第一電路接腳的第二電源電壓產生回授電壓於第二電路接腳,使得電壓調節器依據回授電壓來調節第一電源電壓。 The present invention provides an electronic device including a first circuit pin, a second circuit pin, and a processing circuit. The first circuit pin is coupled to the output of the voltage regulator and is configured to receive the first power voltage provided by the output of the voltage regulator such that the first circuit pin has a second power voltage. The second circuit pin is coupled to the feedback end of the voltage regulator. The processing circuit is coupled to the first circuit pin and the second circuit pin, and configured to generate a feedback voltage to the second circuit pin according to the second power voltage of the first circuit pin, so that the voltage regulator is based on the feedback voltage Adjust the first supply voltage.
本案另提供一種電子裝置,所述電子裝置包括具有輸出端及回授端的電壓調節器,以及具有第一連接墊、第二連接墊及處理電路的內部電路。其中,第一連接墊耦接於電壓調節器的輸出端,並用以接收電壓調節器的輸出端提供的第一電源電壓,使得第一連接墊具有第二電源電壓。第二連接墊耦接於電壓調節器的回授端。處理電路則耦接於第一連接墊及第二連接墊,並用以根據第一連接墊的第二電源電壓產生一回授電壓於第二連接墊,使得電壓調節器依據回授電壓來調節第一電源電壓。 The present invention further provides an electronic device including a voltage regulator having an output end and a feedback end, and an internal circuit having a first connection pad, a second connection pad, and a processing circuit. The first connection pad is coupled to the output end of the voltage regulator and configured to receive the first power supply voltage provided by the output of the voltage regulator such that the first connection pad has a second power supply voltage. The second connection pad is coupled to the feedback end of the voltage regulator. The processing circuit is coupled to the first connection pad and the second connection pad, and configured to generate a feedback voltage to the second connection pad according to the second power supply voltage of the first connection pad, so that the voltage regulator adjusts according to the feedback voltage A power supply voltage.
本案另提供一種輸入電壓補償方法,執行於電子裝置中。所述電子裝置包括第一電路接腳、第二電路接腳及處理電路,其中第一電路接腳耦接於處理電路與一電壓調節器的輸出端,且第二電路接腳耦接於處理電路與此電壓調節器的回授端。所述輸入電壓補償方法包括以下步驟。首先,利用第一電路接腳,接收自於電壓調節器的輸出端所提供的第一電源電壓,使得第一電路接腳具有一第二電源電壓。接著,利用處理電路,根據第一電路接腳的第二電源電壓以產生一回授電壓於第二電路接腳,並使得電壓調節器依據回授電壓來調節第一電源電壓。 The present invention further provides an input voltage compensation method, which is implemented in an electronic device. The electronic device includes a first circuit pin, a second circuit pin, and a processing circuit, wherein the first circuit pin is coupled to the processing circuit and an output of the voltage regulator, and the second circuit pin is coupled to the processing The circuit and the feedback terminal of this voltage regulator. The input voltage compensation method includes the following steps. First, the first power supply voltage is received from the output of the voltage regulator by using the first circuit pin such that the first circuit pin has a second power supply voltage. Then, the processing circuit is used to generate a feedback voltage to the second circuit pin according to the second power voltage of the first circuit pin, and cause the voltage regulator to adjust the first power voltage according to the feedback voltage.
綜上所述,本案所提供的電子裝置及輸入電壓補償方法,可藉由額外增設於同一晶片的電路接腳來耦接至電壓調節器的回授端,藉以抵銷電壓衰退之影響,並且降低電子裝置於低效能模式 下的功耗損失。 In summary, the electronic device and the input voltage compensation method provided by the present invention can be coupled to the feedback terminal of the voltage regulator by additionally adding circuit pins on the same chip, thereby offsetting the influence of voltage decay, and Reduce the electronic device in low performance mode Loss of power consumption.
1、1’‧‧‧電子裝置 1, 1'‧‧‧ electronic devices
110、120‧‧‧電路接腳 110, 120‧‧‧ circuit pins
130‧‧‧處理電路 130‧‧‧Processing Circuit
20、20’‧‧‧電壓調節器 20, 20'‧‧‧Voltage regulator
210‧‧‧輸出端 210‧‧‧ Output
220‧‧‧回授端 220‧‧‧reporting end
VDD1、VDD2‧‧‧電源電壓 VDD1, VDD2‧‧‧ power supply voltage
VF‧‧‧回授電壓 VF‧‧‧ feedback voltage
Z1、Z2、Z3‧‧‧寄生阻抗 Z1, Z2, Z3‧‧‧ parasitic impedance
R1、R2、R3、R4、Ra_1~Ra_N、Rb_1~Rb_M‧‧‧電阻 R1, R2, R3, R4, Ra_1~Ra_N, Rb_1~Rb_M‧‧‧ resistance
C1、C2、C3、C4‧‧‧電容 C1, C2, C3, C4‧‧‧ capacitors
L1、L2、L4‧‧‧電感 L1, L2, L4‧‧‧ inductance
I1‧‧‧負載電流 I1‧‧‧Load current
GND‧‧‧接地電壓 GND‧‧‧ Grounding voltage
10‧‧‧內部電路 10‧‧‧Internal circuits
110’、120’‧‧‧連接墊 110’, 120’‧‧‧ connection pads
131‧‧‧處理器 131‧‧‧ processor
133‧‧‧補償電路 133‧‧‧Compensation circuit
TS‧‧‧控制信號 TS‧‧‧ control signal
TS1、TS2‧‧‧開關控制信號 TS1, TS2‧‧‧ switch control signals
1331、1333‧‧‧電阻陣列 1331, 1333‧‧‧ resistance array
SW1_1~SW1_N、SW2_1~SW2_M‧‧‧開關電路 SW1_1~SW1_N, SW2_1~SW2_M‧‧‧ Switching Circuit
S501~S503‧‧‧流程步驟 S501~S503‧‧‧ Process steps
圖1是本案一實施例所提供的電子裝置之電路示意圖。 1 is a circuit diagram of an electronic device according to an embodiment of the present disclosure.
圖2是本案另一實施例所提供的電子裝置之電路示意圖。 FIG. 2 is a schematic circuit diagram of an electronic device according to another embodiment of the present disclosure.
圖3是本案一實施例所提供的電子裝置中的處理電路之示意圖。 FIG. 3 is a schematic diagram of a processing circuit in an electronic device according to an embodiment of the present disclosure.
圖4是圖3之處理電路中的補償電路之電路示意圖。 4 is a circuit diagram of a compensation circuit in the processing circuit of FIG.
圖5是本案一實施例所提供的輸入電壓補償方法之流程圖。 FIG. 5 is a flow chart of an input voltage compensation method according to an embodiment of the present disclosure.
在下文中,將藉由圖式說明本案之各種實施例來描述本發明。然而,本發明概念可能以許多不同形式來體現,且不應解釋為限於本文中所闡述之例示性實施例。此外,在圖式中相同的參考數字可表示相同或類似的元件。 In the following, the invention will be described by way of illustration of various embodiments of the invention. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. In addition, the same reference numerals may be used in the drawings.
參閱圖1,圖1是本案一實施例所提供的電子裝置之電路示意圖。電子裝置1包括電路接腳110、電路接腳120以及處理電路130。在本實施例中,電子裝置1可例如由一積體電路(IC)所製成。在一些實施例中,圖1的電子裝置1可視為一系統單晶片(System on Chip,SoC)。 Referring to FIG. 1, FIG. 1 is a schematic circuit diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1 includes a circuit pin 110, a circuit pin 120, and a processing circuit 130. In the present embodiment, the electronic device 1 can be made, for example, by an integrated circuit (IC). In some embodiments, the electronic device 1 of FIG. 1 can be regarded as a system on chip (SoC).
電路接腳110耦接於電壓調節器20的輸出端210,並用以接收電壓調節器20的輸出端210所提供的電源電壓VDD1,使得電路接腳110具有電源電壓VDD2。電路接腳120則耦接於電壓調節器20的回授端220。 The circuit pin 110 is coupled to the output 210 of the voltage regulator 20 and is configured to receive the power supply voltage VDD1 provided by the output 210 of the voltage regulator 20 such that the circuit pin 110 has a power supply voltage VDD2. The circuit pin 120 is coupled to the feedback terminal 220 of the voltage regulator 20 .
處理電路130耦接電路接腳110、120,並用以根據電路接腳110的電源電壓VDD2產生回授電壓VF於電路接腳120,使得電壓調節器20可依據回授電壓VF來調節電源電壓VDD1。 The processing circuit 130 is coupled to the circuit pins 110 and 120 and configured to generate the feedback voltage VF according to the power supply voltage VDD2 of the circuit pin 110 to the circuit pin 120, so that the voltage regulator 20 can adjust the power supply voltage VDD1 according to the feedback voltage VF. .
在本實施例中,電壓調節器20係設置在電子裝置1之外的晶 片基板上。在一些實施例中,電壓調節器20為開關穩壓器(switch regulator)。在一些實施例中,電壓調節器20可由純硬體電路來實現,或由硬體電路搭配韌體或軟體來實現。另外,由於電壓調節器20的原理為本技術領域中具有通常知識者所習知,因此有關於電壓調節器20的細部內容於此便不多加贅述。 In the present embodiment, the voltage regulator 20 is a crystal disposed outside the electronic device 1. On the substrate. In some embodiments, voltage regulator 20 is a switch regulator. In some embodiments, the voltage regulator 20 can be implemented as a purely hardware circuit or as a hardware circuit with a firmware or software. In addition, since the principle of the voltage regulator 20 is well known to those of ordinary skill in the art, the details of the voltage regulator 20 will not be described herein.
更進一步來說,由於電子裝置1的電路接腳110容易受到電子裝置1與電壓調節器20間的路徑(即PCB路徑)及電子裝置1(IC)內部打線接合分別產生之寄生阻抗Z1、Z2的影響,因此電路接腳110的電源電壓VDD2並不完全會等於為電壓調節器20所提供的第一電源電壓VDD1。舉例來說,於圖1的實施例中,假設PCB路徑的等效電路可由電阻R1、電感L1及電容C1所組成,IC內部打線接合的等效電路則可由電阻R2、電感L2及電容C2所組成,而圖1中的寄生阻抗Z1、Z2可表示成:ZPCB=RPCB+LPCB (1) Furthermore, since the circuit pin 110 of the electronic device 1 is easily exposed by the path between the electronic device 1 and the voltage regulator 20 (ie, the PCB path) and the internal wiring of the electronic device 1 (IC), the parasitic impedances Z1 and Z2 are respectively generated. The effect, therefore, the supply voltage VDD2 of the circuit pin 110 is not exactly equal to the first supply voltage VDD1 provided for the voltage regulator 20. For example, in the embodiment of FIG. 1, it is assumed that the equivalent circuit of the PCB path can be composed of the resistor R1, the inductor L1, and the capacitor C1, and the equivalent circuit of the internal wire bonding of the IC can be performed by the resistor R2, the inductor L2, and the capacitor C2. Composition, and the parasitic impedances Z1 and Z2 in Figure 1 can be expressed as: Z PCB = R PCB + L PCB (1)
ZWB=RWB+LWB (2) Z WB =R WB +L WB (2)
其中,ZPCB、ZWB分別為寄生阻抗Z1的阻抗值,RPCB、RWB分別為電阻R1、R2的阻抗值,LPCB、LWB分別為電感L1、L2的阻抗值。而第一電路接腳110上的第二電源電壓VDD2則可表示成:Vin=Vout-I*(ZPCB+ZWB) (3) Among them, Z PCB and Z WB are the impedance values of the parasitic impedance Z1, R PCB and R WB are the impedance values of the resistors R1 and R2, respectively, and L PCB and L WB are the impedance values of the inductors L1 and L2, respectively. The second power voltage VDD2 on the first circuit pin 110 can be expressed as: Vin=Vout-I*(Z PCB +Z WB ) (3)
其中,Vin表示為電源電壓VDD2的值,Vout表示為電源電壓VDD1的值,I則表示為負載電流I1的值。顯然地,對於傳統實作方式(亦即電壓調節器20的輸出端210耦接於回授端220)而言,電壓調節器20得到的回授電壓並不能反應實際輸入電子裝置1內部的電源電壓(即電源電壓VDD2),即電壓調節器20參考到不準 確的回授電壓,進而調節出不理想的輸出電壓(即電源電壓VDD1)。 Here, Vin is the value of the power supply voltage VDD2, Vout is the value of the power supply voltage VDD1, and I is the value of the load current I1. Obviously, for the conventional implementation (that is, the output 210 of the voltage regulator 20 is coupled to the feedback terminal 220), the feedback voltage obtained by the voltage regulator 20 does not reflect the power input to the actual input device 1. Voltage (ie, power supply voltage VDD2), that is, voltage regulator 20 is referenced The feedback voltage is confirmed, and the undesired output voltage (ie, the power supply voltage VDD1) is adjusted.
有鑑於此,電子裝置1經由額外增設於同一晶片基板的電路接腳120來耦接至電壓調節器20的回授端220,使得電壓調節器20能獲取對應於實際輸入電子裝置1內部之電源電壓VDD2的回授電壓VF,以作為電壓調節器20的回授電壓,進而使得電壓調節器20能據以調節出理想的輸出電壓(即電源電壓VDD1)。 In view of this, the electronic device 1 is coupled to the feedback terminal 220 of the voltage regulator 20 via a circuit pin 120 additionally added to the same wafer substrate, so that the voltage regulator 20 can obtain a power source corresponding to the internal of the actual input electronic device 1. The feedback voltage VF of the voltage VDD2 serves as the feedback voltage of the voltage regulator 20, thereby enabling the voltage regulator 20 to adjust the desired output voltage (ie, the power supply voltage VDD1).
為進一步說明如何使電路接腳120上的回授電壓VF能趨近於實際輸入電子裝置1內部的電源電壓VDD2,本案提出了一種實施方式,復參閱圖1,電子裝置1更可包括電阻R3及電容C3。其中,電阻R3的第一端耦接於第一電路接腳110,電阻R3的第二端耦接於處理電路130,電容C3的第一端耦接於電阻R3的第二端,電容C3的第二端則耦接於接地電壓GND。 To further illustrate how the feedback voltage VF on the circuit pin 120 can be brought close to the power supply voltage VDD2 inside the actual input electronic device 1, an embodiment is proposed in the present invention. Referring to FIG. 1, the electronic device 1 may further include a resistor R3. And capacitor C3. The first end of the resistor R3 is coupled to the first circuit pin 110, the second end of the resistor R3 is coupled to the processing circuit 130, and the first end of the capacitor C3 is coupled to the second end of the resistor R3, and the capacitor C3 The second end is coupled to the ground voltage GND.
值得注意的是,於其他實施方式中,電容C3也可例如為一極性電容。因此,電容C3的正向端耦接於電阻R3的第二端,且電容C3的負向端則耦接於接地電壓GND。 It should be noted that in other embodiments, the capacitor C3 can also be, for example, a polar capacitor. Therefore, the forward end of the capacitor C3 is coupled to the second end of the resistor R3, and the negative end of the capacitor C3 is coupled to the ground voltage GND.
再者,若先不將處理電路130所運行的技術特徵給考量進去。也就是說,當處理電路130僅視為將電阻R3的第二端耦接至第二電路接腳120的情況下,電路接腳120上的回授電壓VF可表示成:
其中,Vin2則表示為回授電壓VF的值。因此,應當理解的是,本案實施例所提供的電子裝置1的技術手段與傳統實作中的技術手段完全不同。除此之外,不論是在電子裝置1操作於高效能模式或低效能模式的情況下,當負載電流I1增加所導致電壓衰退的影響遽增時,電壓調節器20仍可得到對應於實際輸入IC內部之電源電壓VDD2的回授電壓VF,使得電壓調節器20能據以調節 出理想的第一電源電壓VDD1。 Among them, Vin2 is expressed as the value of the feedback voltage VF. Therefore, it should be understood that the technical means of the electronic device 1 provided by the embodiment of the present invention is completely different from the technical means in the conventional implementation. In addition, the voltage regulator 20 can still obtain the actual input corresponding to the actual input when the influence of the voltage decay caused by the increase of the load current I1 increases, whether the electronic device 1 operates in the high-performance mode or the low-performance mode. The feedback voltage VF of the power supply voltage VDD2 inside the IC enables the voltage regulator 20 to adjust An ideal first supply voltage VDD1 is produced.
如此一來,電子裝置1不僅可抵銷PCB路徑及電子裝置1內部打線接合所造成的電壓衰退之影響,還可使實際輸入電子裝置1內部的電源電壓不會隨著負載電流I1的變化而改變。有鑑於此,當在操作於高效能模式的情況下,電子裝置1仍能得到穩定的電源電壓,並在操作於低效能模式的情況下,電子裝置1還能降低靜態功耗損失。 In this way, the electronic device 1 not only offsets the influence of the voltage decay caused by the PCB path and the internal wire bonding of the electronic device 1, but also causes the power supply voltage inside the actual input electronic device 1 to not change with the load current I1. change. In view of this, when operating in the high-performance mode, the electronic device 1 can still obtain a stable power supply voltage, and in the case of operating in the low-performance mode, the electronic device 1 can also reduce the static power consumption loss.
另一方面,於其他實施方式中,圖1中的電壓調節器20也可以是同樣地設置在電子裝置1之內部的同一晶片基板上。換言之,電路接腳110、電路接腳120、處理電路130及電壓調節器20也可設置於同一晶片基板上,參閱圖2,圖2是本案另一實施例所提供的電子裝置之電路示意圖。 On the other hand, in other embodiments, the voltage regulator 20 of FIG. 1 may be similarly disposed on the same wafer substrate inside the electronic device 1. In other words, the circuit pin 110, the circuit pin 120, the processing circuit 130, and the voltage regulator 20 can also be disposed on the same wafer substrate. Referring to FIG. 2, FIG. 2 is a schematic circuit diagram of an electronic device according to another embodiment of the present disclosure.
相較於圖1的電子裝置1,圖2的電子裝置1’主要包括內部電路10及電壓調節器20’。其中,電壓調節器20’同樣包含有輸出端210及回授端220,而內部電路10則包含連接墊110’、連接墊120’及處理電路130。 Compared to the electronic device 1 of Fig. 1, the electronic device 1' of Fig. 2 mainly includes an internal circuit 10 and a voltage regulator 20'. The voltage regulator 20' also includes an output terminal 210 and a feedback terminal 220, and the internal circuit 10 includes a connection pad 110', a connection pad 120', and a processing circuit 130.
其中,圖2的連接墊110’類似於圖1的電路接腳110,圖2的連接墊120’則類似於圖1的電路接腳120。因此,連接墊110’耦接於電壓調節器20’的輸出端210,並用以接收電源電壓VDD1,使得連接墊110’具有電源電壓VDD2。連接墊120’則耦接於電壓調節器20’的回授端220。 Wherein, the connection pad 110' of FIG. 2 is similar to the circuit pin 110 of FIG. 1, and the connection pad 120' of FIG. 2 is similar to the circuit pin 120 of FIG. Therefore, the connection pad 110' is coupled to the output terminal 210 of the voltage regulator 20' and is configured to receive the power supply voltage VDD1 such that the connection pad 110' has the power supply voltage VDD2. The connection pad 120' is coupled to the feedback terminal 220 of the voltage regulator 20'.
處理電路130耦接於連接墊110’與連接墊120’,並用以根據電源電壓VDD2產生回授電壓VF於連接墊120’,使得電壓調節器20’依據回授電壓VF來調節電源電壓VDD1。 The processing circuit 130 is coupled to the connection pad 110' and the connection pad 120', and is configured to generate a feedback voltage VF to the connection pad 120' according to the power supply voltage VDD2, so that the voltage regulator 20' adjusts the power supply voltage VDD1 according to the feedback voltage VF.
另外,由於連接墊110’、120’、處理電路130及電壓調節器20’設置於同一晶片基板上,因此於圖2的實施例中,電子裝置1’將會受到有IC晶片上走線所產生的寄生阻抗Z3之影響。於是,連接墊110’上的電源電壓VDD2可表示成。 In addition, since the connection pads 110', 120', the processing circuit 130, and the voltage regulator 20' are disposed on the same wafer substrate, in the embodiment of FIG. 2, the electronic device 1' will be subjected to the wiring on the IC chip. The effect of the generated parasitic impedance Z3. Thus, the power supply voltage VDD2 on the connection pad 110' can be represented.
Vin=Vout-I*ZWB' (5) Vin=Vout-I*Z WB ' (5)
其中,ZWB'表示為寄生阻抗Z3的阻抗值。另一方面,對於以降低靜態功耗損失為目的的習知技藝而言,動態調整電壓與頻率(dynamic voltage frequency scaling,DVFS)是近年來廣泛應用的技術手段。簡單來說,DVFS可以在當IC內部的處理器偵測到IC操作於低效能模式時,將輸入IC內部的電源電壓調整至低電壓準位,以達到節能之效果。因此,DVFS的主要實現方式是使IC內部的處理器可透過一通訊協定介面來與電壓調節器進行通訊,使得電壓調節器調節出符合IC所期望的輸出電壓。而上述作法成本較高,還會使得IC電路上的設計更為複雜。 Where Z WB ' is expressed as the impedance value of the parasitic impedance Z3. On the other hand, for the prior art for the purpose of reducing static power loss, dynamic voltage frequency scaling (DVFS) is a widely used technical means in recent years. To put it simply, DVFS can adjust the power supply voltage inside the input IC to a low voltage level when the IC inside the IC detects that the IC is operating in low-efficiency mode to achieve energy saving. Therefore, the main implementation of DVFS is to enable the internal processor of the IC to communicate with the voltage regulator through a communication protocol interface, so that the voltage regulator adjusts the output voltage that is expected by the IC. The high cost of the above method will also make the design on the IC circuit more complicated.
為解決上述問題,本案進一步提供一種實施方式。參閱圖3,圖3是本案實施例所提供的電子裝置中的處理電路之示意圖,處理電路130可執行於圖1的電子裝置1或圖2的電子裝置1’中,但本案並不以此為限。為方便說明,本實施例的處理電路130將採用以執行於電子裝置1的例子來說明,因此,一併參閱圖1以利理解。另外,圖3中部分與圖1相同之元件以相同之圖號標示,故於此不再多加贅述。 In order to solve the above problems, the present invention further provides an implementation manner. Referring to FIG. 3, FIG. 3 is a schematic diagram of a processing circuit in an electronic device according to an embodiment of the present disclosure. The processing circuit 130 can be implemented in the electronic device 1 of FIG. 1 or the electronic device 1' of FIG. 2, but the present invention does not Limited. For convenience of explanation, the processing circuit 130 of the present embodiment will be described with an example for execution on the electronic device 1. Therefore, reference is made to FIG. 1 for easy understanding. In addition, the components in FIG. 3 that are the same as those in FIG. 1 are denoted by the same reference numerals, and thus will not be further described herein.
處理電路130包括處理器131及補償電路133。處理器131可例如為IC內部的中央處理器或一般處理器。另外,補償電路133耦接於電路接腳110、處理器131及電路接腳120,補償電路133用以依據電路接腳110上的電源電壓VDD2以及處理器131所輸出的控制信號TS,來產生出回授電壓VF於第二電路接腳120。 The processing circuit 130 includes a processor 131 and a compensation circuit 133. The processor 131 can be, for example, a central processor or a general processor internal to the IC. In addition, the compensation circuit 133 is coupled to the circuit pin 110, the processor 131, and the circuit pin 120. The compensation circuit 133 is configured to generate the voltage according to the power supply voltage VDD2 on the circuit pin 110 and the control signal TS outputted by the processor 131. The feedback voltage VF is outputted to the second circuit pin 120.
因此,本案實施例的電子裝置1將採用完全相異於DVFS的技術手段,而是由處理器131控制相互耦接的電壓調節器20來調節出輸出電壓(即電源電壓VDD1),此技術手段不僅降低開發成本,還能夠使得IC電路上的設計更為簡單。然而,由於圖3中的處理 電路130依據電源電壓VDD2及控制信號TS來產生回授電壓VF,故電子裝置1中的電阻R3及電容C3亦可省略。 Therefore, the electronic device 1 of the embodiment of the present invention will adopt a technical means that is completely different from the DVFS, and the processor 131 controls the voltage regulator 20 coupled to each other to adjust the output voltage (ie, the power supply voltage VDD1). Not only does it reduce development costs, but it also makes designing on IC circuits simpler. However, due to the processing in Figure 3 The circuit 130 generates the feedback voltage VF according to the power supply voltage VDD2 and the control signal TS. Therefore, the resistor R3 and the capacitor C3 in the electronic device 1 can also be omitted.
更進一步來說,一併參閱圖4以說明圖3的補償電路133的實現細節。圖4是圖3之處理電路中的補償電路之電路示意圖。然而,圖4僅是本實施例的補償電路133的其中一種實現方式,並不以此為限。 Still further, reference is made to FIG. 4 to illustrate implementation details of the compensation circuit 133 of FIG. 4 is a circuit diagram of a compensation circuit in the processing circuit of FIG. However, FIG. 4 is only one implementation of the compensation circuit 133 of the embodiment, and is not limited thereto.
一併參閱圖1、圖3與圖4,控制信號TS包括開關控制信號TS1及開關控制信號TS2。另外,補償電路133包含兩組的電阻陣列1331及電阻陣列1333。詳細來說,電阻陣列1331由相互並聯的N個電阻Ra_1~Ra_N所組成,電阻Ra_1~Ra_N之每一者的第一端耦接於電路接腳120,電阻Ra_1~Ra_N之每一者的第二端則分別耦接於開關電路SW1_1~SW1_N,開關電路SW1_1~SW1_N受控於開關控制信號TS1,藉以選擇性地導通電阻Ra_1~Ra_N的第一端與接地電壓GND。 Referring to FIG. 1, FIG. 3 and FIG. 4 together, the control signal TS includes a switch control signal TS1 and a switch control signal TS2. In addition, the compensation circuit 133 includes two sets of the resistor array 1331 and the resistor array 1333. In detail, the resistor array 1331 is composed of N resistors Ra_1~Ra_N connected in parallel with each other, and the first end of each of the resistors Ra_1~Ra_N is coupled to the circuit pin 120, and each of the resistors Ra_1~Ra_N The two ends are respectively coupled to the switch circuits SW1_1~SW1_N, and the switch circuits SW1_1~SW1_N are controlled by the switch control signal TS1 to selectively turn on the first end of the resistors Ra_1~Ra_N and the ground voltage GND.
第二電阻陣列1333則由相互並聯的M個電阻Rb_1~Rb_M所組成,電阻Rb_1~Rb_M之每一者的第一端共同耦接於電路接腳110,電阻Rb_1~Rb_M之每一者的第二端則分別耦接於開關電路SW2_1~SW2_M,開關電路SW2_1~SW2_M受控於開關控制信號TS2,藉以選擇性地導通電阻Rb_1~Rb_M的第二端與電阻Ra_1~Ra_N的第一端。在一些實施例中,M和N可為大於等於2的正整數。 The second resistor array 1333 is composed of M resistors Rb_1~Rb_M connected in parallel with each other, and the first ends of each of the resistors Rb_1~Rb_M are commonly coupled to the circuit pin 110, and each of the resistors Rb_1~Rb_M The two ends are respectively coupled to the switch circuits SW2_1~SW2_M, and the switch circuits SW2_1~SW2_M are controlled by the switch control signal TS2, thereby selectively turning on the second ends of the resistors Rb_1~Rb_M and the first ends of the resistors Ra_1~Ra_N. In some embodiments, M and N can be positive integers greater than or equal to two.
因此,電壓調節器20能依據補償電路130輸出之回授電壓VF來調節所提供的第一電源電壓VDD1。如此一來,本案實施例的電子裝置1不僅可在低效能模式下降低靜態功耗損失,還可具有動態改變回授電壓VF的功能,使得電壓調節器20能夠據以調節出符合電子裝置1所期望接收的電源電壓。 Therefore, the voltage regulator 20 can adjust the supplied first power supply voltage VDD1 according to the feedback voltage VF output from the compensation circuit 130. In this way, the electronic device 1 of the embodiment of the present invention can not only reduce the static power consumption loss in the low performance mode, but also have the function of dynamically changing the feedback voltage VF, so that the voltage regulator 20 can adjust the compliance electronic device 1 accordingly. The power supply voltage that is expected to be received.
本案亦不限制開關控制信號TS1及開關控制信號TS2的具體實現方式,故本技術領域中具有通常知識者應可依據實際需求或應 用來進行設計。 This case also does not limit the specific implementation of the switch control signal TS1 and the switch control signal TS2, so those with ordinary knowledge in the technical field should be able to Used to design.
最後,參閱圖5以完整說明電子裝置的運作流程,圖5是本案實施例提供的輸入電壓補償方法之流程圖。本例所述的方法可以在圖1或圖2之實施例的電子裝置中執行。為了方便說明,本例所述的方法以圖1的電子裝置1為例。 Finally, referring to FIG. 5 to fully explain the operation flow of the electronic device, FIG. 5 is a flow chart of the input voltage compensation method provided by the embodiment of the present invention. The method described in this example can be performed in the electronic device of the embodiment of FIG. 1 or 2. For convenience of explanation, the method described in this example takes the electronic device 1 of FIG. 1 as an example.
在步驟S501中,電路接腳110接收由電壓調節器20的輸出端提供的電源電壓VDD1,使得電路接腳110具有電源電壓VDD2。 In step S501, the circuit pin 110 receives the power supply voltage VDD1 supplied from the output terminal of the voltage regulator 20 such that the circuit pin 110 has the power supply voltage VDD2.
在步驟S503中,處理電路130根據電路接腳110的電源電壓VDD2以產生回授電壓VF於第二電路接腳120,並使電壓調節器依據回授電壓VF來調節電源電壓VDD1。 In step S503, the processing circuit 130 generates a feedback voltage VF according to the power supply voltage VDD2 of the circuit pin 110 to the second circuit pin 120, and causes the voltage regulator to adjust the power supply voltage VDD1 according to the feedback voltage VF.
綜上所述,本案實施例所提供的電子裝置及輸入電壓補償方法,可藉由額外增設於同一晶片基板的電路接腳來耦接至電壓調節器的回授端,藉以降低PCB路徑及IC內部打線接合所造成的電壓衰退之影響,並且降低IC所操作於低效能模式下的功耗損失。除此之外,上述電子裝置及輸入電壓補償方法還可透過IC內部的電阻陣列來產生出回授電壓,以控制電壓調節器調節出符合IC所期望的輸出電壓。 In summary, the electronic device and the input voltage compensation method provided by the embodiments of the present invention can be coupled to the feedback terminal of the voltage regulator by additionally adding circuit pins on the same wafer substrate, thereby reducing the PCB path and the IC. The effect of voltage decay caused by internal wire bonding and the loss of power consumption of the IC operating in low-performance mode. In addition, the above electronic device and the input voltage compensation method can also generate a feedback voltage through the internal resistance array of the IC to control the voltage regulator to adjust the output voltage that is required by the IC.
1‧‧‧電子裝置 1‧‧‧Electronic device
110、120‧‧‧電路接腳 110, 120‧‧‧ circuit pins
130‧‧‧處理電路 130‧‧‧Processing Circuit
20‧‧‧電壓調節器 20‧‧‧Voltage regulator
210‧‧‧輸出端 210‧‧‧ Output
220‧‧‧回授端 220‧‧‧reporting end
VDD1、VDD2‧‧‧電源電壓 VDD1, VDD2‧‧‧ power supply voltage
VF‧‧‧回授電壓 VF‧‧‧ feedback voltage
Z1、Z2‧‧‧寄生阻抗 Z1, Z2‧‧‧ parasitic impedance
R1、R2、R3‧‧‧電阻 R1, R2, R3‧‧‧ resistance
C1、C2、C3‧‧‧電容 C1, C2, C3‧‧‧ capacitors
L1、L2‧‧‧電感 L1, L2‧‧‧ inductance
I1‧‧‧負載電流 I1‧‧‧Load current
GND‧‧‧接地電壓 GND‧‧‧ Grounding voltage
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