TWI419447B - Power converter and gate driver of power transistor thereof - Google Patents

Description

Power converter and gate driver for its power transistor

The present invention relates to a circuit for a gate driver for a power transistor, and more particularly to a gate driver for a power transistor for driving a power converter.

In order to provide the versatility of electronic products, power converters are often used in today's electronic devices as a medium for generating operating power. In the switching power converter, a power transistor with high withstand voltage and high current driving capability is required, and power conversion is performed by switching operation of the power transistor.

Since power transistors generally have large size characteristics, they also have relatively large gate parasitic capacitance. Therefore, in the gate driver of a conventional power transistor, a so-called Low Drop-Out Regulator (LDO Regulator) is often used to supply a sufficient current to drive the power transistor. However, in order to provide a large current to increase the switching speed of the power transistor, the low-dropout regulator needs to be equipped with a compensation capacitor for providing a larger driving current outside the chip for frequency compensation or a voltage stabilizing capacitor for voltage regulation. As a result, the complexity of the circuit design is increased, the stability of the circuit is sacrificed, and the overall BOM cost is increased.

In another approach, the operating power source received by the power transistor is a high voltage (eg, 40 volts) that is much higher than a logic voltage (eg, 3 volts). In the state of the control signal logic signal received by the gate driver of the power transistor, a so-called voltage level shifter must be constructed in the gate driver. The relative increase in the circuit component die area of the gate driver also increases its overall circuit cost.

The present invention provides a circuit for driving a gate driver of a power transistor to generate a drive output signal of a high drive current without using a voltage level shift circuit.

The present invention provides a power converter in which a gate driver of a driving power transistor generates a high voltage driving output signal without using a voltage level shifting circuit.

The present invention provides a circuit for a gate driver for driving a power transistor, including a pre-driver circuit and a post-driver circuit. The pre-driver circuit receives the first voltage as an operating power source, and the pre-driver circuit further receives the control signal and boosts the drive current of the control signal to generate a pre-drive control signal. The input of the rear drive circuit is directly connected to the output of the pre-drive circuit and receives the second voltage as an operating power source for the rear drive circuit. Moreover, the rear driving circuit further receives the pre-drive control signal and boosts the driving current of the pre-drive control signal and regulates the driving output voltage signal, wherein the driving output voltage signal is transmitted to the control terminal of the power transistor and the voltage level of the second voltage A voltage level greater than the first voltage.

In an embodiment of the invention, the gate driver described above further includes a low dropout voltage regulator circuit. The low dropout voltage stabilizing circuit is coupled to the pre-drive circuit, and the low dropout voltage stabilizing circuit receives the second voltage and adjusts the voltage level of the second voltage to generate the first voltage.

In an embodiment of the invention, the pre-driver circuit includes a plurality of first buffers and a plurality of second buffers. The plurality of first buffers are serially connected between the control signal and the first pre-drive control signal in the pre-drive control signal in accordance with the order of the drive currents of the respective first buffers. The plurality of second buffers are connected in series between the control signal and the second pre-drive control signal in the pre-drive control signal in accordance with the order of the drive currents of the second buffers. Wherein, the first pre-drive control signal is the reverse of the second pre-drive control signal.

In an embodiment of the invention, the pre-driver circuit further includes a first logic operator, a feedback inverter, and a second logic operator. The first logic operator is connected in series between the paths of the first buffer of the first stage to receive the control signal. The first logic operator receives and controls whether to pass the control signal to the first buffer according to the reverse feedback signal. The feedback inverter receives and reverses the second pre-drive control signal to generate a reverse feedback signal. The second logic operator is connected in series between the paths of the second buffer receiving the control signal of the first stage. The second logic operator receives and controls whether to pass the control signal to the first buffer according to the first pre-drive control signal.

In an embodiment of the invention, the first logic operator is a reverse gate.

In an embodiment of the invention, the second logic operator is a reverse OR gate.

In an embodiment of the invention, the first and second buffers are reverse gates.

In an embodiment of the invention, the subsequent driving circuit comprises a first high voltage transistor and a second high voltage transistor. The first high voltage transistor has a first end, a second end and a control end, and the control end receives the first pre-drive control signal, the first end of which receives the second voltage, and the second end of which generates the drive output signal. a second high voltage transistor having a first end, a second end, and a control end, the control end receiving the second pre-drive control signal, the first end of which is coupled to the second end of the first high voltage transistor to generate a drive output a signal, and the second end of the second high voltage transistor is coupled to the ground voltage.

In an embodiment of the invention, the voltage level of the first voltage is a logic voltage level.

The invention further provides a power converter comprising a power transistor and a gate driver. The gate driver is coupled to the control end of the power transistor and generates a drive output signal to control the power transistor. The gate driver includes a pre-drive circuit and a rear drive circuit. The pre-driver circuit receives the first voltage as an operating power source. The pre-driver circuit additionally receives the control signal and boosts the drive current of the control signal to generate a pre-drive control signal. The rear drive circuit is directly connected to the pre-drive circuit and receives the second voltage as an operating power source. The rear drive circuit further receives the pre-drive control signal and boosts the drive current of the pre-drive control signal to generate a drive output signal. Wherein, the driving output signal is transmitted to the control end of the power transistor and the voltage level of the second voltage is greater than the voltage level of the first voltage.

Based on the above, the present invention proposes a pre-driver circuit to receive a relatively low voltage first voltage as an operating voltage, thereby boosting the drive current of the control signal, and then generating a high voltage and a high current through a rear drive circuit that receives a relatively high voltage to operate the voltage. Drive output signal. The switching of the power transistor is effectively controlled by transmitting the drive output signal to the control terminal of the power transistor. In this way, the pre-drive circuit only needs to be constructed by using logic process components, which can save the area of the circuit layout and the total chip area. And through the high-voltage rear drive circuit, the high-voltage drive output signal is generated without the voltage level shift circuit, which can effectively save the layout area of the circuit and improve the price competitiveness of the product.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a gate driver 100 according to an embodiment of the invention. The gate driver 100 is coupled to the gate of the power transistor PT and is used to drive the power transistor PT. The gate driver 100 includes a pre-drive circuit 110 and a rear drive circuit 120. The pre-driver circuit 110 receives the voltage VDD1 as an operation power source. The pre-driver circuit 110 additionally receives the control signal CS and boosts the drive current of the control signal CS to generate a pre-drive control signal PDS. The rear drive circuit 120 is directly connected to the pre-drive circuit 110. The rear drive circuit 120 then receives the voltage VCC as an operating power source. The rear drive circuit 120 further receives the pre-drive control signal PDS and boosts the drive current of the pre-drive control signal to generate the drive output signal DS. The driving output signal DS is transmitted to the control terminal (gate) of the power transistor PT and the voltage level of the voltage VCC is greater than the voltage level of the voltage VDD1.

Further, the pre-driver circuit 110 receives the voltage VDD1 as the operating power source as a voltage (for example, 3 volts or 5 volts) that can provide a logic element action, and the control signal CS received by the pre-drive circuit 110 is a low voltage. The logic signal, that is, the control signal CS can be a signal that transitions between the voltage VDD1 and the ground voltage GND (0 volts). In addition, the pre-drive control signal PDS generated by the pre-driver circuit 110 is also a logic signal that transitions between the voltage VDD1 and the ground voltage GND (0 volts). Therefore, the pre-driver circuit 110 only needs a low voltage logic circuit element that can operate at the voltage VDD1 without using a high voltage circuit component.

Please note that after the pre-driver circuit 110 receives the control signal CS, the drive current for the control signal CS is boosted, thereby generating a pre-drive control signal PDS having a relatively strong drive current, and providing the pre-drive control signal PDS to Rear drive circuit 120.

The rear drive circuit 120 is then directly connected to the pre-drive circuit 110 to receive the pre-drive control signal PDS. The rear drive circuit 120 receives the voltage VCC as an operating power source. The voltage VCC is a high voltage power supply with respect to the voltage VDD1. The magnitude of the voltage level of the voltage VCC can then be determined by the operating power source received by the power transistor PT (e.g., 40 volts). Here, the rear driving circuit 120 further boosts the driving current of the pre-drive control signal PDS to generate the driving output signal DS, and the rear driving circuit 120 further boosts the current driving capability of the pre-driving control signal PDS according to the operating voltage VCC it receives. To generate a drive output signal DS. Specifically, the drive output signal DS is switched between the operating voltage VDD1 and the ground voltage GND.

As can be seen from the above description, the driving output signal DS received by the power transistor PT is switched between the operating voltage VDD1 and the ground voltage GND, and the driving current is performed by the pre-driving circuit 110 and the rear driving circuit 120. Improvement. The drive output signal DS can effectively control the on or off state of the power transistor PT without the need for an additional compensation component (such as a compensation capacitor or a voltage stabilizing capacitor) to provide additional drive current.

It should be noted that the gate driver 100 in this embodiment further includes a low dropout voltage stabilizing circuit 130. The low dropout regulator circuit 130 is coupled to the pre-driver circuit 110 and receives the voltage VCC. The low dropout voltage stabilizing circuit 130 operates at the voltage VCC and generates a voltage VDD1 by lowering the voltage level of the voltage VCC. Of course, the use of the low dropout voltage stabilizing circuit 130 to generate the voltage VDD1 as the operating power source of the pre-drive circuit 110 is only an example. The voltage VDD1 does not have to be generated by the low dropout regulator circuit 130, and the designer can supply the voltage VDD1 to the pre-driver circuit 110 depending on the condition of the system to which the gate driver 100 belongs. Regarding the low dropout voltage stabilizing circuit 130, since only the current must be supplied to the pre-drive circuit 110, the compensation capacitor or the stabilizing capacitor can be implemented by using a small capacitor in the wafer, without the need for an external compensation component as described in the prior art (for example Compensate capacitor or voltage regulator capacitor) to implement.

Referring to FIG. 2, FIG. 2 illustrates an embodiment of a pre-driver circuit 110 in accordance with an embodiment of the present invention. The pre-driver circuit 110 includes a plurality of first buffers BUF11 to BUF1N and a plurality of second buffers BUF21 to BUF2M, wherein N and M are positive integers representing the number of the first and second buffers. The first buffers BUF11 to BUF1N are sequentially connected in series with the first pre-drive control signal PDS1 in the control signal CS and the pre-drive control signal PDS in accordance with the order of the drive currents of the first buffers BUF11 to BUF1N. between. Similarly, the second buffers BUF21~BUF2M are sequentially connected in series from the control current CS and the pre-drive control signal PDS in a sequence of driving currents of the second buffers BUF21 to BUF2N. Drive control signal PDS2. In addition, the first and second pre-drive control signals PDS1 and PDS2 are mutually inverted. When the first and second buffers BUF11~BUF1N and BUF21~BUF2M are implemented by the reverse gate in the logic gate, N of them And M has an odd number and the other is an even number.

Specifically, the control signal CS is transmitted to the first buffers BUF11 to BUF1N, and the driving current is gradually increased in accordance with the connection order of the first buffers BUF11 to BUF1N to generate the first pre-drive control signal PDS1. The control signal CS is further transmitted to the second buffers BUF21 to BUF2M, and the driving current is gradually increased in accordance with the connection order of the second buffers BUF21 to BUF2M to generate the second pre-drive control signal PDS2. In this way, the pre-driver circuit 110 can effectively generate the first and second pre-drive control signals PDS1 and PDS2 having relatively high drive currents.

The pre-driver circuit 110 further includes logic operators 210, 220 and a feedback inverter FBUF1. The logic operator 210 is serially connected between the paths of the first buffer BUF11 of the first stage receiving the control signal CS, and the logic operator 210 receives and controls whether to transmit the control signal CS to the first buffer BUF11 according to the reverse feedback signal IFS. ~BUF1N. The logic operator 220 is connected in series between the paths of the second buffer BUF21 of the first stage receiving the control signal CS, and the logic operator 220 receives and controls whether to transmit the control signal CS to the second buffer according to the first pre-drive control signal PDS1. BUF21~BUF2M.

The feedback inverter FBUF1 is coupled to the logic operator 210 and the second pre-drive control signal PDS2. The feedback inverter FBUF1 receives the second pre-drive control signal PDS2 and reverses the second pre-drive control signal PDS2 to generate a reverse feedback signal IFS.

In the present embodiment, the logic operator 210 is constructed by the inverse gate in the logic gate, the logic operator 220 is constructed by the inverse gate in the logic gate, and the feedback inverter FBUF1 is constructed by using the reverse gate.

In particular, in the present embodiment, the logic operators 210 and 220 and the feedback inverter FBUF1 are configured to enable the first and second pre-drive control signals PDS1 and PDS2 to be enabled (transition to logic high precision). The time can be staggered, a so-called non-overlap circuit to avoid transistor burnout.

It is not difficult to know from the above description that in the present embodiment, all circuit elements of the pre-driver circuit 110 can be constructed using logic gates (reverse gates, reverse gates, and inverse or gates). That is to say, all the circuit components of the pre-driver circuit 110 need only use the low-voltage voltage VDD1 as the operation power source, and it is not necessary to use the high-voltage voltage VCC as the large-sized high-voltage component that operates the power source.

Referring to FIG. 3, FIG. 3 illustrates an embodiment of a rear driving circuit 120 according to an embodiment of the present invention. The rear drive circuit 120 includes a high voltage transistor HM1 and a HM2 of a high voltage or low voltage transistor. The high piezoelectric crystal HM1 has a first end, a second end and a control end, and the control end thereof receives the first pre-drive control signal PDS1, the first end of which receives the voltage VCC and the second end of which generates the drive output signal DS. The high voltage or low voltage transistor HM2 has a first end, a second end and a control end, and the control end receives the second pre-drive control signal PDS2, the first end of which is coupled to the second end of the first high voltage transistor HM1 to generate The output signal DS is driven, and the second end of the second transistor HM2 is coupled to the ground voltage GND.

In the present embodiment, the high voltage transistor HM1 and the high voltage or low voltage HM2 are both N-type transistors. Therefore, the control terminals (gates) of the high voltage transistors HM1 and HM2 can be effectively turned on or off only by the first and second pre-drive control signals PDS1 and PDS2 that receive the logic voltage level, and are generated to be high. Current drive capability output signal DS.

Incidentally, since the first and second pre-drive control signals PDS1 and PDS2 are opposite to each other, the high-voltage transistors HM1 and HM2 are not turned on at the same time. In addition, under the action of the logic operators 210 and 220 and the feedback inverter FBUF1 illustrated in FIG. 2, the on-time opportunity of the high-voltage transistor HM1 is performed after the high-voltage or low-voltage transistor HM2 is completely turned off. In contrast, the turn-on timing of the high-voltage or low-voltage transistor HM2 is also performed after the high-voltage transistor HM1 is completely turned off. In this way, it is possible to effectively prevent the high voltage transistors HM1 and HM2 from being partially turned on at the same time, so that the voltage VCC generates a large short-circuit breakdown current in the path in which the high-voltage transistors HM1 and HM2 are connected in series, causing the circuit to burn.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a power converter 400 according to an embodiment of the present invention. The power converter 400 includes a gate driver 410, a pulse width modulation controller 420, a diode D1, an inductor L1, a power transistor PT1, resistors R1 and R2, and a voltage stabilizing capacitor C1. The power converter 400 receives the input voltage VIN and converts the input voltage VIN by the switching action of the power transistor PT1 to generate the output voltage VOUT. The voltage dividing circuit formed by the resistors R1 and R2 divides the output voltage VOUT, and transmits the result of the voltage division to the pulse width modulation controller 420. The pulse width modulation controller 420 can determine whether the output voltage VOUT has risen to a required voltage according to the result of the voltage division, and accordingly, the switching operation of the power transistor PT1 is started or turned off by the output control signal CS. .

The gate driver 410 is connected in series between the pulse width modulation controller 420 and the power transistor PT1 to receive the control signal CS to generate a driving output signal DS for transmission to the control terminal of the power transistor PT1. The gate driver 410 includes a pre-driver circuit 411 and a rear driver circuit 412, and details of the operation of the gate driver 410 have been described in detail in the foregoing embodiments, and will not be described below.

Incidentally, the gate driver 410 is applicable to various types of power converters, and is not limited to the step-up power converter 400 illustrated in FIG. In the teachings of the embodiment illustrated in FIG. 4, those of ordinary skill in the art should know that as long as the gate driver 410 is disposed between the control terminal of the power transistor of any power converter and the pulse width modulation controller, The main features of embodiments of the invention can be implemented.

Referring to FIG. 5A and FIG. 5B, FIG. 5A and FIG. 5B respectively illustrate application circuit diagrams of the gate driver 100 according to the embodiment of the present invention. The gate driver 100 illustrated in FIGS. 5A and 5B is applied to the driving integrated circuit 510 of the light emitting diode. In the illustration of FIG. 5A, the driving integrated circuit 510 includes a power transistor PT1 and has a power input pin VINP, a current sensing pin CSN, a ground pin GNDP, a dimming signal pin DIM, and a power coupled to the power. The switch pin SW of the transistor PT1. The power input pin VINP directly receives the input voltage VIN, and the current sense pin CSN is connected to the input voltage VIN through the resistor RS. The ground pin GNDP directly receives the ground voltage GND, and the dimming signal pin DIM receives the dimming signal DIMS of the pulse width modulation signal.

It is to be noted that the switch pin SW provides the built-in power transistor PT1 in the integrated circuit 510 to couple the inductor L2 and the diode D2 outside the drive integrated circuit 500. The driving output signal DS generated by the gate driver 100 controls the on or off operation of the power transistor PT1 to generate a driving current to pass through the light emitting diode LD1, thereby illuminating the light emitting diode LD1.

In addition, in the drawing of FIG. 5B, the power input pin VINP directly receives the input voltage VIN, which may be generated by rectifying the AC voltage ACVIN through a rectifier composed of the diodes D3 to D6. Further, the number of the light-emitting diodes LD2 to LD4 driven by the integrated circuit 510 is not limited to one and can be increased as needed.

In summary, the present invention utilizes a pre-driver circuit that receives a low-voltage voltage as an operating power source and a rear-drive circuit that receives a high-voltage voltage as an operating power source to sequentially drive the drive current of the control signal to generate a drive output signal. The pre-driver circuit and the post-driver circuit are directly connected to each other, and a voltage level shift circuit is not required. Accordingly, the gate driver provided by the present invention can perform the action of generating a high-voltage drive output signal by using a minimum of high-voltage circuit components and saving an external compensation component. Effectively reduce the required circuit cost and improve the competitiveness of the product.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 410. . . Gate driver

110. . . Pre-driver circuit

120. . . Rear drive circuit

130. . . Low dropout regulator circuit

210, 220. . . Logical operator

400. . . Power converter

420. . . Pulse width modulation controller

510. . . Driving integrated circuit

FBUF1. . . Feedback reverser

VDD1, VCC. . . Voltage

CS. . . control signal

PDS, PDS1, PDS2. . . Pre-drive control signal

DS. . . Drive output signal

GND. . . Ground voltage

PT. . . Power transistor

BUF11~BUF1N, BUF21~BUF2M. . . buffer

HM1, HM2. . . High voltage crystal

R1, R2, RS. . . resistance

C1. . . capacitance

D1~D6. . . Dipole

L1, L2. . . inductance

VOUT. . . The output voltage

VIN. . . Input voltage

VINP, CSN, SW, DNDP, DIM. . . Pin

FIG. 1 is a schematic diagram of a gate driver 100 according to an embodiment of the invention.

FIG. 2 illustrates an embodiment of a pre-driver circuit 110 in accordance with an embodiment of the present invention.

FIG. 3 illustrates an embodiment of a rear drive circuit 120 in accordance with an embodiment of the present invention.

FIG. 4 is a schematic diagram of a power converter 400 in accordance with an embodiment of the present invention.

FIG. 5A and FIG. 5B respectively illustrate application circuit diagrams of the gate driver 100 according to the embodiment of the present invention.

100. . . Gate driver

110. . . Pre-driver circuit

120. . . Rear drive circuit

130. . . Low dropout regulator circuit

VDD1, VCC. . . Voltage

CS. . . control signal

PDS. . . Pre-drive control signal

DS. . . Drive output signal

GND. . . Ground voltage

PT. . . Power transistor

Claims (16)

A gate driver for driving a power transistor, comprising: a pre-drive circuit receiving a first voltage as an operation power source, the pre-drive circuit further receiving a control signal and boosting a drive current of the control signal to generate a a pre-drive control signal; and a rear drive circuit directly connected to the pre-drive circuit to receive a second voltage as an operation power supply, the rear drive circuit further receiving the pre-drive control signal and boosting a drive current of the pre-drive control signal A drive output signal is generated, wherein the drive output signal is transmitted to a control terminal of the power transistor and a voltage level of the second voltage is greater than a voltage level of the first voltage. The gate driver of claim 1, further comprising: a low dropout voltage stabilizing circuit coupled to the pre-drive circuit, receiving the second voltage and lowering a voltage level of the second voltage to generate the The first voltage. The gate driver of claim 1, wherein the pre-driver circuit comprises: a plurality of first buffers serially connected to the control signal and the pre-drive according to a sequence of driving currents of the first buffers a first pre-drive control signal in the control signal; and a plurality of second buffers connected in series with the second of the control signal and the pre-drive control signal in accordance with a sequence of driving currents of the second buffers Pre-driving the control signal, wherein the first pre-drive control signal is a reverse of the second pre-drive control signal. The gate driver of claim 3, wherein the pre-driver circuit further comprises: a first logic operator connected in series between the paths of the first buffer of the first stage to receive the control signal, the A logic operator receives and controls whether to transmit the control signal to the first buffers according to a reverse feedback signal; a feedback inverter that receives and reverses the second pre-drive control signal to generate the inverse Transmitting a signal; and a second logic operator serially connected between the paths of the second buffer of the first stage to receive the control signal, the second logic operator receiving and controlling according to the first pre-drive control signal Whether to transmit the control signal to the second buffers. The gate driver of claim 4, wherein the first logic operator is a reverse gate and the second logic operator is an inverse gate. The gate driver of claim 3, wherein each of the first and second buffers is a reverse gate. The gate driver of claim 3, wherein the rear driving circuit comprises: a first high voltage transistor having a first end, a second end, and a control end, the control end receiving the first pre-drive a control signal, a first end thereof receives the second voltage, and a second end thereof generates the driving output signal; and a second transistor having a first end, a second end, and a control end, the control end receiving the second The pre-drive control signal has a first end coupled to the second end of the first high voltage transistor to generate the drive output signal, and a second end of the second transistor coupled to a ground voltage. The gate driver of claim 1, wherein the voltage level of the first voltage is a logic voltage level. A power converter includes: a power transistor having a control terminal; and a gate driver coupled to the control terminal of the power transistor to generate a drive output signal for controlling the power transistor, including: a pre-drive circuit Receiving a first voltage as an operating power source, the pre-driving circuit further receiving a control signal and boosting a driving current of the control signal to generate a pre-drive control signal; and a rear driving circuit directly connecting the pre-driving circuit to receive a second voltage as an operating power source, the rear driving circuit further receiving the pre-drive control signal and boosting a driving current of the pre-drive control signal to generate the driving output signal, wherein the driving output signal is transmitted to the power transistor The control terminal and the voltage level of the second voltage are greater than the voltage level of the first voltage. The power converter of claim 9, further comprising: a low dropout voltage stabilizing circuit coupled to the pre-drive circuit, receiving the second voltage and lowering a voltage level of the second voltage to generate the The first voltage. The power converter of claim 9, wherein the pre-drive circuit comprises: a plurality of first buffers, according to driving currents of the first buffers The sequence is serially connected between the control signal and a first pre-drive control signal of the pre-drive control signal; and a plurality of second buffers are serially connected to the control according to a sequence of driving currents of the second buffers And a second pre-drive control signal of the pre-drive control signal, wherein the first pre-drive control signal is a reverse of the second pre-drive control signal. The power converter of claim 11, wherein the pre-driver circuit further comprises: a first logic operator serially connected between the paths of the first buffer of the first stage to receive the control signal, the A logic operator receives and controls whether to transmit the control signal to the first buffers according to a reverse feedback signal; a feedback inverter that receives and reverses the second pre-drive control signal to generate the inverse Transmitting a signal; and a second logic operator serially connected between the paths of the second buffer of the first stage to receive the control signal, the second logic operator receiving and controlling according to the first pre-drive control signal Whether to transmit the control signal to the second buffers. The power converter of claim 12, wherein the first logic operator is a reverse gate and the second logic operator is an inverse gate. The power converter of claim 11, wherein each of the first and second buffers is a reverse gate. The power converter of claim 11, wherein the rear drive circuit comprises: a first high voltage transistor having a first end, a second end, and a control end, the control end receiving the first pre-drive a control signal, a first end thereof receives the second voltage, and a second end thereof generates the driving output signal; and a second high voltage transistor having a first end, a second end, and a control end, the control end receiving the The second pre-drive control signal has a first end coupled to the second end of the first high voltage transistor to generate the drive output signal, and a second end of the second high voltage transistor coupled to a ground voltage. The power converter of claim 9, wherein the voltage level of the first voltage is a logic voltage level.