CN102625513B - Power converter and grid driver of power transistor thereof - Google Patents
Power converter and grid driver of power transistor thereof Download PDFInfo
- Publication number
- CN102625513B CN102625513B CN201110034693.2A CN201110034693A CN102625513B CN 102625513 B CN102625513 B CN 102625513B CN 201110034693 A CN201110034693 A CN 201110034693A CN 102625513 B CN102625513 B CN 102625513B
- Authority
- CN
- China
- Prior art keywords
- control signal
- voltage
- predrive
- receives
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000872 buffer Substances 0.000 claims description 48
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 15
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 15
- 239000008186 active pharmaceutical agent Substances 0.000 description 13
- 101100395484 Arabidopsis thaliana HPD gene Proteins 0.000 description 10
- 101100463166 Oryza sativa subsp. japonica PDS gene Proteins 0.000 description 10
- 101150061817 PDS1 gene Proteins 0.000 description 10
- 230000033228 biological regulation Effects 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Images
Landscapes
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
Abstract
A gate driver for driving a power transistor includes a pre-driver circuit and a post-driver circuit. The pre-driving circuit receives the first voltage as an operation power supply, and the pre-driving circuit receives the control signal and increases a driving current of the control signal to generate a pre-driving control signal. The rear drive circuit receives the second voltage as an operation power supply. The rear driving circuit receives the pre-driving control signal as an input signal and boosts a driving current of the pre-driving control signal to generate a driving output signal, wherein the driving output signal is transmitted to the control end of the power transistor and a voltage potential of the second voltage is greater than a voltage potential of the first voltage. The invention can effectively save the layout area of the circuit and improve the price competitiveness of the product.
Description
Technical field
The present invention relates to a kind of circuit of gate drivers of power transistor, and particularly relate to a kind of gate drivers of the power transistor that is used for driving power transducer.
Background technology
For providing electronic product multi-functional demand, in electronic installation now, often utilize power supply changeover device to be used as producing the medium of operating power.And in switch type power converter, need the power transistor of a high withstand voltage and high current drive capability, and move to carry out power supply conversion by the switching of power transistor.
Because power transistor has large-sized characteristic conventionally, therefore also relatively there is larger grid parasitic capacitance.Therefore,, in the gate drivers of existing power transistor, often utilize so-called low dropout voltage regulator (Low Drop-Out Regulator, LDO Regulator) to supply enough electric currents with driving power transistor.But in order to provide large electric current with the transistorized switch speed of bring to power, low dropout voltage regulator need to configure one in order to provide the building-out capacitor of larger drive current to carry out frequency compensation or electric capacity of voltage regulation carries out voltage stabilizing outside chip.Thus, increased the complexity of circuit design, sacrificed the stability of circuit and increased whole circuit board cost (BOM Cost).
In the another kind of practice, the operating power receiving due to power transistor is for example, for example, with respect to the high a lot of high tension voltage (40 volts) of logic voltage (3 volts).And under the state of the control signal logical signal receiving at the gate drivers of power transistor, a kind of so-called voltage potential deviator (voltage levelshifter) just must be configured in gate drivers.The demand of the relative circuit element chip area that has also increased gate drivers and increase its overall circuit cost.
Summary of the invention
The object of the present invention is to provide the circuit of the transistorized gate drivers of a kind of driving power, under the situation of not using voltage potential off-centre circuit, produce the drive output signal of high drive current.
The invention provides a kind of power supply changeover device, the transistorized gate drivers of driving power wherein produces the drive output signal of high pressure under the situation of not using voltage potential off-centre circuit.
The present invention proposes a kind of circuit of gate drivers, is used for driving power transistor, comprises predrive circuit and back driving circuit.Predrive circuit receives the first voltage usings as operating power, and the another reception control signal of predrive circuit the drive current that promotes control signal are to produce predrive control signal.The input of back driving circuit is directly connected in the output of predrive circuit, and receives the operating power that second voltage is usingd as back driving circuit.And, back driving circuit separately receives predrive control signal and promotes drive current and the regulation and control driver output voltage signal of predrive control signal, wherein, driver output voltage signal is transferred into the voltage potential that the control end of power transistor and the voltage potential of second voltage are greater than the first voltage.
In one embodiment of this invention, above-mentioned gate drivers, wherein also comprises low-pressure drop voltage-stabilizing circuit.Low-pressure drop voltage-stabilizing circuit is coupled to predrive circuit, and the voltage potential that low-pressure drop voltage-stabilizing circuit receives second voltage and adjusts second voltage is to produce the first voltage.
In one embodiment of this invention, above-mentioned predrive circuit comprises a plurality of the first buffers and a plurality of the second buffer.A plurality of the first buffers are serially connected between the first predrive control signal in control signal and predrive control signal according to the order of the drive current of each the first buffer.And a plurality of the second buffers, the order according to the drive current of each the second buffer is serially connected between the second predrive control signal in control signal and predrive control signal.Wherein, the first predrive control signal is the reverse signal of the second predrive control signal.
In one embodiment of this invention, above-mentioned predrive circuit also comprises the first logical-arithmetic unit, feedback reverser and the second logical-arithmetic unit.The first logical-arithmetic unit is serially connected between the path of the first buffer reception control signal of the first order.The first logical-arithmetic unit receives and whether controls transfer control signal to the first buffer according to reverse feedback signal.The reception of feedback reverser reverse the second predrive control signal are to produce reverse feedback signal.The second logical-arithmetic unit is serially connected between the path of the second buffer reception control signal of the first order.The second logical-arithmetic unit receives and whether controls transfer control signal to the first buffer according to the first predrive control signal.
In one embodiment of this invention, the first above-mentioned logical-arithmetic unit is NAND gate.
In one embodiment of this invention, the second above-mentioned logical-arithmetic unit is NOR gate.
In one embodiment of this invention, first and second above-mentioned buffer is not gate.
In one embodiment of this invention, above-mentioned back driving circuit comprises the first high voltage transistor and the second high voltage transistor.The first high voltage transistor, has first end, the second end and control end, and its control end receives the first predrive control signal, and its first end receives second voltage, and its second end produces drive output signal.The second high voltage transistor, there is first end, the second end and control end, its control end receives the second predrive control signal, and its first end couples the second end of the first high voltage transistor to produce drive output signal, and the second end of the second high voltage transistor couples earthed voltage.
In one embodiment of this invention, the voltage potential of the first above-mentioned voltage is logic voltage current potential.
The present invention is another proposes a kind of power supply changeover device, comprise power transistor with gate driver.Gate drivers couples the control end of power transistor, and produces drive output signal with power ratio control transistor, and gate drivers comprises predrive circuit and back driving circuit.Predrive circuit receives the first voltage and usings as operating power.The another reception control signal of predrive circuit the drive current that promotes control signal are to produce predrive control signal.Back driving circuit is directly connected in predrive circuit, and receives second voltage and using as operating power.The drive current that back driving circuit separately receives predrive control signal and promotes predrive control signal is to produce drive output signal.Wherein, drive output signal is transferred into the voltage potential that the control end of power transistor and the voltage potential of second voltage are greater than the first voltage.
Based on above-mentioned, the present invention proposes the first voltage that predrive circuit receives relative low-voltage and usings as operating voltage, and use the drive current that promotes control signal, then by receiving relative high voltage, think that the back driving circuit of operating voltage produces the drive output signal of the high electric current of high pressure.And by transmitting this drive output signal to the control end of power transistor, carry out the transistorized switching of effective power ratio control.Thus, predrive circuit only needs to utilize the construction of logic processing procedure element institute, can save the area and total chip area of circuit layout.And by coordinating the back driving circuit of high pressure, under the situation that does not need voltage potential off-centre circuit, produce the drive output signal of high pressure, can effectively save the layout area of circuit, the price competitiveness of product under promoting.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the schematic diagram of a gate drivers 100 of the embodiment of the present invention;
Fig. 2 illustrates an execution mode of the predrive circuit 110 of the embodiment of the present invention;
Fig. 3 illustrates an execution mode of the back driving circuit 120 of the embodiment of the present invention;
Fig. 4 illustrates the schematic diagram of the power supply changeover device 400 of one embodiment of the invention.
Fig. 5 A and Fig. 5 B illustrate respectively the application circuit of the gate drivers 100 of the embodiment of the present invention.
Main element symbol description
100,410: gate drivers
110: predrive circuit
120: back driving circuit
130: low-pressure drop voltage-stabilizing circuit
210,220: logical-arithmetic unit
400: power supply changeover device
420: PWM controller
510: drive integrated circult
FBUF1: feedback reverser
VDD1, VCC: voltage
CS: control signal
PDS, PDS1, PDS2: predrive control signal
DS: drive output signal
GND: earthed voltage
PT: power transistor
BUF11～BUF1N, BUF21～BUF2M: buffer
HM1, HM2: high voltage transistor
R1, R2, RS: resistance
C1: electric capacity
D1～D6: diode
L1, L2: inductance
VOUT: output voltage
VIN: input voltage
VINP, CSN, SW, DNDP, DIM: pin
Embodiment
Below please refer to Fig. 1, Fig. 1 illustrates the schematic diagram of a gate drivers 100 of the embodiment of the present invention.Gate drivers 100 is coupled to the grid of power transistor PT, and in order to driving power transistor PT.Gate drivers 100 comprises predrive circuit 110 and back driving circuit 120.Predrive circuit 110 receiver voltage VDD1 are usingd as operating power.The another reception control signal CS of predrive circuit 110 drive current that promotes control signal CS are to produce predrive control signal PDS.120 of back driving circuits directly connect predrive circuit 110.120 receiver voltage VCC of back driving circuit are usingd as operating power.120 another drive currents that receive predrive control signal PDS and promote this predrive control signal of back driving circuit are with generation drive output signal DS.Wherein, drive output signal DS is transferred into the voltage potential that the control end (grid) of power transistor PT and the voltage potential of voltage VCC are greater than voltage VDD1.
Further illustrate, predrive circuit 110 for example receives the voltage VDD1 of take as operating power, as the voltage (3 volts or 5 volts) of logic element action can be provided, the control signal CS that predrive circuit 110 receives is the logical signal of a low pressure, that is to say, control signal CS can be the signal of a transition between voltage VDD1 and earthed voltage GND (0 volt).In addition the predrive control signal PDS that, predrive circuit 110 produces is equally also the logical signal of a transition between voltage VDD1 and earthed voltage GND (0 volt).Therefore, predrive circuit 110 only needs to be operated in the low voltage logic circuit element of voltage VDD1, does not need to use the circuit element of high pressure.
At this, please note, after predrive circuit 110 reception control signal CS, drive current for control signal CS is promoted, and uses to produce and have the predrive control signal PDS of relatively strong drive current, and predrive control signal PDS is provided to back driving circuit 120.
120 of back driving circuits are to be directly connected to predrive circuit 110 to receive predrive control signal PDS.Back driving circuit 120 is that receiver voltage VCC comes as operating power.Voltage VCC is the power supply of a high pressure with respect to voltage VDD1.The operating power that the size of the voltage potential of voltage VCC can be received by power transistor PT decides (for example 40 volts).At this, the drive current that back driving circuit 120 more promotes predrive control signal PDS produces drive output signal DS, and the operating voltage VCC that back driving circuit 120 more receives according to it promotes the current driving ability of predrive control signal PDS to produce drive output signal DS.More specifically illustrate, drive output signal DS carries out transition between operating voltage VDD1 and earthed voltage GND.
By above-mentioned explanation, can be learnt, the drive output signal DS that power transistor PT receives carries out transition between operating voltage VDD1 and earthed voltage GND, and, the lifting of the drive current that process predrive circuit 110 and back driving circuit 120 carry out.Drive output signal DS is conducting or the off-state of power ratio control transistor PT effectively, and does not need additional compensating element, (for example building-out capacitor or electric capacity of voltage regulation) that extra drive current is provided.
It should be noted that the gate drivers 100 in the present embodiment also comprises low-pressure drop voltage-stabilizing circuit 130.Low-pressure drop voltage-stabilizing circuit 130 is coupled to predrive circuit 110 receiver voltage VCC.Low-pressure drop voltage-stabilizing circuit 130 be take voltage VCC as operating power, and the voltage potential that passes through to reduce voltage VCC is to produce voltage VDD1.Certainly, utilize low-pressure drop voltage-stabilizing circuit 130 to produce an example just only as the voltage VDD1 of the operating power of predrive circuit 110.Voltage VDD1 is also nonessential to be produced by low-pressure drop voltage-stabilizing circuit 130, and designer can provide voltage VDD1 to predrive circuit 110 according to the situation of the system under gate drivers 100.And about low-pressure drop voltage-stabilizing circuit 130 because need only provide electric current to predrive circuit 110, therefore the little electric capacity in utilized chip is implemented building-out capacitor or electric capacity of voltage regulation, does not need for example, to implement as additional compensating element, described in the prior art (building-out capacitor or electric capacity of voltage regulation).
Then please refer to Fig. 2, Fig. 2 illustrates an execution mode of the predrive circuit 110 of the embodiment of the present invention.Predrive circuit 110 comprises a plurality of first buffer BUF11～BUF1N and a plurality of second buffer BUF21～BUF2M, and N wherein and M are positive integers, represent the number of first and second buffer.First buffer BUF11～BUF1N, by the order of the drive current according to each first buffer BUF11～BUF1N, is sequentially serially connected between the first predrive control signal PDS1 in control signal CS and predrive control signal PDS from small to large.Similar, second buffer BUF21～BUF2M, by the order of the drive current according to each second buffer BUF21～BUF2N, is sequentially serially connected between the second predrive control signal PDS2 in control signal CS and predrive control signal PDS from small to large.In addition, first and second predrive control signal PDS1 and PDS2 are mutually reverse, when first and second buffer BUF11～BUF1N and BUF21～BUF2M implement by the not gate in gate, N wherein and M have one for odd number, and another is even number.
More specifically illustrate, control signal CS is transferred into first buffer BUF11～BUF1N, and produces the first predrive control signal PDS1 according to gradual its drive current that is raised of the order of connection of first buffer BUF11～BUF1N.And control signal CS is separately transferred into second buffer BUF21～BUF2M, and produce the second predrive control signal PDS2 according to gradual its drive current that is raised of the order of connection of second buffer BUF21～BUF2M.Thus, predrive circuit 110 just can effectively produce first and second predrive control signal PDS1 and the PDS2 with relatively high drive current.
Feedback reverser FBUF1 is coupled in logical-arithmetic unit 210 and the second predrive control signal PDS2.Feedback reverser FBUF1 receives the second predrive control signal PDS2 reverse the second predrive control signal PDS2 to produce reverse feedback signal IFS.
In the present embodiment, logical-arithmetic unit 210 is by the NAND gate in gate, and logical-arithmetic unit 220 carrys out construction by the NOR gate in gate, and feedback reverser FBUF1 utilizes not gate to carry out construction.
Please pay special attention to, in present embodiment, the configuration of logical-arithmetic unit 210,220 and feedback reverser FBUF1 is for first and second predrive control signal PDS1 and the PDS2 time of (transition is logic high potential) of being enabled can be staggered, the circuit of so-called non-crossover (non-overlap) namely, to avoid transistor to burn.
By above-mentioned explanation, be not difficult to learn, all circuit elements of predrive circuit 110 all can utilize gate (not gate, NAND gate and NOR gate) to carry out construction in the present embodiment.That is to say, all circuit elements of predrive circuit 110 all only need to utilize the voltage VDD1 of low pressure to come as operating power, and not needing to utilize needs the voltage VCC of high pressure to carry out the large-sized high voltage device as operating power.
With the next Fig. 3 that please refer to, Fig. 3 illustrates an execution mode of the back driving circuit 120 of the embodiment of the present invention.Back driving circuit 120 comprises the HM2 of high voltage transistor HM1 and high pressure or low voltage transistor.High voltage transistor HM1 has first end, the second end and control end, and its control end receives the first predrive control signal PDS1, its first end receiver voltage VCC, and its second end produces drive output signal DS.High pressure or low voltage transistor HM2 have first end, the second end and control end, its control end receives the second predrive control signal PDS2, its first end couples the second end of the first high voltage transistor HM1 to produce drive output signal DS, and the second end of transistor seconds HM2 couples earthed voltage GND.
In the present embodiment, high voltage transistor HM1 and high pressure or low pressure HM2 are N-type transistor.Therefore, first and second predrive control signal PDS1 and PDS2 that the control end of high voltage transistor HM1 and HM2 (grid) only must receive logic voltage potential just can effectively be switched on or disconnect, and go forward side by side to produce high current driving ability output signal DS.
Subsidiary one carries, and because first and second predrive control signal PDS1 and PDS2 are mutually reverse, therefore, high voltage transistor HM1 and HM2 can not be switched on simultaneously.In addition, under the effect of the logical-arithmetic unit 210,220 illustrating at Fig. 2 and feedback reverser FBUF1, during being switched on of high voltage transistor HM1, chance is just carried out after high pressure or low voltage transistor HM2 are disconnected completely, relative, also can just carry out the opportunity that is switched on of high pressure or low voltage transistor HM2 after high voltage transistor HM1 is disconnected completely.Thus, can effectively avoid high voltage transistor HM1 and HM2 by part conducting, to be made voltage VCC produce large short circuit breakdown current simultaneously on the path of high voltage transistor HM1 and HM2 serial connection, cause the situation of circuit burnout.
Please refer to Fig. 4, Fig. 4 illustrates the schematic diagram of the power supply changeover device 400 of one embodiment of the invention.Power supply changeover device 400 comprises gate drivers 410, PWM controller 420, diode D1, inductance L 1, power transistor PT1, resistance R 1, R2 and electric capacity of voltage regulation C1.Power supply changeover device 400 receives input voltage VIN and moves to change input voltage VIN to produce output voltage VO UT by the switching of power transistor PT1.Wherein, the formed bleeder circuit of resistance R 1 and R2 carries out dividing potential drop to output voltage VO UT, and the result of dividing potential drop is sent to PWM controller 420.420 of PWM controller can judge whether output voltage VO UT has risen to required voltage according to the result of this dividing potential drop, and pass through according to this that exported control signal CS starts or the switching of closing power transistor PT1 is moved.
410 of gate drivers are to be serially connected between PWM controller 420 and power transistor PT1, with reception control signal CS, produce the control end that drive output signal DS is sent to power transistor PT1.Gate drivers 410 comprises predrive circuit 411 and back driving circuit 412, and the existing detailed explanation in the foregoing embodiments of action details about gate drivers 410, seldom repeats with next.
Subsidiary one carries, and gate drivers 410 is applicable to various types of power supply changeover devices, is not limited only to the booster type power supply changeover device 400 that Fig. 4 illustrates.Under the teaching of the embodiment illustrating at Fig. 4, this area tool knows that the knowledgeable will be appreciated that conventionally, as long as gate drivers 410 is configured between the control end and PWM controller of power transistor of arbitrary power supply changeover device, just can implement the principal character of the embodiment of the present invention.
Please refer to Fig. 5 A and Fig. 5 B, Fig. 5 A and Fig. 5 B illustrate respectively the application circuit of the gate drivers 100 of the embodiment of the present invention.Wherein, the gate drivers 100 that Fig. 5 A and Fig. 5 B illustrate is for to be applied in the drive integrated circult 510 of light-emitting diode.In the illustrating of Fig. 5 A, drive integrated circult 510 comprises power transistor PT1, and the switch pins SW that has power supply input pin VINP, electric current induction pin CSN, ground connection pin GNDP, dim signal pin DIM and be coupled to power transistor PT1.Power supply input pin VINP directly receives input voltage VIN, and electric current induction pin CSN is connected to input voltage VIN by resistance R S.Ground connection pin GNDP directly receives earthed voltage GND, and dim signal pin DIM receives the dim signal DIMS of pulse-width modulation signal.
Please pay special attention to, switch pins SW provides power transistor PT1 built-in in drive integrated circult 510 to couple inductance L 2 and the diode D2 of drive integrated circult 500 outsides.The drive output signal DS producing by gate drivers 100 comes the conducting of power ratio control transistor PT1 or the action of disconnection, produces drive current to pass through light-emitting diode LD1, and uses and light light-emitting diode LD1.
In addition, in the illustrating of Fig. 5 B, it can be that the rectifier that utilizes alternating voltage ACVIN to form via diode D3～D6 to produce after rectification that power supply input pin VINP directly receives input voltage VIN.And the quantity of light-emitting diode LD2～LD4 that drive integrated circult 510 drives, is also not limited to one and can increase on demand.
In sum, the present invention utilizes and receives the predrive circuit that low voltage voltage is operating power and receive the back driving circuit that high tension voltage is operating power, with the drive current of incremental lifting control signal, produces drive output signal.Between predrive circuit and back driving circuit, directly interconnect, do not need voltage potential off-centre circuit.Accordingly, gate drivers provided by the present invention can recycle minimum high-tension circuit element and save in the situation of additional compensating element,, completes the action of the drive output signal that produces high pressure.Effectively reduce required circuit cost, improve the competitiveness of product.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when defining and be as the criterion depending on accompanying claim.
Claims (14)
1. a gate drivers, in order to drive a power transistor, is characterized in that, comprising:
One predrive circuit, receives one first voltage and usings as operating power, and the another drive current that receives a control signal and promote this control signal of this predrive circuit is to produce a predrive control signal; And
One back driving circuit, directly connect this predrive circuit, receiving a second voltage usings as operating power, the drive current that this back driving circuit separately receives this predrive control signal and promotes this predrive control signal to be to produce a drive output signal, and wherein this drive output signal is transferred into the voltage potential that the control end of this power transistor and the voltage potential of this second voltage are greater than this first voltage;
This predrive circuit comprises:
A plurality of the first buffers, are serially connected between one first predrive control signal in this control signal and this predrive control signal according to the order of the drive current of this first buffer respectively; And
A plurality of the second buffers, are serially connected between one second predrive control signal in this control signal and this predrive control signal according to the order of the drive current of this second buffer respectively;
Wherein, the reverse signal that this first predrive control signal is this second predrive control signal.
2. gate drivers as claimed in claim 1, is characterized in that, also comprises:
One low-pressure drop voltage-stabilizing circuit, couples this predrive circuit, and the voltage potential that receives this second voltage and reduce this second voltage is to produce this first voltage.
3. gate drivers as claimed in claim 1, is characterized in that, this predrive circuit also comprises:
One first logical-arithmetic unit, the first buffer that is serially connected in the first order receives between the path of this control signal, and this first logical-arithmetic unit receives and controls and whether transmit this and control signal to described the first buffer according to a reverse feedback signal;
One feedback reverser, receives also reverse this second predrive control signal to produce this reverse feedback signal; And
One second logical-arithmetic unit, the second buffer that is serially connected in the first order receives between the path of this control signal, and this second logical-arithmetic unit receives and controls and whether transmit this and control signal to described the second buffer according to this first predrive control signal.
4. gate drivers as claimed in claim 3, is characterized in that, this first logical-arithmetic unit is NAND gate, and this second logical-arithmetic unit is NOR gate.
5. gate drivers as claimed in claim 1, is characterized in that, the plurality of the first buffer BUF11-BUF1N and the plurality of the second buffer BUF21-BUF2M are not gate, and in M and N, one is that one of even number is odd number.
6. gate drivers as claimed in claim 1, is characterized in that, this back driving circuit comprises:
One first high voltage transistor, has first end, the second end and control end, and its control end receives this first predrive control signal, and its first end receives this second voltage, and its second end produces this drive output signal; And
One transistor seconds, there is first end, the second end and control end, its control end receives this second predrive control signal, and its first end couples the second end of this first high voltage transistor to produce this drive output signal, and the second end of this transistor seconds couples an earthed voltage.
7. gate drivers as claimed in claim 1, is characterized in that, the voltage potential of this first voltage is logic voltage current potential.
8. a power supply changeover device, is characterized in that, comprising:
One power transistor, has control end; And
One gate drivers, couples the control end of this power transistor, produces a drive output signal to control this power transistor, comprising:
One predrive circuit, receives one first voltage and usings as operating power, and the another drive current that receives a control signal and promote this control signal of this drive circuit is to produce a predrive control signal in advance; And
One back driving circuit, directly connect this predrive circuit, receiving a second voltage usings as operating power, the drive current that this back driving circuit separately receives this predrive control signal and promotes this predrive control signal to be to produce this drive output signal, and wherein this drive output signal is transferred into the voltage potential that the control end of this power transistor and the voltage potential of this second voltage are greater than this first voltage;
Wherein, this predrive circuit comprises:
A plurality of the first buffers, are serially connected between one first predrive control signal in this control signal and this predrive control signal according to the order of the drive current of this first buffer respectively; And
A plurality of the second buffers, are serially connected between one second predrive control signal in this control signal and this predrive control signal according to the order of the drive current of this second buffer respectively;
Wherein, the reverse signal that this first predrive control signal is this second predrive control signal.
9. power supply changeover device as claimed in claim 8, is characterized in that, also comprises:
One low-pressure drop voltage-stabilizing circuit, couples this predrive circuit, and the voltage potential that receives this second voltage and reduce this second voltage is to produce this first voltage.
10. power supply changeover device as claimed in claim 8, is characterized in that, this predrive circuit also comprises:
One first logical-arithmetic unit, the first buffer that is serially connected in the first order receives between the path of this control signal, and this first logical-arithmetic unit receives and controls and whether transmit this and control signal to described the first buffer according to a reverse feedback signal;
One feedback reverser, receives also reverse this second predrive control signal to produce this reverse feedback signal; And
One second logical-arithmetic unit, the second buffer that is serially connected in the first order receives between the path of this control signal, and this second logical-arithmetic unit receives and controls and whether transmit this and control signal to described the second buffer according to this first predrive control signal.
11. power supply changeover devices as claimed in claim 10, is characterized in that, this first logical-arithmetic unit is NAND gate, and this second logical-arithmetic unit is NOR gate.
12. power supply changeover devices as claimed in claim 8, is characterized in that, the plurality of the first buffer BUF11-BUF1N and the plurality of the second buffer BUF21-BUF2M are not gate, and in M and N, one is that one of even number is odd number.
13. power supply changeover devices as claimed in claim 8, is characterized in that, this back driving circuit comprises:
One first high voltage transistor, has first end, the second end and control end, and its control end receives this first predrive control signal, and its first end receives this second voltage, and its second end produces this drive output signal; And
One second high voltage transistor, there is first end, the second end and control end, its control end receives this second predrive control signal, and its first end couples the second end of this first high voltage transistor to produce this drive output signal, and the second end of this second high voltage transistor couples an earthed voltage.
14. power supply changeover devices as claimed in claim 8, is characterized in that, the voltage potential of this first voltage is logic voltage current potential.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100103142 | 2011-01-27 | ||
| TW100103142A TWI419447B (en) | 2011-01-27 | 2011-01-27 | Power converter and gate driver of power transistor thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102625513A CN102625513A (en) | 2012-08-01 |
| CN102625513B true CN102625513B (en) | 2014-03-12 |
Family
ID=46565135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110034693.2A Active CN102625513B (en) | 2011-01-27 | 2011-01-30 | Power converter and grid driver of power transistor thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102625513B (en) |
| TW (1) | TWI419447B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140072543A (en) * | 2012-12-05 | 2014-06-13 | 삼성전기주식회사 | Gate driving device and inverter having the same |
| KR101983158B1 (en) * | 2013-11-26 | 2019-05-28 | 삼성전기주식회사 | Gate driving device and inverter having the same |
| TWI692187B (en) * | 2018-12-24 | 2020-04-21 | 財團法人工業技術研究院 | Driving apparatus |
| CN111800010A (en) * | 2019-04-08 | 2020-10-20 | 华润矽威科技（上海）有限公司 | Switching power supply circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426348A (en) * | 1994-04-20 | 1995-06-20 | Wattsmart, Inc. | High efficiency ballast for operation of electronic lamps |
| CN101295977A (en) * | 2007-04-24 | 2008-10-29 | 松下电器产业株式会社 | Output circuit and multi-output circuit |
| CN101753123A (en) * | 2008-12-08 | 2010-06-23 | 绿达光电股份有限公司 | High-efficiency output drive circuit and related method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7298124B2 (en) * | 2004-12-01 | 2007-11-20 | Semiconductor Components Industries, L.L.C. | PWM regulator with discontinuous mode and method therefor |
| JP4347249B2 (en) * | 2005-03-31 | 2009-10-21 | 富士通マイクロエレクトロニクス株式会社 | DC-DC converter, control circuit for DC-DC converter, and control method for DC-DC converter |
| US7675276B2 (en) * | 2005-05-20 | 2010-03-09 | Torex Semiconductor Ltd. | DC/DC converter |
| JP5034451B2 (en) * | 2006-11-10 | 2012-09-26 | 富士通セミコンダクター株式会社 | Current mode DC-DC converter control circuit and current mode DC-DC converter control method |
| JP5205083B2 (en) * | 2008-03-07 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | Power supply |
| TW200938985A (en) * | 2008-03-14 | 2009-09-16 | Acbel Polytech Inc | Voltage-modulation circuit containing function enhancing light-load efficiency |
| CN101546957B (en) * | 2008-03-24 | 2012-07-25 | 凹凸电子（武汉）有限公司 | DC to DC converter having controller and control method thereof |
-
2011
- 2011-01-27 TW TW100103142A patent/TWI419447B/en active
- 2011-01-30 CN CN201110034693.2A patent/CN102625513B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426348A (en) * | 1994-04-20 | 1995-06-20 | Wattsmart, Inc. | High efficiency ballast for operation of electronic lamps |
| CN101295977A (en) * | 2007-04-24 | 2008-10-29 | 松下电器产业株式会社 | Output circuit and multi-output circuit |
| CN101753123A (en) * | 2008-12-08 | 2010-06-23 | 绿达光电股份有限公司 | High-efficiency output drive circuit and related method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201233015A (en) | 2012-08-01 |
| CN102625513A (en) | 2012-08-01 |
| TWI419447B (en) | 2013-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3044864B1 (en) | Bidirectional dc converter with two inputs and buck function in forward direction and boost function in reveress direction | |
| CN101789682B (en) | Multiple output power supply time sequence control device and method | |
| CN1436393A (en) | Deal drive buck regulator | |
| CN102332827B (en) | Power supply converter with electricity-saving mechanism and power supply conversion method | |
| CN102625513B (en) | Power converter and grid driver of power transistor thereof | |
| CN103516206A (en) | Switched mode power supply and method of operating thereof | |
| CN103840661A (en) | Buck power converter | |
| CN102830784A (en) | Power supply detection circuit and power supply circuit provided with same | |
| CN107040250A (en) | A kind of voltage mode drive circuit | |
| US20210409005A1 (en) | Chip, signal level shifter circuit, and electronic device | |
| CN113724660B (en) | Control circuit for voltage generator | |
| US20090322291A1 (en) | Integrated circuit with output drive power section | |
| CN110869877A (en) | Series circuit, circuit board and computing equipment | |
| CN103715877A (en) | Power supply apparatus relating to dc-dc voltage conversion and having short protection function | |
| KR102240439B1 (en) | Efficient Voltage Control System For USB Related Multiport Terminal | |
| CN102474182B (en) | Integrated circuit comprising voltage modulation circuitry and method therefor | |
| WO2023035271A1 (en) | Driving circuit and electronic device | |
| CN115051443A (en) | Camera power supply device for unmanned vehicle and unmanned vehicle | |
| US8487649B2 (en) | Output circuit, system including output circuit, and method of controlling output circuit | |
| CN105576948A (en) | Power management device, DC-DC control circuit and chip enabling method thereof | |
| CN101730329B (en) | Back light module control system and control method thereof | |
| CN101131809A (en) | LCD device and method for conveying gamma voltage signal | |
| US20120209936A1 (en) | Communication circuit and method utilizing a single communication line | |
| CN114362518A (en) | Bidirectional voltage conversion circuit suitable for high power | |
| US20120185705A1 (en) | Power supply circuit for a cpu |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |