TWI416681B - Chip on film arrangement - Google Patents
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Abstract
Description
本發明是有關於一種薄膜覆晶封裝排列，且特別是有關於一種可降低成本之薄膜覆晶封裝排列。The present invention relates to a film flip chip package arrangement, and more particularly to a thin film flip chip package arrangement that reduces cost.
在現有的薄膜覆晶(Chip on Film，COF)封裝技術中，每一張薄膜覆晶均需要有一定面積的測試區以供測試薄膜覆晶的好壞。請參照第1A圖及第1B圖，其繪示傳統薄膜覆晶封裝排列之不同例之示意圖。於第1A圖的每一張薄膜覆晶中，晶片的輸入腳位及輸出腳位被電性連接至位於不同側的輸入端及輸出端，故薄膜覆晶的兩側存在輸入測試區及輸出測試區以分別測試輸入腳位及輸出腳位。於第1B圖的每一張薄膜覆晶中，晶片的輸入腳位及輸出腳位被電性連接至位於同側的輸入及輸出端，故薄膜覆晶的單側存在一測試區(整合了輸入測試區及輸出測試區)以測試輸入腳位及輸出腳位。In the existing chip on film (COF) packaging technology, each film is covered with a test area of a certain area for the test film to be covered. Please refer to FIG. 1A and FIG. 1B , which are schematic diagrams showing different examples of the conventional film flip chip package arrangement. In each of the film flip-chips of FIG. 1A, the input pin and the output pin of the chip are electrically connected to the input end and the output end on different sides, so that there are input test areas and outputs on both sides of the film flip chip. Test area to test input pin and output pin separately. In each of the film flip-chips of FIG. 1B, the input pins and the output pins of the wafer are electrically connected to the input and output terminals on the same side, so that there is a test area on one side of the film flip chip (integrated Input test area and output test area) to test input pin and output pin.
然而，第1A圖及第1B圖中的輸入測試區、輸出測試區及測試區在如第2圖所示的外引腳結合(outer lead bond，OLB)打孔(punch)的過程會被留下不用，如第3A圖及第3B圖的打孔後薄膜覆晶封裝排列所示。比較第1A圖/第1B圖及第3A圖/第3B圖可知，若測試區的面積越大，則薄膜覆晶封裝排列中的彈性電路板(flexible circuit board)的使用率越低。如此一來，同樣面積的彈性電路板將無法呈載更多數目的薄膜覆晶，將導致成本居高不下。However, the input test area, the output test area, and the test area in FIGS. 1A and 1B are left in the process of outer lead bond (OLB) punch as shown in FIG. Not used, as shown in the 3A and 3B drawings after the punched film flip-chip package arrangement. Comparing FIGS. 1A/1B and 3A/3B, it can be seen that the larger the area of the test area, the lower the utilization rate of the flexible circuit board in the film flip chip package arrangement. As a result, the same area of the flexible circuit board will not be able to carry a larger number of film overlays, resulting in high costs.
本發明係有關於一種薄膜覆晶封裝排列，藉由改變薄膜覆晶的排列方向，提高彈性電路板的使用率，而得以大幅降低成本。The invention relates to a film flip chip package arrangement, which can greatly reduce the cost by changing the arrangement direction of the film flip chip and increasing the utilization rate of the elastic circuit board.
根據本發明之第一方面，提出一種薄膜覆晶封裝排列，包括一第一晶片、一第二晶片以及一彈性電路板。彈性電路板包括一第一接合區、一第二接合區及一共同測試區。第一接合區電性連接該第一晶片；第二接合區電性連接該第二晶片。共同測試區相鄰配置於第一接合區及第二接合區之間，具有多個測試引腳，每一個測試引腳經由第一接合區及第二接合區耦接至第一晶片的輸出腳位及第二晶片的輸出腳位，或耦接至第一晶片的輸入腳位及第二晶片的輸入腳位。According to a first aspect of the present invention, a thin film flip chip package arrangement is provided, comprising a first wafer, a second wafer, and an elastic circuit board. The flexible circuit board includes a first bonding area, a second bonding area, and a common test area. The first bonding region is electrically connected to the first wafer; the second bonding region is electrically connected to the second wafer. The common test area is disposed adjacent to the first bonding area and the second bonding area, and has a plurality of test pins, each of the test pins being coupled to the output pin of the first chip via the first bonding area and the second bonding area And the output pin of the second chip, or the input pin of the first chip and the input pin of the second chip.
為讓本發明之上述內容能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:
本發明提出一種薄膜覆晶封裝排列，藉由改變薄膜覆晶的排列方向，使得不同的薄膜覆晶可共用測試區，進而提高彈性電路板的使用率，而得以大幅降低成本。The invention provides a film flip-chip package arrangement, which can change the arrangement direction of the film flip-chip, so that different film flip-chips can share the test area, thereby increasing the utilization rate of the elastic circuit board, thereby greatly reducing the cost.
本發明係提出一種薄膜覆晶封裝排列，包括一第一晶片、一第二晶片以及一彈性電路板。彈性電路板包括一第一接合區、一第二接合區及一共同測試區。第一接合區電性連接該第一晶片；第二接合區電性連接該第二晶片。共同測試區相鄰配置於第一接合區及第二接合區之間，具有多個測試引腳，每一個測試引腳經由第一接合區及第二接合區耦接至第一晶片的輸出腳位及第二晶片的輸出腳位，或耦接至第一晶片的輸入腳位及第二晶片的輸入腳位。The invention provides a thin film flip chip package arrangement comprising a first wafer, a second wafer and an elastic circuit board. The flexible circuit board includes a first bonding area, a second bonding area, and a common test area. The first bonding region is electrically connected to the first wafer; the second bonding region is electrically connected to the second wafer. The common test area is disposed adjacent to the first bonding area and the second bonding area, and has a plurality of test pins, each of the test pins being coupled to the output pin of the first chip via the first bonding area and the second bonding area And the output pin of the second chip, or the input pin of the first chip and the input pin of the second chip.
請參照第4A圖及第4B圖，第4A繪示依照本發明第一實施例之薄膜覆晶封裝排列之示意圖，第4B圖繪示依照本發明第二實施例之薄膜覆晶封裝排列之示意圖。於第4A圖的每一張薄膜覆晶中，晶片的輸入腳位及輸出腳位被電性連接至位於不同側的輸入端及輸出端，且相鄰的晶片於接合區內的置放方向實質上是相反的。於第4B圖的每一張薄膜覆晶中，晶片的輸入腳位及輸出腳位被電性連接至位於同側的輸入及輸出端，且相鄰的晶片於接合區內的置放方向實質上是相反的。Please refer to FIG. 4A and FIG. 4B , FIG. 4A is a schematic diagram of a film flip chip package arrangement according to a first embodiment of the present invention, and FIG. 4B is a schematic view showing a film flip chip package arrangement according to a second embodiment of the present invention. . In each of the film flip-chips of FIG. 4A, the input pin and the output pin of the wafer are electrically connected to the input end and the output end on different sides, and the adjacent wafers are placed in the joint area. In essence, the opposite is true. In each of the film flip-chips of FIG. 4B, the input pins and the output pins of the wafer are electrically connected to the input and output terminals on the same side, and the adjacent wafers are placed in the joint area substantially. The opposite is true.
於第4A圖中，薄膜覆晶封裝排列400包括一第一晶片410、一第二晶片415以及一彈性電路板420。彈性電路板420包括一第一接合區430、一第二接合區435及一共同測試區440。第一接合區430電性連接第一晶片410；第二接合區435電性連接第二晶片415。共同測試區440相鄰配置於第一接合區430及第二接合區435之間。共同測試區440實質上具有如第4A圖所示之多個測試引腳，每一個測試引腳經由第一接合區430及第二接合區435的輸入端耦接至第一晶片410的輸入腳位及第二晶片415的輸入腳位。In FIG. 4A, the film flip chip package arrangement 400 includes a first wafer 410, a second wafer 415, and a flexible circuit board 420. The flexible circuit board 420 includes a first bonding region 430, a second bonding region 435, and a common test region 440. The first bonding region 430 is electrically connected to the first wafer 410; the second bonding region 435 is electrically connected to the second wafer 415. The common test zone 440 is disposed adjacent between the first junction zone 430 and the second junction zone 435. The common test area 440 has substantially a plurality of test pins as shown in FIG. 4A. Each test pin is coupled to the input pin of the first wafer 410 via the input ends of the first land 430 and the second land 435. The bit and the input pin of the second wafer 415.
此外，薄膜覆晶封裝排列400實質上更包括與彈性電路板420上的一第三接合區437電性連接之一第三晶片417。在第三接合區437與第一接合區430之間亦存在一共同測試區445。共同測試區445實質上具有如第4A圖所示之多個測試引腳，每一個測試引腳經由第一接合區430及第三接合區437的輸出端耦接至第一晶片410的輸出腳位及第三晶片417的輸出腳位。其中，共同測試區440及445的不同處在於，共同測試區440的測試引腳均耦接至晶片的輸入腳位，而共同測試區445的測試引腳均耦接至晶片的輸出腳位。In addition, the thin film flip chip package arrangement 400 further includes a third wafer 417 electrically connected to a third bonding region 437 on the flexible circuit board 420. A common test zone 445 is also present between the third land 437 and the first land 430. The common test area 445 has substantially a plurality of test pins as shown in FIG. 4A, and each test pin is coupled to the output pin of the first wafer 410 via the output ends of the first land 430 and the third land 437. The bit and the output pin of the third wafer 417. The common test areas 440 and 445 are different in that the test pins of the common test area 440 are coupled to the input pins of the chip, and the test pins of the common test area 445 are coupled to the output pins of the chip.
第一晶片410實質上具有一第一失能腳位，第二晶片415實質上亦具有一第二失能腳位。當共同測試區440的測試引腳耦接至第一晶片410的輸入腳位及第二晶片415的輸入腳位，共同測試區440更具有一第一失能引腳442及一第二失能引腳444，第一失能引腳442經由第一接合區430的輸入端耦接至第一晶片410的第一失能腳位，第二失能引腳444經由第二接合區435的輸入端耦接至及第二晶片415的第二失能腳位。The first wafer 410 has a first disabled pin, and the second die 415 also has a second disabled pin. When the test pin of the common test area 440 is coupled to the input pin of the first die 410 and the input pin of the second die 415, the common test zone 440 further has a first disable pin 442 and a second disable. The first disabling pin 442 is coupled to the first disabling pin of the first wafer 410 via the input end of the first bonding region 430, and the second disabling pin 444 is input through the second bonding region 435. The end is coupled to the second disabled pin of the second wafer 415.
當進行測試時，若欲測試第一晶片410，第二失能引腳444被施加一特定電壓以經由第二失能腳位使得第二晶片415的輸出腳位均呈現高阻抗狀態。如此一來，測試機台所讀取的即為第一晶片410的測試狀態(testing status)，可用以判斷第一晶片410是否通過測試。反之，若欲測試第二晶片415，第一失能引腳442被施加一特定電壓以經由第一失能腳位使得第一晶片410的輸出腳位均呈現高阻抗狀態。如此一來，測試機台所讀取的即為第二晶片415的測試狀態，可用以判斷第二晶片415是否通過測試。When testing, if the first wafer 410 is to be tested, the second disabling pin 444 is applied with a specific voltage to cause the output pins of the second wafer 415 to assume a high impedance state via the second disabling pin. In this way, the test machine reads the test status of the first wafer 410, and can be used to determine whether the first wafer 410 passes the test. On the other hand, if the second wafer 415 is to be tested, the first disabling pin 442 is applied with a specific voltage to cause the output pins of the first wafer 410 to assume a high impedance state via the first disabling pin. In this way, the test state read by the test machine is the test state of the second wafer 415, and can be used to determine whether the second wafer 415 passes the test.
於第4B圖中，薄膜覆晶封裝排列500包括一第一晶片510、一第二晶片515以及一彈性電路板520。彈性電路板520包括一第一接合區530、一第二接合區535及一共同測試區540。第一接合區530電性連接第一晶片510；第二接合區535電性連接第二晶片515。共同測試區540相鄰配置於第一接合區530及第二接合區535之間。共同測試區540實質上整合了共同輸出測試區及共同輸入測試區，其具有如第4B圖所示之多個測試引腳，每一個測試引腳經由第一接合區530及第二接合區535的輸入及輸出端耦接至第一晶片510及第二晶片515的輸入腳位及輸出腳位。In FIG. 4B, the thin film flip chip package arrangement 500 includes a first wafer 510, a second wafer 515, and a flexible circuit board 520. The flexible circuit board 520 includes a first bonding region 530, a second bonding region 535, and a common test region 540. The first bonding region 530 is electrically connected to the first wafer 510; the second bonding region 535 is electrically connected to the second wafer 515. The common test zone 540 is disposed adjacent to the first bonding zone 530 and the second bonding zone 535. The common test zone 540 substantially integrates a common output test zone and a common input test zone having a plurality of test pins as shown in FIG. 4B, each test pin via a first land 530 and a second land 535 The input and output terminals are coupled to the input pin and the output pin of the first die 510 and the second die 515.
第一晶片510實質上具有一第一失能腳位，第二晶片515實質上亦具有一第二失能腳位；共同測試區540更具有共同輸入測試區之一第一失能引腳542及一第二失能引腳544，第一失能引腳542經由第一接合區530的輸入及輸出端耦接至第一晶片510的第一失能腳位，第二失能引腳544經由第二接合區535的輸入及輸出端耦接至及第二晶片515的第二失能腳位。The first die 510 has a first disable pin, and the second die 515 has a second disable pin. The common test zone 540 further has a first input pin 542 of the common input test zone. And a second disable pin 544, the first disable pin 542 is coupled to the first disable pin of the first die 510 via the input and output terminals of the first bonding region 530, and the second disable pin 544 The input and output terminals of the second bonding region 535 are coupled to the second disabled pin of the second wafer 515.
當進行測試時，若欲測試第一晶片510，第二失能引腳544被施加一特定電壓以經由第二失能腳位使得第二晶片515的輸出腳位均呈現高阻抗狀態。如此一來，測試機台所讀取的即為第一晶片510的測試狀態，可用以判斷第一晶片510是否通過測試。反之，若欲測試第二晶片515，第一失能引腳542被施加一特定電壓以經由第一失能腳位使得第一晶片510的輸出腳位均呈現高阻抗狀態。如此一來，測試機台所讀取的即為第二晶片515的測試狀態，可用以判斷第二晶片515是否通過測試。When testing, if the first wafer 510 is to be tested, the second disabling pin 544 is applied with a specific voltage to cause the output pins of the second wafer 515 to assume a high impedance state via the second disabling pin. In this way, the test state read by the test machine is the test state of the first wafer 510, and can be used to determine whether the first wafer 510 passes the test. Conversely, if the second wafer 515 is to be tested, the first disable pin 542 is applied with a particular voltage to cause the output pins of the first wafer 510 to assume a high impedance state via the first disable pin. In this way, the test state read by the test machine is the test state of the second wafer 515, and can be used to determine whether the second wafer 515 passes the test.
在上述的接合區都具有指向標記以指示電性連接於接合區的晶片的輸出腳位的方向。以第4A圖為例，第一接合區430及第二接合區435的指向標記會相背離；反之，第一接合區430及第三接合區437的指向標記會相向。更進一步地，上述實施例所揭露之薄膜覆晶封裝排列，實質上係為一捲帶式結構。在第5圖所示的薄膜覆晶封裝排列的外引腳結合(outer lead bond，OLB)打孔(punch)的第一輪打孔過程中，例如與第一晶片410置放方向相同的所有晶片及其接合區會在對應於捲帶式結構為正向時被打孔。而在第一輪打孔結束後，將第5圖捲盤2反向後即可進行第二輪打孔。其中，與第二晶片415置放方向相同(亦即與第一晶片410置放方向相反)的所有晶片及其接合區會在對應於捲帶式結構為反向時被打孔。因此，本發明上述實施例所揭露之薄膜覆晶封裝排列，其在彈性電路板上用以指示晶片輸出腳位方向的指向標記並不會如第2圖所示的全部相同方向，而是如第5圖所示的交替方向。The junction regions described above all have pointing marks to indicate the direction of the output pins of the wafer that are electrically connected to the land. Taking FIG. 4A as an example, the pointing marks of the first land 430 and the second land 435 may face away from each other; otherwise, the pointing marks of the first land 430 and the third land 437 may face each other. Furthermore, the film flip chip package arrangement disclosed in the above embodiments is substantially a tape-and-reel structure. In the first round of the punching of the outer lead bond (OLB) punch of the film flip chip package arrangement shown in FIG. 5, for example, all of the same direction as the first wafer 410 is placed. The wafer and its land will be perforated when the tape-and-reel structure is positive. After the first round of punching is completed, the second round of punching can be performed by reversing the reel of the fifth drawing. Wherein, all the wafers and their bonding regions which are placed in the same direction as the second wafer 415 (ie, opposite to the direction in which the first wafer 410 is placed) may be perforated when the tape-reel structure is reversed. Therefore, the film flip-chip package arrangement disclosed in the above embodiments of the present invention, the pointing marks on the flexible circuit board for indicating the direction of the output pin of the wafer are not in the same direction as shown in FIG. 2, but The alternate direction shown in Figure 5.
第4A圖及第4B圖中的共同測試區在如第5圖所示的的過程會被留下不用，如第6A圖及第6B圖的打孔後薄膜覆晶封裝排列所示。比較第3A圖/第3B圖及第6A圖/第6B圖可知，本發明上述實施例所揭露之薄膜覆晶封裝排列相較於傳統的薄膜覆晶封裝排列，節省了將近百分之五十的共同測試區所佔彈性電路板的面積。如此一來，同樣面積的彈性電路板將可呈載更多數目的薄膜覆晶，大幅降低成本。The common test zone in Figures 4A and 4B will be left unused in the process as shown in Figure 5, as shown in the post-punch film flip-chip package arrangement of Figures 6A and 6B. Comparing the 3A/3B and the 6A/6B, the film flip chip package arrangement disclosed in the above embodiment of the present invention saves nearly 50% compared with the conventional film flip chip package arrangement. The common test area occupies the area of the flexible circuit board. In this way, the same area of the flexible circuit board will be able to carry a greater number of film overlays, significantly reducing costs.
本發明上述實施例所揭露之薄膜覆晶封裝排列，具有多項優點，以下僅列舉部分優點說明如下：本發明之薄膜覆晶封裝排列，藉由改變薄膜覆晶的排列方向，使得相鄰的薄膜覆晶可共用測試區，進而提高彈性電路板的使用率，而得以大幅降低成本。此外，利用兩輪外引腳結合打孔之方式，不需重新設計外引腳結合機台，解決了機台共用性的問題。The film flip chip package arrangement disclosed in the above embodiments of the present invention has a plurality of advantages. The following only some of the advantages are described as follows: the film flip chip package arrangement of the present invention, by changing the alignment direction of the film flip chip, so that adjacent films The flip chip can share the test area, thereby increasing the utilization rate of the flexible circuit board, and the cost is greatly reduced. In addition, the use of two rounds of external pins combined with punching, no need to redesign the external pins combined with the machine, to solve the problem of machine sharing.
綜上所述，雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
400、500．．．薄膜覆晶封裝排列400, 500. . . Film flip chip package arrangement
410、510．．．第一晶片410, 510. . . First wafer
415、515．．．第二晶片415, 515. . . Second chip
417．．．第三晶片417. . . Third chip
420、520．．．彈性電路板420, 520. . . Flexible circuit board
430、530．．．第一接合區430, 530. . . First junction
435、535．．．第二接合區435, 535. . . Second junction
437．．．第三接合區437. . . Third junction
440、445、540．．．共同測試區440, 445, 540. . . Common test area
442、542．．．第一失能引腳442, 542. . . First disable pin
444、544．．．第二失能引腳444, 544. . . Second disable pin
第1A圖及第1B圖繪示傳統薄膜覆晶封裝排列之不同例之示意圖。1A and 1B are schematic views showing different examples of conventional film flip-chip package arrangements.
第2圖繪示傳統薄膜覆晶封裝排列的外引腳結合打孔過程之示意圖。FIG. 2 is a schematic view showing the outer pin bonding and punching process of the conventional film flip chip package arrangement.
第3A圖及第3B圖繪示傳統打孔後薄膜覆晶封裝排列之不同例之示意圖。3A and 3B are schematic views showing different examples of conventional flip-chip film flip-chip package arrangements.
第4A圖繪示依照本發明第一實施例之薄膜覆晶封裝排列之示意圖。4A is a schematic view showing a film flip chip package arrangement in accordance with a first embodiment of the present invention.
第4B圖繪示依照本發明第一實施例之薄膜覆晶封裝排列之示意圖。FIG. 4B is a schematic view showing a film flip chip package arrangement according to the first embodiment of the present invention.
第5圖繪示依照本發明較佳實施例之薄膜覆晶封裝排列的外引腳結合打孔過程之示意圖。FIG. 5 is a schematic diagram showing an outer pin bonding and punching process of a film flip chip package arrangement in accordance with a preferred embodiment of the present invention.
第6A圖及第6B圖繪示依照本發明較佳實施例之打孔後薄膜覆晶封裝排列之不同例之示意圖。6A and 6B are schematic views showing different examples of the flip-chip package arrangement after punching in accordance with a preferred embodiment of the present invention.
400．．．薄膜覆晶封裝排列400. . . Film flip chip package arrangement
410．．．第一晶片410. . . First wafer
415．．．第二晶片415. . . Second chip
417．．．第三晶片417. . . Third chip
420．．．彈性電路板420. . . Flexible circuit board
430．．．第一接合區430. . . First junction
435．．．第二接合區435. . . Second junction
437．．．第三接合區437. . . Third junction
440、445．．．共同測試區440, 445. . . Common test area
442．．．第一失能引腳442. . . First disable pin
444．．．第二失能引腳444. . . Second disable pin
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99118965A TWI416681B (en) | 2010-06-10 | 2010-06-10 | Chip on film arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99118965A TWI416681B (en) | 2010-06-10 | 2010-06-10 | Chip on film arrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201145480A TW201145480A (en) | 2011-12-16 |
| TWI416681B true TWI416681B (en) | 2013-11-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW99118965A TWI416681B (en) | 2010-06-10 | 2010-06-10 | Chip on film arrangement |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI416681B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060099789A1 (en) * | 2004-10-22 | 2006-05-11 | Tessera, Inc. | Micro lead frame packages and methods of manufacturing the same |
| TW200912341A (en) * | 2007-06-06 | 2009-03-16 | Advantest Corp | TCP testing method and TCP testing apparatus |
| TW200926386A (en) * | 2007-12-14 | 2009-06-16 | Chipmos Technologies Inc | Chip carrier tape for packaging chips and chip package structure |
-
2010
- 2010-06-10 TW TW99118965A patent/TWI416681B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060099789A1 (en) * | 2004-10-22 | 2006-05-11 | Tessera, Inc. | Micro lead frame packages and methods of manufacturing the same |
| TW200912341A (en) * | 2007-06-06 | 2009-03-16 | Advantest Corp | TCP testing method and TCP testing apparatus |
| TW200926386A (en) * | 2007-12-14 | 2009-06-16 | Chipmos Technologies Inc | Chip carrier tape for packaging chips and chip package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201145480A (en) | 2011-12-16 |
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