TWI416677B - Package structure and manufacturing method thereof - Google Patents
Package structure and manufacturing method thereof Download PDFInfo
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- TWI416677B TWI416677B TW098103463A TW98103463A TWI416677B TW I416677 B TWI416677 B TW I416677B TW 098103463 A TW098103463 A TW 098103463A TW 98103463 A TW98103463 A TW 98103463A TW I416677 B TWI416677 B TW I416677B
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- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 claims description 120
- 239000002184 metal Substances 0.000 claims description 73
- 238000007747 plating Methods 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 12
- 229920001187 thermosetting polymer Polymers 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000007787 solid Substances 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 3
- 238000009713 electroplating Methods 0.000 abstract 3
- 235000012431 wafers Nutrition 0.000 description 68
- 230000008569 process Effects 0.000 description 6
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000011343 solid material Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229960002317 succinimide Drugs 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
一種封裝結構及其製法，尤指一種提升電性連接良率之封裝結構及其製法。A package structure and a method for manufacturing the same, in particular, a package structure for improving electrical connection yield and a method for manufacturing the same.
隨著半導體封裝技術的演進，除了傳統打線式(Wire bonding)或覆晶式(flip chip)半導體封裝技術以外，目前半導體裝置(Semiconductor device)已開發出不同的封裝型態，例如直接在一封裝基板(packaging substrate)中嵌埋並電性整合一例如具有積體電路之半導體晶片，此種封裝件可縮減整體半導體裝置之體積並提昇電性功能，遂成為一種封裝的主流。請參閱第1A至第1D圖，係為習知封裝基板之製法示意圖。With the evolution of semiconductor packaging technology, in addition to conventional wire bonding or flip chip semiconductor packaging technology, semiconductor devices have been developed in different package types, such as directly in a package. A semiconductor wafer, such as an integrated circuit, is embedded and electrically integrated in a packaging substrate. Such a package can reduce the volume of the entire semiconductor device and enhance electrical functions, and becomes a mainstream of the package. Please refer to FIGS. 1A to 1D for a schematic diagram of a conventional package substrate.
如第1A圖所示，首先，提供一第一承載板10，且該第一承載板10具有相對之第一表面10a及第二表面10b，並於該第一承載板10中形成至少一貫穿該第一表面10a及第二表面10b之開口101，且提供一第二承載板11，並將該第一承載板10之第二表面10b接合於該第二承載板11上。As shown in FIG. 1A, first, a first carrier 10 is provided, and the first carrier 10 has a first surface 10a and a second surface 10b opposite to each other, and at least one through hole is formed in the first carrier 10. The first surface 10a and the opening 101 of the second surface 10b are provided with a second carrier plate 11 and the second surface 10b of the first carrier plate 10 is joined to the second carrier plate 11.
如第1B圖所示，提供一半導體晶片12，其具有相對之作用面12a及非作用面12b，且該作用面12a上具有複數電極墊121，藉由一黏著材13將該半導體晶片12之非作用面12b固定於該開口101中的第二承載板11上。As shown in FIG. 1B, a semiconductor wafer 12 is provided having an opposite active surface 12a and an inactive surface 12b, and the active surface 12a has a plurality of electrode pads 121 thereon. The semiconductor wafer 12 is bonded by an adhesive 13 The non-acting surface 12b is fixed to the second carrier plate 11 in the opening 101.
如第1C圖所示，接著，於該第一承載板10及該半導體晶片12之作用面12a上以熱壓形成介電層14，且該介電層14填入該開口101與半導體晶片12之間的間隙中。As shown in FIG. 1C, a dielectric layer 14 is formed by hot pressing on the first carrier 10 and the active surface 12a of the semiconductor wafer 12, and the dielectric layer 14 fills the opening 101 and the semiconductor wafer 12. Between the gaps.
如第1D圖所示，以雷射先於該介電層14形成複數盲孔141，再於該盲孔141中及該介電層14上形成導電盲孔16及線路層15，以電性連接該半導體晶片12之電極墊121。As shown in FIG. 1D, a plurality of blind vias 141 are formed in advance of the dielectric layer 14 by lasers, and conductive vias 16 and circuit layers 15 are formed in the blind vias 141 and the dielectric layer 14 to electrically The electrode pads 121 of the semiconductor wafer 12 are connected.
然而，前述習知技術中，至少會產生兩次加工對位的誤差，以致於影響電性連接之良率；其一，由於該半導體晶片12與開口101的邊緣之間必須預留間隙，在該介電層14進行熱壓時，因為壓力等因素，易使該半導體晶片12於該開口101中偏移e，而此偏移e會造成該導電盲孔16連接該電極墊121之對位偏差，甚至因偏差過大而無法有效電性連接該電極墊121，如第1C圖所示；其二，以雷射形成該盲孔141時，亦可能產生對位誤差，造成該導電盲孔16連接該電極墊121之對位偏差，甚至因偏差過大而無法電性連接該電極墊121。However, in the prior art, at least two processing alignment errors are generated, so as to affect the yield of the electrical connection; first, since a gap must be reserved between the semiconductor wafer 12 and the edge of the opening 101, When the dielectric layer 14 is hot pressed, the semiconductor wafer 12 is easily offset by e in the opening 101 due to pressure and the like, and the offset e causes the conductive blind via 16 to be connected to the electrode pad 121. The deviation, even if the deviation is too large, can not be electrically connected to the electrode pad 121 as shown in FIG. 1C; secondly, when the blind hole 141 is formed by laser, a registration error may also occur, resulting in the conductive blind hole 16 The alignment deviation of the electrode pad 121 is connected, and the electrode pad 121 cannot be electrically connected even if the deviation is too large.
此外，除了上述的加工對位問題外，以雷射加工導電盲孔16還有成本較高、速度較慢且容易造成該半導體晶片12損壞等缺失。In addition, in addition to the above-described processing alignment problem, the laser processing of the conductive via hole 16 is also costly, slow, and easily causes damage to the semiconductor wafer 12.
因此，鑒於上述之問題，如何避免習知技術中半導體晶片之電極墊對位盲孔的兩次對位偏差，以造成電性連接不良等問題，實已成目前亟欲解決的課題。Therefore, in view of the above problems, how to avoid the problem of two alignment deviations of the electrode pad aligning blind holes of the semiconductor wafer in the prior art to cause problems such as poor electrical connection has become a problem to be solved.
鑒於上述習知技術之種種缺失，本發明之主要目的係在於提供一種提升電性連接良率之封裝結構及其製法。In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a package structure for improving the electrical connection yield and a method of manufacturing the same.
為達上述及其他目的，本發明提供一種封裝結構，係包括：介電層；半導體晶片，係設於該介電層中，且該半導體晶片具有相對之作用面及非作用面，該作用面具有複數電極墊，於各該電極墊上設有電鍍焊錫；電鍍金屬層，係設於該介電層部份表面上並圍繞各該電鍍焊錫；以及第一金屬層，係設於該電鍍金屬層上及各該電鍍焊錫上，且該第一金屬層及電鍍金屬層係構成線路層，並令部分圍繞各該電鍍焊錫的第一金屬層及電鍍金屬層作為電性連接凹槽，以包覆各該電鍍焊錫。To achieve the above and other objects, the present invention provides a package structure including: a dielectric layer; a semiconductor wafer disposed in the dielectric layer, wherein the semiconductor wafer has opposing active and non-active surfaces, the active surface a plurality of electrode pads having electroplated solder on each of the electrode pads; an electroplated metal layer disposed on a surface of the dielectric layer and surrounding each of the electroplated solders; and a first metal layer disposed on the electroplated metal layer And the first metal layer and the plated metal layer form a circuit layer, and the first metal layer and the plated metal layer partially surrounding each of the plating solders are used as electrical connection grooves to coat Each of the plating solders.
前述之封裝結構復可包括第一防焊層，係設於該介電層及線路層上，且該第一防焊層形成有複數開孔，以外露出部分之線路層，俾供作為電性接觸墊；又該半導體晶片之非作用面顯露於該介電層未形成該線路層之表面，可形成第二防焊層，且該第二防焊層中形成開口，令該半導體晶片之非作用面顯露於該開口。The package structure may include a first solder resist layer disposed on the dielectric layer and the circuit layer, and the first solder resist layer is formed with a plurality of openings, and the exposed portion of the circuit layer is provided as an electrical layer. a contact pad; and an inactive surface of the semiconductor wafer is exposed on a surface of the dielectric layer where the circuit layer is not formed, a second solder resist layer may be formed, and an opening is formed in the second solder resist layer to make the semiconductor wafer non-active The active surface is exposed to the opening.
本發明再提供一種封裝結構，係包括：基板，係具有相對之第一及第二表面，該基板中具有複數貫穿之導通孔，且該第一表面上具有電性連接各該導通孔之複數電性連接墊，各該電性連接墊上具有電鍍焊錫，而該第二表面上具有電性連接各該導通孔之線路層，該線路層具有複數電性接觸墊；半導體晶片，係設於該基板之第一表面上，且該半導體晶片具有相對之作用面及非作用面，該作用面具有複數電極墊，以對應導接各該電鍍焊錫；以及介電層，係覆蓋該基板之第一表面及該半導體晶片，且包覆各該電極墊、電性連接墊及電鍍焊錫。The present invention further provides a package structure, comprising: a substrate having opposite first and second surfaces, wherein the substrate has a plurality of through holes, and the first surface has a plurality of electrically connected to the through holes An electrical connection pad, each of the electrical connection pads has a plating solder, and the second surface has a circuit layer electrically connected to each of the via holes, the circuit layer has a plurality of electrical contact pads; the semiconductor wafer is disposed on the a first surface of the substrate, wherein the semiconductor wafer has opposite active and non-active surfaces, the active surface has a plurality of electrode pads for correspondingly guiding the respective plating solders; and the dielectric layer covers the first of the substrates The surface and the semiconductor wafer are coated with the electrode pads, the electrical connection pads, and the plated solder.
前述之封裝結構中，該些導通孔係為空心導電盲孔、實心導電盲孔或空心導電通孔。In the foregoing package structure, the via holes are hollow conductive blind holes, solid conductive blind holes or hollow conductive through holes.
依上所述，，復包括第一防焊層，係設於該基板之第二表面及線路層上，且該第一防焊層具有複數開孔，以對應外露出各該電性接觸墊，於該電性接觸墊上接置有焊球。According to the above, the first solder resist layer is disposed on the second surface of the substrate and the circuit layer, and the first solder resist layer has a plurality of openings to correspondingly expose the respective electrical contact pads. Solder balls are attached to the electrical contact pads.
又依上所述，該半導體晶片之非作用面外露出該介電層；復包括第二防焊層，係形成於該介電層未形成該線路層之表面，且該第二防焊層中形成開口，令該半導體晶片之非作用面顯露於該開口。According to the above, the non-active surface of the semiconductor wafer exposes the dielectric layer; the second solder resist layer is formed on the surface of the dielectric layer where the circuit layer is not formed, and the second solder resist layer An opening is formed in the semiconductor wafer to expose the inactive surface of the semiconductor wafer.
本發明復提供一種封裝結構之製法，係包括：提供一承載板，且於該承載板上形成第一金屬層；於部分之第一金屬層上形成電鍍金屬層，以形成複數電性連接凹槽；於該第一金屬層上接置具有相對之作用面及非作用面之半導體晶片，且該作用面上具有複數電極墊，各該電極墊上形成電鍍焊錫，以對應置入各該電性連接凹槽中，而令各該電性連接凹槽對應包覆各該電極墊；於該第一金屬層及該半導體晶片之非作用面上壓合介電層；移除該承載板，以外露出該第一金屬層；以及圖案化蝕刻該第一金屬層及電鍍金屬層，以於該介電層上形成線路層，並令各該電極墊藉由該電鍍焊錫電性連接該線路層。The invention provides a method for manufacturing a package structure, comprising: providing a carrier plate, and forming a first metal layer on the carrier plate; forming a plating metal layer on a portion of the first metal layer to form a plurality of electrical connection recesses a semiconductor wafer having opposite active and non-active surfaces is disposed on the first metal layer, and the active surface has a plurality of electrode pads, and each of the electrode pads is plated with solder to form corresponding electrical properties. Connecting the recesses, wherein each of the electrical connection recesses respectively covers the electrode pads; pressing the dielectric layer on the first metal layer and the inactive surface of the semiconductor wafer; removing the carrier board Exposing the first metal layer; and pattern etching the first metal layer and the plating metal layer to form a wiring layer on the dielectric layer, and electrically connecting the electrode pads to the circuit layer by the plating solder.
依上述封裝結構之製法，該電性連接凹槽之製法，係包括：於該第一金屬層上形成阻層，且該阻層形成有複數開口區，以露出部分之第一金屬層；於各該開口區中之第一金屬層上形成該電鍍金屬層；以及移除該阻層，以形成由該第一金屬層及電鍍金屬層所構成之電性連接凹槽。According to the manufacturing method of the above package structure, the method for manufacturing the electrical connection groove comprises: forming a resist layer on the first metal layer, and the resist layer is formed with a plurality of open regions to expose a portion of the first metal layer; Forming the plated metal layer on the first metal layer in each of the open regions; and removing the resist layer to form an electrical connection groove formed by the first metal layer and the plated metal layer.
依上述之製法，該介電層上具有第二金屬層，當移除該承載板時，一併移除該第二金屬層，令該半導體晶片之非作用面顯露於該介電層表面。According to the above method, the dielectric layer has a second metal layer. When the carrier is removed, the second metal layer is removed, so that the non-active surface of the semiconductor wafer is exposed on the surface of the dielectric layer.
依上所述，復包括於該介電層及線路層上形成第一防焊層，且該第一防焊層形成有複數開孔，以外露出部分之線路層，俾供作為電性接觸墊。According to the above, a first solder resist layer is formed on the dielectric layer and the circuit layer, and the first solder resist layer is formed with a plurality of openings, and a portion of the exposed circuit layer is provided as an electrical contact pad. .
又依上所述，該半導體晶片之非作用面顯露於該介電層表面；復包括於該介電層未形成該線路層之表面形成第二防焊層，且該第二防焊層中形成開口，令該半導體晶片之非作用面顯露於該開口。According to the above, the non-active surface of the semiconductor wafer is exposed on the surface of the dielectric layer; the second solder resist layer is formed on the surface of the dielectric layer where the circuit layer is not formed, and the second solder resist layer is An opening is formed to expose an inactive surface of the semiconductor wafer to the opening.
本發明又提供一種封裝結構之製法，係包括：提供一基板，係具有相對之第一及第二表面，該基板中具有複數導通孔，且該第一表面具有電性連接各該導通孔之電性連接墊，而該第二表面上具有電性連接各該導通孔之線路層；於該基板之第二表面上結合承載板；於該基板之第一表面上接置具有相對之作用面及非作用面之半導體晶片，且該半導體晶片之作用面上具有複數電極墊，各該電極墊具有電鍍焊錫，以對應結合至各該電性連接墊；於該基板之第一表面上壓合介電層，以包覆該半導體晶片、各該電極墊、電性連接墊及電鍍焊錫；以及移除該承載板，以外露出該線路層。The invention further provides a method for manufacturing a package structure, comprising: providing a substrate having opposite first and second surfaces, wherein the substrate has a plurality of via holes, and the first surface has electrical connection between each of the via holes An electrical connection pad, wherein the second surface has a circuit layer electrically connected to each of the via holes; a carrier plate is bonded to the second surface of the substrate; and the opposite surface is disposed on the first surface of the substrate And a non-active semiconductor wafer, and the active surface of the semiconductor wafer has a plurality of electrode pads, each of the electrode pads having electroplated solder for corresponding bonding to each of the electrical connection pads; and pressing on the first surface of the substrate a dielectric layer for covering the semiconductor wafer, each of the electrode pads, the electrical connection pads, and the plated solder; and removing the carrier plate to expose the circuit layer.
依上述封裝結構之製法，該些導通孔係為空心導電盲孔、實心導電盲孔或空心導電通孔；該承載板係藉由黏著材結合至該基板上；該介電層上具有熱固材，且於移除該承載板時，一併移除該熱固材。According to the manufacturing method of the above package structure, the via holes are hollow conductive blind holes, solid conductive blind holes or hollow conductive through holes; the carrier plate is bonded to the substrate by an adhesive material; the dielectric layer has thermosetting And removing the thermoset when the carrier is removed.
依上述之製法，復包括於該基板之第二表面及線路層上形成第一防焊層，且該第一防焊層形成有複數開孔，以外露出部分之線路層，俾供作為電性接觸墊，於該電性接觸墊上接置焊球。According to the above manufacturing method, the first solder resist layer is formed on the second surface of the substrate and the circuit layer, and the first solder resist layer is formed with a plurality of openings, and the exposed circuit layer is externally provided. A contact pad is attached to the electrical contact pad.
依上所述，該半導體晶片之非作用面外露出該介電層；復包括於該介電層未形成該線路層之表面形成第二防焊層，且該第二防焊層中形成開口，令該半導體晶片之非作用面顯露於該開口。According to the above, the dielectric layer is exposed outside the inactive surface of the semiconductor wafer; the second solder resist layer is formed on the surface of the dielectric layer where the circuit layer is not formed, and an opening is formed in the second solder resist layer. The inactive surface of the semiconductor wafer is exposed to the opening.
本發明另提供一種封裝結構之製法，係包括：提供一基板，係具有相對之第一及第二表面，該基板中具有複數導通孔，且該第一表面上具有連接各該導通孔之電性連接墊，各該電性連接墊上具有電鍍焊錫，而該第二表面上具有電性連接各該導通孔之線路層；於該基板之第二表面上結合承載板；於該基板之第一表面上接置具有相對之作用面及非作用面之半導體晶片，且該半導體晶片之作用面上具有複數電極墊，以對應接置於各該電鍍焊錫上；於該基板之第一表面上壓合介電層，以包覆該半導體晶片、各該電極墊、電性連接墊及電鍍焊錫；以及移除該承載板，以外露出該線路層。The invention further provides a method for manufacturing a package structure, comprising: providing a substrate having opposite first and second surfaces, wherein the substrate has a plurality of via holes, and the first surface has a connection for each of the via holes Each of the electrical connection pads has an electroplated solder, and the second surface has a circuit layer electrically connected to each of the via holes; and the carrier substrate is bonded to the second surface of the substrate; a semiconductor wafer having opposite active and non-active surfaces is disposed on the surface, and a plurality of electrode pads are disposed on the active surface of the semiconductor wafer to be correspondingly disposed on each of the plating solders; and the first surface of the substrate is pressed a dielectric layer is formed to cover the semiconductor wafer, each of the electrode pads, the electrical connection pads, and the plating solder; and the carrier plate is removed to expose the circuit layer.
依上述之封裝結構之製法，該些導通孔係為空心導電盲孔、實心導電盲孔或空心導電通孔；該承載板係藉由黏著材結合至該基板上；該介電層上具有熱固材，且於移除該承載板時，一併移除該熱固材。According to the manufacturing method of the above package structure, the via holes are hollow conductive blind holes, solid conductive blind holes or hollow conductive through holes; the carrier plate is bonded to the substrate by an adhesive; the dielectric layer has heat The solid material, and when the carrier plate is removed, the thermosetting material is removed together.
依上所述，復包括於該基板之第二表面及線路層上形成第一防焊層，且該第一防焊層形成有複數開孔，以外露出部分之線路層，俾供作為電性接觸墊，於該電性接觸墊上接置焊球。According to the above, a first solder resist layer is formed on the second surface of the substrate and the circuit layer, and the first solder resist layer is formed with a plurality of openings, and the exposed portion of the circuit layer is provided as an electrical property. A contact pad is attached to the electrical contact pad.
又依上所述，該半導體晶片之非作用面外露出該介電層，並於該介電層未形成該線路層之表面形成第二防焊層，且該第二防焊層中形成開口，令該半導體晶片之非作用面顯露於該開口。According to the above, the dielectric layer is exposed outside the inactive surface of the semiconductor wafer, and a second solder resist layer is formed on the surface of the dielectric layer where the circuit layer is not formed, and an opening is formed in the second solder resist layer. The inactive surface of the semiconductor wafer is exposed to the opening.
由上可知，本發明先於基板或承載板上形成對位結構，以利於該半導體晶片之設置，使各該電極墊預先完成輸出/輸入端的對位，以便於各該電極墊之對外電性連接，相較於習知技術之雷射盲孔製程，本發明不僅有效節省製程步驟及時間，且可避免各該電極墊的對位不良，而達到提升電性連接良率之目的。As can be seen from the above, the present invention forms an alignment structure on the substrate or the carrier board to facilitate the arrangement of the semiconductor wafer, so that the electrode pads are pre-aligned at the output/input end to facilitate the external electrical properties of the electrode pads. Compared with the laser blind hole process of the prior art, the invention not only effectively saves the process steps and time, but also avoids the misalignment of the electrode pads, and achieves the purpose of improving the electrical connection yield.
此外，本發明藉由該導通孔上之電性連接墊導接至該電鍍焊錫，或藉由該電性連接凹槽包覆該電鍍焊錫，均可利於該電極墊之對位接合。In addition, the present invention can facilitate the alignment bonding of the electrode pads by guiding the electrical connection pads on the via holes to the plating solder or by coating the plating solder through the electrical connection grooves.
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.
請參閱第2A至2I圖，係為本發明之封裝結構之製法之第一實施例之剖面示意圖。2A to 2I are schematic cross-sectional views showing a first embodiment of a method for fabricating a package structure of the present invention.
如第2A圖所示，首先，提供一承載板20，且於該承載板20上設有第一金屬層21a。As shown in FIG. 2A, first, a carrier 20 is provided, and a first metal layer 21a is disposed on the carrier 20.
如第2B圖所示，於該第一金屬層21a上形成阻層22，且該阻層22形成有複數開口區420，以露出部分之第一金屬層21a。As shown in FIG. 2B, a resist layer 22 is formed on the first metal layer 21a, and the resist layer 22 is formed with a plurality of open regions 420 to expose a portion of the first metal layer 21a.
如第2C圖所示，於各該開口區420中之第一金屬層21a上形成電鍍金屬層21b。As shown in FIG. 2C, a plated metal layer 21b is formed on the first metal layer 21a in each of the open regions 420.
如第2D圖所示，移除該阻層22，以形成由部分該第一金屬層21a及電鍍金屬層21b所組成之電性連接凹槽210。As shown in FIG. 2D, the resist layer 22 is removed to form an electrical connection recess 210 composed of a portion of the first metal layer 21a and the plated metal layer 21b.
如第2E圖所示，於該第一金屬層21a上接置一具有相對之作用面25a及非作用面25b的半導體晶片25，且該作用面25a上具有複數電極墊251，各該電極墊251上具有電鍍焊錫21c，以對應置入各該電性連接凹槽210中，而令各該電性連接凹槽210對應包覆各該電極墊251，接著進行回焊製程，藉以完成各該電極墊251與輸出/輸入端的預先對位。As shown in FIG. 2E, a semiconductor wafer 25 having a opposing active surface 25a and an inactive surface 25b is disposed on the first metal layer 21a, and the active surface 25a has a plurality of electrode pads 251, each of the electrode pads. The 251 has a plating solder 21c correspondingly disposed in each of the electrical connection grooves 210, so that the electrical connection grooves 210 respectively cover the electrode pads 251, and then a reflow process is performed, thereby completing each of the electrodes The electrode pad 251 is pre-aligned with the output/input.
如第2F圖所示，於該第一金屬層21a及該半導體晶片25之非作用面25b上壓合介電層26，且該介電層26上具有第二金屬層27。藉由熱壓合該第二金屬層27及介電層26，令該介電層26流動至該半導體晶片25週邊的空隙，以完整包覆各該電極墊251。As shown in FIG. 2F, the dielectric layer 26 is laminated on the first metal layer 21a and the non-active surface 25b of the semiconductor wafer 25, and the dielectric layer 26 has a second metal layer 27. The dielectric layer 26 is caused to flow to the gap around the semiconductor wafer 25 by thermally pressing the second metal layer 27 and the dielectric layer 26 to completely cover the electrode pads 251.
如第2G圖所示，藉由切削及物理剝除方式移除該承載板20，以外露出該第一金屬層21a；且一併移除該第二金屬層27，以外露出該半導體晶片25之非作用面25b及介電層26。As shown in FIG. 2G, the carrier layer 20 is removed by cutting and physical stripping, and the first metal layer 21a is exposed; and the second metal layer 27 is removed, and the semiconductor wafer 25 is exposed. The non-active surface 25b and the dielectric layer 26.
如第2H圖所示，藉由圖案化蝕刻該第一金屬層21a及電鍍金屬層21b，以形成線路層23，且令各該電極墊251藉由該電鍍焊錫21c電性連接至該電性連接凹槽210及該線路層23。然，有關線路層之製法種類繁多，於此不再贅述。As shown in FIG. 2H, the first metal layer 21a and the plated metal layer 21b are patterned and etched to form the wiring layer 23, and each of the electrode pads 251 is electrically connected to the electrical property by the plating solder 21c. The groove 210 and the wiring layer 23 are connected. However, there are many types of methods for the circuit layer, and will not be described here.
如第2I圖所示，於該介電層26及線路層23上形成第一防焊層29，且該第一防焊層29形成有複數開孔290，以外露出部分之線路層23，而作為電性接觸墊231，以供接置焊球28。又該介電層26未形成該線路層23之表面形成第二防焊層29’，該第二防焊層29’中形成有開口290’以對應顯露該半導體晶片25之非作用面25b。As shown in FIG. 2I, a first solder resist layer 29 is formed on the dielectric layer 26 and the wiring layer 23, and the first solder resist layer 29 is formed with a plurality of openings 290, and a portion of the wiring layer 23 is exposed. As the electrical contact pad 231, the solder ball 28 is attached. Further, the dielectric layer 26 is not formed on the surface of the wiring layer 23 to form a second solder resist layer 29'. The second solder resist layer 29' is formed with an opening 290' corresponding to the non-active surface 25b of the semiconductor wafer 25.
本發明藉由先於該承載板20上形成各該電性連接凹槽210，再令各該電極墊251與各該電性連接凹槽210進行對位接置，再經圖案化蝕刻以形成該線路層23，並使各該半導體晶片25之電極墊251藉由電鍍焊錫21c電性連接至該線路層23，俾令該半導體晶片25藉由各該線路層23以供對外電性連接。In the present invention, each of the electrical connection grooves 210 is formed on the carrier board 20, and then the electrode pads 251 are aligned with the respective electrical connection grooves 210, and then patterned and etched to form The circuit layer 23 and the electrode pads 251 of the semiconductor wafers 25 are electrically connected to the circuit layer 23 by plating solder 21c, and the semiconductor wafers 25 are electrically connected to each other by the circuit layers 23.
再者，本發明藉由該第一金屬層21a及電鍍金屬層21b包覆該電鍍焊錫21c，俾利於各該電極墊251與電性連接凹槽210之對位接合。Furthermore, in the present invention, the plating solder 21c is covered by the first metal layer 21a and the plating metal layer 21b, thereby facilitating the alignment bonding of the electrode pads 251 and the electrical connection grooves 210.
本發明復提供一種封裝結構，係包括：介電層26；半導體晶片25，係設於該介電層26中，且該半導體晶片25具有相對之作用面25a及非作用面25b，該作用面25a具有複數電極墊251，且各該電極墊251上設有電鍍焊錫21c，而該非作用面25b外露出該介電層26；電鍍金屬層21b，係形成於該介電層26部份表面上並圍繞各該電鍍焊錫21c；以及第一金屬層21a，係設於該電鍍金屬層21b上及各該電鍍焊錫21c上，且該第一金屬層21a及電鍍金屬層21b係構成線路層23，並令部分圍繞各該電鍍焊錫21b的第一金屬層21a及電鍍金屬層21b作為電性連接凹槽210，以包覆各該電鍍焊錫21c。The present invention further provides a package structure including a dielectric layer 26, a semiconductor wafer 25 disposed in the dielectric layer 26, and the semiconductor wafer 25 having an opposite active surface 25a and an inactive surface 25b. 25a has a plurality of electrode pads 251, and each of the electrode pads 251 is provided with a plating solder 21c, and the non-active surface 25b exposes the dielectric layer 26; the plating metal layer 21b is formed on a part of the surface of the dielectric layer 26. And surrounding the plating solder 21c; and the first metal layer 21a on the plating metal layer 21b and each of the plating solders 21c, and the first metal layer 21a and the plating metal layer 21b constitute the circuit layer 23, The first metal layer 21a and the plated metal layer 21b partially surrounding the plating solder 21b are electrically connected to the recess 210 to cover each of the plating solders 21c.
所述之封裝結構復包括第一防焊層29，係設於該介電層26及線路層23上，且該第一防焊層29形成有複數開孔290，以外露出部分之線路層23，俾供作為電性接觸墊231；且該介電層26未形成該線路層23之表面形成第二防焊層29’，該第二防焊層29’中形成有開口290’以對應顯露該半導體晶片25之非作用面25b。The package structure further includes a first solder resist layer 29 disposed on the dielectric layer 26 and the circuit layer 23, and the first solder resist layer 29 is formed with a plurality of openings 290, and the exposed portion of the circuit layer 23 And the dielectric layer 26 is not formed on the surface of the circuit layer 23 to form a second solder resist layer 29', and the second solder resist layer 29' is formed with an opening 290' to correspondingly reveal The non-active surface 25b of the semiconductor wafer 25.
請參閱第3A至3F圖，係為本發明之封裝結構之製法之第二實施例之剖面示意圖；本實施例與第一實施例之差異係在於半導體晶片對位接置之結構。3A to 3F are cross-sectional views showing a second embodiment of the method for fabricating a package structure of the present invention; the difference between this embodiment and the first embodiment lies in the structure in which the semiconductor wafers are aligned.
如第3A圖所示，首先，提供一基板31，係具有相對之第一表面31a及第二表面31b，該基板31中具有複數導通孔310，且該第一表面31a上具有連接各該導通孔310之複數電性連接墊310a，於各該電性連接墊310a上分別形成有電鍍焊錫32，而該第二表面31b上具有電性連接各該導通孔310之線路層33，該線路層33具有複數電性接觸墊331；後續請參考第4A至4C圖說明該導通孔310之不同態樣。As shown in FIG. 3A, first, a substrate 31 is provided having a first surface 31a and a second surface 31b. The substrate 31 has a plurality of via holes 310, and the first surface 31a has a connection. The plurality of electrical connection pads 310a of the holes 310 are formed with electroplated solders 32 on the respective electrical connection pads 310a, and the second surface 31b has a circuit layer 33 electrically connected to the via holes 310. 33 has a plurality of electrical contact pads 331; please refer to Figures 4A through 4C for different aspects of the vias 310.
如第3B圖所示，接著，於該基板31之第二表面31b及線路層33上以黏著材34結合一承載板30。As shown in FIG. 3B, a carrier 30 is bonded to the second surface 31b of the substrate 31 and the wiring layer 33 by an adhesive material 34.
如第3C圖所示，接著，於該基板31之第一表面31a上接置一具有相對之作用面25a及非作用面25b之半導體晶片25，且該半導體晶片25之作用面25a上具有複數電極墊251，以對應接置於各該電鍍焊錫32上，再進行回焊製程，藉以完成各該電極墊251與輸出/輸入端的預先對位。As shown in FIG. 3C, a semiconductor wafer 25 having an opposite active surface 25a and an inactive surface 25b is disposed on the first surface 31a of the substrate 31, and the active surface 25a of the semiconductor wafer 25 has a plurality of The electrode pads 251 are correspondingly placed on the respective plating solders 32, and then subjected to a reflow process to complete the pre-alignment of the electrode pads 251 and the output/input terminals.
如第3D圖所示，於該基板31之第一表面31a及半導體晶片25上壓合介電層36，且該介電層36上亦可具有熱固材37，藉由壓合該熱固材37及介電層36，令該介電層36包覆該半導體晶片25、各該電極墊251、電性連接墊310a及電鍍焊錫32，並且令該半導體晶片25之非作用面25b外露出該介電層36及熱固材37。As shown in FIG. 3D, the dielectric layer 36 is press-bonded onto the first surface 31a of the substrate 31 and the semiconductor wafer 25, and the dielectric layer 36 may have a thermosetting material 37 thereon. The dielectric layer 36 and the dielectric layer 36 are such that the dielectric layer 36 covers the semiconductor wafer 25, the electrode pads 251, the electrical connection pads 310a, and the plating solder 32, and the non-active surface 25b of the semiconductor wafer 25 is exposed. The dielectric layer 36 and the thermosetting material 37.
所述之介電層36係例如為雙順丁烯二酸醯亞胺/三氮阱；所述之熱固材37係例如聚丙烯、樹脂、ABF(Ajinomoto Build-up Film)、BCB(Benzocyclo-buthene)、LCP(Liquid Crystal Polymer)、PI(Poly-imide)等材料。藉由該熱固材37以熱壓合的方式，令該介電層36流動至該半導體晶片25週邊的空隙，以完整包覆各該電極墊251及電鍍焊錫32。The dielectric layer 36 is, for example, a bis-succinimide/trinitrogen trap; the thermosetting material 37 is, for example, polypropylene, resin, ABF (Ajinomoto Build-up Film), BCB (Benzocyclo). -buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide) and other materials. The dielectric layer 36 is caused to flow into the gap around the semiconductor wafer 25 by thermocompression bonding to completely cover the electrode pads 251 and the plating solder 32.
如第3E圖所示，藉由切削及物理剝除方式移除該承載板30，以外露出該基板31之第二表面31b上的線路層33及各該電性接觸墊331；同時，一併移除該熱固材37，並使該半導體晶片25之非作用面25b顯露於該介電層36。As shown in FIG. 3E, the carrier plate 30 is removed by cutting and physical stripping, and the circuit layer 33 on the second surface 31b of the substrate 31 and the respective electrical contact pads 331 are exposed; The thermoset 37 is removed and the non-active surface 25b of the semiconductor wafer 25 is exposed to the dielectric layer 36.
如第3F圖所示，於該基板31之第二表面31b及線路層33上形成第一防焊層39，且該第一防焊層39形成有複數開孔390，以對應外露出各該電性接觸墊331，俾供接置焊球38；另外，於該介電層36未形成該線路層33上形成有第二防焊層39’，且該第二防焊層29’中形成有開口390’以對應外露該半導體晶片25之非作用面25b。As shown in FIG. 3F, a first solder resist layer 39 is formed on the second surface 31b of the substrate 31 and the circuit layer 33, and the first solder resist layer 39 is formed with a plurality of openings 390 to correspondingly expose the respective openings. The electrical contact pad 331 is provided with the solder ball 38; further, the second solder resist layer 39' is formed on the circuit layer 33 where the dielectric layer 36 is not formed, and the second solder resist layer 29' is formed. There is an opening 390' to correspondingly expose the inactive surface 25b of the semiconductor wafer 25.
接著，請一併參閱第4A至4C圖，係說明該導通孔310之型式；如第4A圖所示，該導通孔310係為空心導電盲孔；如第4B圖所示，該導通孔310係為實心導電盲孔；如第4C圖所示，該導通孔310係為空心導電通孔。Next, please refer to FIG. 4A to FIG. 4C for explaining the type of the via hole 310; as shown in FIG. 4A, the via hole 310 is a hollow conductive blind hole; as shown in FIG. 4B, the via hole 310 is as shown in FIG. 4B. The system is a solid conductive blind hole; as shown in FIG. 4C, the via hole 310 is a hollow conductive via.
本發明藉由先於該基板31之第一表面31a之電性連接墊310a上形成各該電鍍焊錫32，且於該第二表面31b上形成各該電性接觸墊331，再令該半導體晶片25之電極墊251與各該電鍍焊錫32進行對位接置，令該半導體晶片25藉由各該導通孔310及電性接觸墊331進行對外電性連接。In the present invention, each of the plating solders 32 is formed on the electrical connection pads 310a of the first surface 31a of the substrate 31, and the electrical contact pads 331 are formed on the second surface 31b, and the semiconductor wafer is further formed. The electrode pads 251 of 25 are aligned with the plating pads 32, and the semiconductor wafers 25 are externally electrically connected by the via holes 310 and the electrical contact pads 331.
請參閱第5A至5C圖，係為本發明之封裝結構之製法之第三實施例之剖面示意圖。本實施例與第二實施例之差異僅在於電鍍焊錫之形成位置，其餘相關封裝結構之製程均大致相同，因此不再重複說明相同部份之製程，以下僅說明其相異處，特此敘明。Please refer to FIGS. 5A to 5C for a cross-sectional view showing a third embodiment of the method for fabricating the package structure of the present invention. The difference between this embodiment and the second embodiment lies in the formation position of the electroplated solder, and the processes of the other related package structures are substantially the same. Therefore, the process of the same part will not be repeated, and only the differences will be described below. .
如第5A圖所示，首先，提供一基板31，係具有相對之第一表面31a及第二表面31b，該基板31中具有複數導通孔310，且該第一表面31a上具有電性連接各該導通孔310之複數電性連接墊310a，而該第二表面31b上具有電性連接各該導通孔310之線路層33，該線路層33具有複數電性接觸墊331。As shown in FIG. 5A, a substrate 31 is provided with a first surface 31a and a second surface 31b. The substrate 31 has a plurality of via holes 310, and the first surface 31a has electrical connections. The plurality of vias 310 are electrically connected to the pad 310a, and the second surface 31b has a circuit layer 33 electrically connected to each of the vias 310. The circuit layer 33 has a plurality of electrical contact pads 331.
如第5B圖所示，接著，於該基板31之第二表面31b上藉由黏著材34結合一承載板30。As shown in FIG. 5B, a carrier plate 30 is then bonded to the second surface 31b of the substrate 31 by an adhesive material 34.
如第5C圖所示，之後，於該基板31之第一表面31a上接置一具有相對之作用面25a及非作用面25b之半導體晶片25，且該半導體晶片25之作用面25a上具有複數電極墊251，各該電極墊251具有電鍍焊錫32，以對應結合至各該電性連接墊310a上，再進行回焊製程，藉以完成各該電極墊251與輸出/輸入端的預先對位。之後則接續前述之第3D所示之製法，於此不再贅述。As shown in FIG. 5C, a semiconductor wafer 25 having an opposite active surface 25a and an inactive surface 25b is disposed on the first surface 31a of the substrate 31, and the active surface 25a of the semiconductor wafer 25 has a plurality of The electrode pads 251 each have a plating solder 32 for correspondingly bonding to each of the electrical connection pads 310a, and then performing a reflow process to complete the pre-alignment of the electrode pads 251 and the output/input terminals. Then, the method shown in the above 3D is continued, and details are not described herein again.
本發明藉由該基板31之第一表面31a之電性連接墊310a、及於該第二表面31b上形成各該電性接觸墊331，再令各該電極墊251藉由該電鍍焊錫32與各該電性連接墊310a進行對位接置，俾該半導體晶片25藉由各該導通孔310及電性接觸墊331進行對外電性連接。In the present invention, the electrical contact pads 310a of the first surface 31a of the substrate 31 and the electrical contact pads 331 are formed on the second surface 31b, and the electrode pads 251 are respectively made by the plating solder 32. The electrical connection pads 310a are electrically connected to each other, and the semiconductor wafers 25 are externally electrically connected by the via holes 310 and the electrical contact pads 331.
再者，本發明藉由該導通孔310之電性連接墊310a導接至該電鍍焊錫32，俾利於各該電極墊251與電性連接墊310a之對位接合。Furthermore, the present invention is guided to the plating solder 32 by the electrical connection pads 310a of the via holes 310, thereby facilitating the alignment bonding of the electrode pads 251 and the electrical connection pads 310a.
本發明又提供一種封裝結構，係包括：基板31，係具有相對之第一表面31a及第二表面31b，該基板31中具有複數導通孔310，且該第一表面31a上具有連接各該導通孔310之複數電性連接墊310a，各該電性連接墊310a上具有電鍍焊錫32，而該第二表面31b上具有電性連接各該導通孔310之線路層33；半導體晶片25，係設於該基板31之第一表面31a上，且該半導體晶片25具有相對之作用面25a及非作用面25b，該作用面25a具有複數電極墊251，以對應導接各該電鍍焊錫32；以及介電層36，係覆蓋該基板31之第一表面31a及該半導體晶片25。The present invention further provides a package structure, comprising: a substrate 31 having an opposite first surface 31a and a second surface 31b, the substrate 31 having a plurality of via holes 310, and the first surface 31a having a connection therebetween The plurality of electrical connection pads 310a of the holes 310, each of the electrical connection pads 310a has a plating solder 32, and the second surface 31b has a circuit layer 33 electrically connected to each of the via holes 310. The semiconductor wafer 25 is provided. On the first surface 31a of the substrate 31, the semiconductor wafer 25 has an opposite active surface 25a and a non-active surface 25b. The active surface 25a has a plurality of electrode pads 251 for correspondingly guiding the respective plating solders 32; The electrical layer 36 covers the first surface 31a of the substrate 31 and the semiconductor wafer 25.
所述之導通孔310係為空心導電盲孔、實心導電盲孔或空心導電通孔；該半導體晶片25之非作用面25b外露出該介電層36。The via hole 310 is a hollow conductive blind hole, a solid conductive blind hole or a hollow conductive through hole; the dielectric layer 36 is exposed outside the non-active surface 25b of the semiconductor wafer 25.
所述之封裝結構復包括第一防焊層39，係設於該介電層36及線路層33上，且該第一防焊層39形成有複數開孔390，以外露出部分之線路層33，俾供作為電性接觸墊331；且該介電層36未形成該線路層33之表面形成第二防焊層39’，該第二防焊層39’中形成有開口390’以對應顯露該半導體晶片25之非作用面25b。The package structure further includes a first solder resist layer 39 disposed on the dielectric layer 36 and the circuit layer 33, and the first solder resist layer 39 is formed with a plurality of openings 390, and the exposed portion of the circuit layer 33 And the dielectric layer 36 is not formed on the surface of the circuit layer 33 to form a second solder resist layer 39', and the second solder resist layer 39' is formed with an opening 390' to correspondingly expose The non-active surface 25b of the semiconductor wafer 25.
綜上所述，本發明先於基板或承載板上形成對位結構，以利於該半導體晶片之設置，且便於各該電極墊之對外電性連接，有效節省製程步驟及時間，且降低對位誤差，以達到提升電性連接良率之目的。In summary, the present invention forms an alignment structure on a substrate or a carrier board to facilitate the arrangement of the semiconductor wafer, and facilitates external electrical connection of the electrode pads, thereby effectively saving process steps and time, and reducing alignment. The error is to achieve the purpose of improving the electrical connection yield.
再者，本發明藉由該導通孔之電性連接墊導接至該電鍍焊錫，或藉由該電性連接凹槽包覆該電鍍焊錫，均利於該電極墊之對位接合。Furthermore, the present invention facilitates the alignment bonding of the electrode pads by guiding the electrical connection pads of the via holes to the plating solder or by coating the plating solder by the electrical connection grooves.
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
10．．．第一承載板10. . . First carrier board
10a,31a．．．第一表面10a, 31a. . . First surface
10b,31b．．．第二表面10b, 31b. . . Second surface
101,290’,390’．．．開口101,290’,390’. . . Opening
11．．．第二承載板11. . . Second carrier
12,25．．．半導體晶片12,25. . . Semiconductor wafer
12a,25a．．．作用面12a, 25a. . . Action surface
12b,25b．．．非作用面12b, 25b. . . Non-active surface
121,251．．．電極墊121,251. . . Electrode pad
13,34．．．黏著材13,34. . . Adhesive
14,26,36．．．介電層14,26,36. . . Dielectric layer
141．．．盲孔141. . . Blind hole
15,23,33．．．線路層15,23,33. . . Circuit layer
16．．．導電盲孔16. . . Conductive blind hole
20,30．．．承載板20,30. . . Carrier board
21a．．．第一金屬層21a. . . First metal layer
21b．．．電鍍金屬層21b. . . Plating metal layer
21c,32．．．電鍍焊錫21c, 32. . . Electroplated solder
210．．．電性連接凹槽210. . . Electrical connection groove
22．．．阻層twenty two. . . Resistance layer
231,331．．．電性接觸墊231,331. . . Electrical contact pad
27．．．第二金屬層27. . . Second metal layer
29,39．．．第一防焊層29,39. . . First solder mask
29’,39’．．．第二防焊層29’, 39’. . . Second solder mask
290,390．．．開孔290,390. . . Opening
31．．．基板31. . . Substrate
310a．．．電性連接墊310a. . . Electrical connection pad
310．．．導通孔310. . . Via
37．．．熱固材37. . . Hot solid material
38．．．焊球38. . . Solder ball
420．．．開口區420. . . Open area
e．．．偏移e. . . Offset
第1A至1D圖係為習知封裝結構之製法之剖面示意圖；1A to 1D are schematic cross-sectional views showing a method of manufacturing a conventional package structure;
第2A至2I圖係為本發明之封裝結構之製法之第一實施例之剖面示意圖；2A to 2I are schematic cross-sectional views showing a first embodiment of a method for fabricating a package structure of the present invention;
第3A至3F圖係為本發明之封裝結構之製法之第二實施例之剖面示意圖；3A to 3F are schematic cross-sectional views showing a second embodiment of the manufacturing method of the package structure of the present invention;
第4A至4C圖係為本發明之封裝結構之導通孔的不同態樣之剖面示意圖；以及4A to 4C are schematic cross-sectional views showing different aspects of the via holes of the package structure of the present invention;
第5A至5C圖係為本發明之封裝結構之製法之第三實施例之剖面示意圖。5A to 5C are schematic cross-sectional views showing a third embodiment of the method of fabricating the package structure of the present invention.
31．．．基板31. . . Substrate
31a．．．第一表面31a. . . First surface
31b．．．第二表面31b. . . Second surface
310．．．導通孔310. . . Via
310a．．．電性連接墊310a. . . Electrical connection pad
32．．．電鍍焊錫32. . . Electroplated solder
33．．．線路層33. . . Circuit layer
331．．．電性接觸墊331. . . Electrical contact pad
25．．．半導體晶片25. . . Semiconductor wafer
25a．．．作用面25a. . . Action surface
25b．．．非作用面25b. . . Non-active surface
251．．．電極墊251. . . Electrode pad
36．．．介電層36. . . Dielectric layer
Claims (32)
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| TW098103463A TWI416677B (en) | 2009-02-04 | 2009-02-04 | Package structure and manufacturing method thereof |
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| TW098103463A TWI416677B (en) | 2009-02-04 | 2009-02-04 | Package structure and manufacturing method thereof |
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| TWI416677B true TWI416677B (en) | 2013-11-21 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5758413A (en) * | 1995-09-25 | 1998-06-02 | International Business Machines Corporation | Method of manufacturing a multiple layer circuit board die carrier with fine dimension stacked vias |
| US20050284655A1 (en) * | 2004-06-29 | 2005-12-29 | Phoenix Precision Technology Corporation | Circuit board with asymmetrical structure and method for fabricating the same |
| US20070281464A1 (en) * | 2006-06-01 | 2007-12-06 | Shih-Ping Hsu | Multi-layer circuit board with fine pitches and fabricating method thereof |
| US20080230886A1 (en) * | 2007-03-23 | 2008-09-25 | Phoenix Precision Technology Corporation | Stacked package module |
| US20080246135A1 (en) * | 2007-04-04 | 2008-10-09 | Phoenix Precision Technology Corporation | Stacked package module |
-
2009
- 2009-02-04 TW TW098103463A patent/TWI416677B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5758413A (en) * | 1995-09-25 | 1998-06-02 | International Business Machines Corporation | Method of manufacturing a multiple layer circuit board die carrier with fine dimension stacked vias |
| US20050284655A1 (en) * | 2004-06-29 | 2005-12-29 | Phoenix Precision Technology Corporation | Circuit board with asymmetrical structure and method for fabricating the same |
| US20070281464A1 (en) * | 2006-06-01 | 2007-12-06 | Shih-Ping Hsu | Multi-layer circuit board with fine pitches and fabricating method thereof |
| US20080230886A1 (en) * | 2007-03-23 | 2008-09-25 | Phoenix Precision Technology Corporation | Stacked package module |
| US20080246135A1 (en) * | 2007-04-04 | 2008-10-09 | Phoenix Precision Technology Corporation | Stacked package module |
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