TWI413958B - Driving circuit and driving method of active matrix display device, and active matrix display device - Google Patents

Abstract

The purpose of this invention is providing a driving circuit of the source rectangular display device which is unevenly displayed and hard to be aware under the situation of having autoecious capacitance among the pixels, a driving method and a source rectangular display device. The invention is a driving method for the rectangular display device. The rectangular display device has two pixels for distributing a signal line, clamping the common signal line of the two adjacent pixels, which is connected to the different scanning line via the switch component. The method comprises: a first driving step, which orderly selects two scanning signal lines corresponding to two pixels of different signal lines; and a second driving step, which enable the selecting order of the two scanning lines reverses to the first driving step.

Description

Driving circuit, driving method and active matrix type display device of active matrix display device

The present invention relates to a driving circuit and a driving method of an active matrix type display device of a type shared by two pixels adjacent to one signal line, and an active matrix type display device using the same.

In recent years, an active matrix display device using a thin film transistor (TFT) as a switching element has been developed.

The active matrix display device has a scanning line driving circuit (hereinafter referred to as a gate driver) that generates scanning signals for sequentially scanning a plurality of pixels arranged in a matrix. The operating frequency of the gate driver is lower than a signal line driver circuit (hereinafter referred to as a source driver) that imparts a video signal to each of the pixels described above. Therefore, even if the TFT and the gate driver described above are simultaneously formed in the same steps as those for forming the TFT corresponding to each of the foregoing pixels, the gate driver can satisfy the specifications.

Further, each pixel in the active matrix display device has a pixel electrode connected to the TFT and a common electrode to which the common voltage Vcom is applied. Then, in order to prevent the liquid crystal from being deteriorated by applying the electric field in one direction for a long time, the polarity of the image signal Vsig from the source driver is generally performed for each frame and each of the common voltage Vcom. Inverted drive of the line or each point inversion.

Further, in the mounting of the active matrix display device, the gate driver, the source driver, and the like are disposed around a display panel (display screen) in which a plurality of pixels are arranged. Then, it is used to electrically connect the scanning lines (hereinafter referred to as gate lines) and signal lines (hereinafter referred to as source lines) in the display screen with The wirings of the gate driver and the source driver are connected to the outside of the display screen. At this time, from the viewpoint of miniaturization of the information device in which the active matrix display device is assembled, it is strongly required to reduce the surrounding area of the wiring, that is, to reduce the area (narrow edge) other than the display panel.

Therefore, in particular, for the narrow edge of the display panel in the lower direction, since the area occupied by the source line can be reduced, the configuration of the pixel wiring in which the number of source lines is halved is considered (for example, Japanese Patent Laid-Open Publication No. 2004-185006) Figure 5).

Fig. 19 is a schematic view showing an example of pixel wiring in a display screen in order to achieve such a narrow edge. This is shared by two pixels 200 adjacent to one source line. At this time, the TFTs 202 of the two pixels 200 are respectively connected to different gate lines. As shown in Fig. 19, the TFT 202 of the red (R) pixel 200 at the upper left is connected to the gate line G1 and the source line S1, and the TFT 202 of the pixel 200 of the right adjacent green (G) is connected to the gate line G2. With the source line S1.

Fig. 20 is a view showing the output sequence of the combination of the image signal Vsig outputted to the plurality of source lines S1, S2, S3, ... in accordance with the information to be displayed in the pixel wiring, and the complex gate lines G1, G2, A timing chart composed of the selection order of G3, . As shown in the figure, since the gate line is twice the number of pixel rows, the complex gate lines G1, G2, G3, ... select one gate line every 1/2 horizontal period (1/2H) in order. (Formation of H signal). Then, the combination of the image signals Vsig corresponding to the pixels 200 of the selected gate line thereof is respectively written, and output to the plurality of source lines S1, S2, S3, ... at a time during 1/2 horizontal period. If the 1/2 level period of the gate line G1 is selected, the combination of the image signal Vsig which becomes "S-1" is output to the complex source. Lines S1, S2, S3, ..., and secondly, in the 1/2 horizontal period of the selection gate line G2, the combination of the image signals Vsig which becomes "S-2" is output to the complex source lines S1, S2, S3, …Case.

Fig. 21 is a sequence diagram showing the writing of the image signal Vsig in each pixel 200. In the pixel wiring described above, the video signal Vsig is written to each of the pixels 200, and as shown in Fig. 20, since it is executed in the order in which the gate lines are arranged, it is as shown in Fig. 21.

The pixel wiring for halving the number of the source lines described above includes a portion of the source line and a portion of the passive line between the pixels. In the portion of the passive line, the parasitic capacitance between the pixels is more active than The part of the polar line is large. Figure 22 shows the equivalent circuit diagram at this time. A drain voltage is generated between the pixels in which the inter-pixel parasitic capacitance 204 exists, whereby the potential of the previously written pixel 200 is changed by the potential of the pixel 200 to be written later. This change in potential appears as a display that is not uniform on the screen. As shown in Fig. 21, since the pixel writing order is fixed, the display caused by the leakage is not uniform and always occurs at the same portion.

Fig. 23 is a diagram showing an example in which the display is not uniform. For the sake of easy understanding, this figure is displayed only for the pixels 200 of G. Here, the scanning order of the gate line is G1→G2→G3→. . . →G8. Further, in Fig. 23, in the pixel 200 of other colors which are blackened, the potential of the previously written pixel 200 changes (details will be described later).

Hereinafter, the pixel potential variation will be described in more detail. Fig. 24 is a view showing the configuration of each pixel when the display panel is a TFTLCD. Each of the pixels 200 is sandwiched between a pixel electrode connected to the source line via the TFT 202 connected to the gate line, and a common electrode (not shown) to which the common voltage Vcom is applied. It is composed of a liquid crystal (not shown). Then, by holding the electric charge in the liquid crystal capacitor Clc for the duration of the field (the period of the frame in the non-interlaced manner), the corresponding display is realized. In order to take measures against the liquid crystal capacitor Clc and the leakage current through the TFT, the storage capacitor Cs is provided in parallel with the liquid crystal capacitor Clc.

Fig. 25A is a scanning timing chart showing the gate driver G1 to G4 of the gate driver in Fig. 24, and Fig. 25B shows the 1/2 voltage period (1/2H) for performing the common voltage Vcom. When the horizontal line inversion of the polarity inversion is driven, the green pixel (hereinafter referred to as the pixel before G) connected to the source line S3 of the 22nd image previously written and the source of the 22nd picture connected to the subsequent write are connected. A pixel potential waveform diagram of a red pixel of the epipolar line S2 (hereinafter referred to as a pixel after R).

Hereinafter, the case where the voltage applied to the pixel is larger and the transmittance is lowered (darkened) in the normal white mode liquid crystal display device will be described. Further, Fig. 25B shows that the amplitude of the common voltage Vcom is 5.0 V, the write voltage of the pixel F before the G (image signal Vsig), the common voltage Vcom is 2.0 V (middle tone), and the writing of the pixel L after R The input voltage (image signal Vsig) is a case where the common voltage Vcom is 4.0 V (black, dark). Further, since the influence of the traction voltage (feedthrough voltage) ΔV which occurs when the TFT 202 is turned from on to off can be eliminated by adjusting the common voltage Vcom (shifting Vcom downward by ΔV portion), it is not described in In the waveform of Fig. 25B (the same applies to the other pixel potential waveforms described below).

When a period for writing a video signal to a pixel of one line of the display screen is one horizontal period, as shown in FIG. 25A, two gate lines are sequentially selected in one horizontal period. In other words, when the period in which one gate line is selected is one scanning period, one horizontal period corresponds to two scanning periods (one scanning period corresponds to the above-described 1/2 horizontal period). Then, the two gate lines selected during one horizontal period are sequentially switched during each horizontal period in each field. At this time, as shown in FIG. 25B, the TFT 202 connected to the selected gate line is turned on, and the image signal Vsig applied from the source line to the corresponding pixel 200 is written. Therefore, the writing timing of the pixel F before G is W _{G in} FIG. 25B, and the writing timing of the pixel L after _R becomes W _R . The pixel potential written by this write timing is maintained until it is overwritten in the next field.

Fig. 25B is a waveform of a pixel potential in an ideal state when the parasitic capacitance 204 between pixels is 0. However, as described above, the inter-pixel parasitic capacitance 204 exists in the portion of the passive electrode line. Fig. 26A is a diagram showing a pixel potential waveform under the same voltage condition as that of Fig. 25B when the parasitic capacitance 204 between pixels is considered. In addition, FIG. 26B shows that the amplitude of the common voltage Vcom when considering the parasitic capacitance 204 between pixels is 5.0 V, and the writing voltage of the pixel F before G is 2.0 v for the common voltage Vcom, and the writing of the pixel L after R The pixel potential waveform when the voltage vs. common voltage Vcom is 1.0V (white, bright).

That is, as shown in FIG. 26A and FIG. 26B, in the pixel F before G, the pixel potential written by selecting the gate line G1 is written after the gate line G2 is selected and R is written. In the case of the pixel L, the Vc portion is shifted in the direction away from the common voltage Vcom (the direction in which it is darkened). The magnitude of this Vc is expressed as follows: Vc = (Vsig (Fn - 1) + Vsig (Fn)) × Cpp / (Cs + Clc + Cpp) × α... (1)

In the formula (1), Vsig (Fn) is the write voltage of the pixel L after the current field R, and Vsig (Fn-1) is the write voltage of the pixel L after the R of the previous field. Therefore, in the case of Fig. 26A, Vsig(Fn-1)+Vsig(Fn)=8.0V, and in the case of Fig. 26B, Vsig(Fn-1)+Vsig(Fn)=2.0V. In addition, Cpp is the capacitance value of the parasitic capacitance 204 between pixels, and the capacitance of the Cs is the auxiliary capacitance Cs. The value, Clc is the capacitance value of the liquid crystal capacitor Clc, and the α is a proportional coefficient, and is determined depending on the panel structure and the like.

Thus, the larger Vsig(Fn-1)+Vsig(Fn), the larger the value Vc of the potential variation, regardless of the amplitude of Vcom.

As described above, the horizontal line inversion driving of the polarity of the common voltage Vcom (the polarity of the voltage applied to the liquid crystal) is different between the pixels adjacent to the source line direction. That is, as shown in FIG. 21, between the pixels connected to the gate line G1 or G2, the pixels connected to the gate line G3 or the gate line G4 are connected to the gate of the gate line G5 or the gate line G6. Between the pixels of the gate line G7 or the gate line G8, the polarity of the common voltage Vcom is inverted.

Further, when the polarity of the common voltage Vcom is reversed, there is also a point in which the polarity of the common voltage Vcom is different between pixels adjacent to the source line and pixels adjacent to the direction along the gate line. The drive method of the drive. At this time, the polarity of the common voltage Vcom is reversed between the pixels adjacent to the upper, lower, left, and right, and between the gate line G1 and the gate line G2 of FIG. 21, the gate line G3 and the gate line Between G4, between the gate line G5 and the gate line G6, between the gate line G7 and the gate line G8, the polarity of the common voltage Vcom is reversed.

In addition, regardless of the horizontal line inversion driving or the dot inversion driving, the polarity of the common voltage Vcom in each pixel is inverted every field.

In the case of performing such dot inversion driving, it is shown in FIG. 27A and FIG. 27B. Here, Fig. 27A shows that the amplitude of the common voltage Vcom when considering the parasitic capacitance 204 between pixels is 5.0 V, and the write voltage of the pixel F before G is 2.0 V (middle tone) to the common voltage Vcom, after R a pixel potential waveform when the write voltage of the pixel L is 4.0V (black) to the common voltage Vcom, Fig. 27B shows that the amplitude of the common voltage Vcom when considering the parasitic capacitance 204 between pixels is 5.0v, and the write voltage of the pixel F before G is 2.0V to the common voltage Vcom, and the write voltage of the pixel L after R The pixel potential waveform when the common voltage Vcom is 1.0 V (white).

That is, as shown in FIG. 27A and FIG. 27B, when the dot inversion driving is performed, the gate line G1 is selected in the pixel F before G as in the case of the horizontal line inversion driving. On the other hand, the pixel potential to be written shifts the Vc portion when the pixel L after R is selected by selecting the gate line G2.

At this time, as in the case of the horizontal line inversion driving, the larger the Vsig (Fn-1) + Vsig (Fn) is, the larger the value Vc of the potential fluctuation is, regardless of the amplitude of the Vcom.

However, in the case of the horizontal line inversion driving, the potential difference is increased so that the potential difference from the common voltage Vcom is increased, and when the dot inversion driving is performed, the potential difference is made such that the potential difference from the common voltage Vcom is small.

Therefore, when the voltage is not applied, it is displayed in white. In the normal white mode in which the black is displayed when the voltage is applied, the pixel before G is darker than the actual display when the horizontal line is reversely driven by the variation of the Vc portion as above. . In addition, the dot inversion drive is brighter than when it is actually displayed. Further, since the pixel potential of the pixel after G is written to a normal voltage, when any of the inversion driving is performed as in the case of the G-grating, the green of the light and dark is displayed every other one in the vertical direction.

The same variation of the Vc portion also occurs in the pixel before R and the pixel before B.

Further, the above-described case is not limited to the case where the pixels 200 are arranged in a strip shape, and the same is true when the pixels are arranged in a triangle.

The method disclosed in Japanese Laid-Open Patent Publication No. 2004-185006 does not solve the problem that the parasitic capacitance 204 between the pixels causes a potential variation in the previously written pixels to cause display unevenness.

The present invention has been made in view of the above problems, and an object thereof is to provide a driving circuit, a driving method, and an active matrix display device of an active matrix display device in which display unevenness in the presence of parasitic capacitance between pixels is not easily recognized.

The driving circuit of an active matrix display device according to the present invention is characterized in that the display device is provided with one signal line every two pixels, and the two adjacent pixels sandwiching the signal line share the signal line, and are different in each case. The scanning line is connected via a switching element, and includes a scanning line driving circuit that selects the plurality of scanning lines, and a signal line driving circuit that outputs a signal according to information to be displayed to the complex signal line.

The scanning line driving circuit includes: a first driving unit that sequentially selects two scanning lines, wherein the two scanning lines correspond to two pixels adjacent to each other connected to different signal lines; and a second driving unit, The order of selection of the two scanning lines is performed opposite to the first driving unit.

Further, a driving method of an active matrix display device according to the present invention is characterized in that the display device is provided with one signal line every two pixels, and two adjacent pixels sandwiching the signal line share the signal line, and Different scan lines are connected via a switching element, and have a first driving step of sequentially selecting two scanning lines corresponding to two pixels adjacent to each other connected to different signal lines; and And a second driving step of performing the selection order of the two scan lines opposite to the first driving step.

Further, an active matrix display device according to a preferred aspect of the present invention includes: a display panel in which one signal line is disposed for every two pixels, and two adjacent pixels sandwiching the signal line share the signal line, and The different scanning lines are connected via a switching element; the scanning line driving circuit selects the plurality of scanning lines; and the signal line driving circuit outputs a signal according to the information to be displayed to the plurality of signal lines.

The scanning line driving circuit includes: a first driving unit that sequentially selects two scanning lines, wherein the two scanning lines correspond to two pixels adjacent to each other connected to different signal lines; and a second driving unit, The order of selection of the two scanning lines is performed opposite to the first driving unit.

According to the present invention, even in the case where parasitic capacitance between pixels exists, display unevenness is not easily recognized.

Hereinafter, the best mode for carrying out the invention will be described with reference to the drawings.

In addition, a period for writing a video signal to all pixels is set to one field, and a period for writing a video signal to pixels of one line portion is set to one horizontal period, and is used for one gate. The period in which the pixel of the line portion is written into the video signal is described as one scanning period.

[First embodiment]

Fig. 1 is a schematic configuration view showing the overall configuration of an active matrix display device according to a first embodiment of the present invention, and Fig. 1B is a schematic diagram of pixel wiring of an LCD panel (liquid crystal display panel) in Fig. 1A. Figure.

In other words, the active matrix display device of the present embodiment is a driving circuit 12 for driving and controlling each pixel of the LCD panel 10 by an LCD panel (display panel) 10 having a plurality of pixels, as shown in FIG. A Vcom circuit 14 having a common voltage Vcom is applied to the LCD panel 10.

As shown in FIG. 1B, the LCD panel 10 has a plurality of pixels arranged in a matrix. The plurality of source lines (signal lines) S1 to S480 and the complex gate lines (scan lines) G1 to G480 are arranged to cross each other. Then, each pixel is connected to one of the source lines and one of the gate lines via the TFT 18 as a switching element. Here, each pixel is disposed so as to be shared by two pixels 16 adjacent to one source line. At this time, the respective TFTs 18 corresponding to the two pixels 16 are connected to gate lines different from each other. As shown in FIG. 1B, the TFT 18 of the pixel 16 of the upper left R is connected to the gate line G1 and the source line S1, and the TFT 18 of the pixel 16 of the right G is connected to the gate line G2 and the source line S1. Further, here, the display pixels 16 are arranged side by side in a strip shape, and the pixels of the odd-numbered columns are connected to the gate lines of the odd-numbered items, and the pixels of the even-numbered columns are connected to the gate lines of the even-numbered items.

The plurality of source lines S1 to S480 and the plurality of gate lines G1 to G480 of the LCD panel 10 are electrically connected to the drive circuit 12 by wirings 20 that surround the substrate (not shown) of the LCD panel 10.

Fig. 2 is a block diagram of the drive circuit 12 in Fig. 1A. As shown in the figure, the driving circuit 12 is composed of a gate driver block (scanning line driving circuit) 22, a source driver block (signal line driving circuit) 24, a level shift circuit 26, and a timing generator (hereinafter referred to as It is composed of a TG) logic circuit 28, a Gamma (hereinafter abbreviated as γ) circuit block 30, a charge pump/regulator block 32, an analog block 34, and other blocks.

Here, the gate driver block 22 selects the plurality of gate lines G1 G G480 of the LCD panel 10 , and the source driver block 24 outputs the image signal Vsig according to the information to be displayed to the plurality of source lines of the LCD panel 10 . S1 ~ S480.

The level shift circuit 26 shifts the level of the signal supplied from the outside to a specific level. The TG portion logic circuit 28 generates a desired timing signal and a control signal based on a signal shifted to a specific level by the level shift circuit 26 and a signal supplied from the outside, and is supplied to each of the driving circuit 12 .

The gamma circuit block 30 is for performing gamma correction so that the image signal Vsig outputted from the source driver block 24 forms a good tone characteristic.

The charge pump/regulator block 32 is a variety of voltages that generate the desired logic level from an external power source, and the analog block 34 is a voltage that is further generated from the voltage generated by the charge pump/regulator block 32. The aforementioned Vcom circuit 14 generates the aforementioned common voltage Vcom from the voltage VVCOM generated by the analog block 34. Since the other blocks are not directly related to the present invention, the description thereof will be omitted.

Fig. 3 is a view showing the output sequence of the combination of the image signal Vsig according to the information to be displayed and the complex gate lines G1 to G480 of the output of the first embodiment to the plurality of source lines S1 to S480 (for the sake of simplicity in the figure) A timing chart constructed by taking only the selection order of the gate lines G1 to G8 for display. Further, FIGS. 4A and 4B show a sequence diagram in which the image signal Vsig is written in each pixel 16. Here, Figure 4A shows, on an expedient, the first field (odd field) and Figure 4B shows the second field (even field) (the first field and the second field can also be replaced).

In the present embodiment, as shown in Fig. 3, the order of selection of the plurality of gate lines G1 to G480 is changed for each field.

That is, the first field (1st field) is the same as before, and the gate driver block 22 performs the first driving, and sequentially selects ( becomes the H signal) for every 1/2 horizontal period (1/2H) according to the arrangement order thereof. The gate line G1~G480. Then, the source driver block 24 will respectively write a combination of the image signals Vsig corresponding to the pixels 16 of the selected gate line, and output to the plurality of source lines S1 to S480 at a time during 1/2 horizontal periods. If the 1/2 horizontal period of the gate line G1 is selected, the combination of the image signals Vsig belonging to "S1-1" is output to the source lines S1 to S480 of the complex number, and secondly, the gate line G2 is selected. In the 1/2 horizontal period, a combination of the video signals Vsig belonging to "S1-2" is output to the plurality of source lines S1 to S480.

In other words, the source driver block 24 corresponds to the selection order of the gate lines in each group of the two gate lines distinguished from each other on the upper side (after selecting the gate line of the odd-numbered term, the gate of the even-numbered term is selected Line), and in one horizontal period, is output in the order of the data corresponding to the pixels of the odd column → the data corresponding to the pixels of the even column.

Therefore, since the first field is in the pixel wiring in which the number of source lines is halved, as shown in FIG. 3, the image signal Vsig is written to each pixel 16 in the order in which the gate lines are arranged, so that Figure 4A shows. Thereby, a drain voltage is generated between the pixels in which the parasitic capacitance 204 between the pixels of the passive polar line portion exists, and the potential of the previously written pixel 16 is changed by the potential of the pixel 16 to be written later.

In addition, as shown in FIG. 3, the gate driver block 22 performs two adjacent configurations corresponding to the connection with different source lines. The selection of the two gate line groups of the pixel 16 is the second drive opposite to the first field. That is, the gate lines G1 and G2 in the reverse order of the first field are first connected to the two gate lines G1 and G2 of the two pixels 16 adjacently arranged to be connected to different source lines. The order is selected, and secondly, the two gate lines G3 and G4 of the two pixels 16 adjacently arranged to be connected to different source lines are connected in accordance with the gate line G4 and the gate in the reverse order of the first field. The order of the line G3 is selected in such a manner that the selection order is replaced in each of the two gate line groups. Then, while the selection order of the gate lines is replaced, the source driver block 24, in response to its selection order, should respectively write a combination of the image signals Vsig corresponding to the pixels 16 of the selected gate line thereof, at 1 /2 horizontal periods are output to the source lines S1 to S480 at a time.

In other words, the source driver block 24 corresponds to the selection order of the gate lines in each group of the two gate lines distinguished from each other on the upper side (after selecting the gate line of the even-numbered term, the gate of the odd-numbered term is selected Line), and in one horizontal period, is output in the order of the data corresponding to the pixels of the even columns → the data corresponding to the pixels of the odd columns.

Thereby, as in the first field, the image signal Vsig with "S1-1" → "S1-2" → "S1-3" → "S1-4" → "S1-5" → "S1-6" → ... The combined sequence is output, and the second field is the image signal of "S1-2" → "S1-1" → "S1-4" → "S1-3" → "S1-6" → "S1-5" →... Vsig's combined sequential output.

Therefore, since the second field is in the pixel wiring in which the number of source lines is halved as described above, as shown in FIG. 3, 2 of the two pixels 16 adjacently arranged corresponding to the source lines connected to different sources are provided. The order in which the gate gates are selected in the reverse order is performed by writing the image signal Vsig to each pixel 16, thus becoming the first The one shown in Figure 4B. Thereby, in the second field, a drain voltage occurs between pixels in the parasitic capacitance 204 between the pixels of the passive polar line portion, and the potential of the previously written pixel 16 is changed by the potential of the pixel 16 to be written later. .

However, the pixel 16 whose potential changes in the second field is different from the pixel 16 whose potential changes in the first field. That is, since the writing order of the image signal Vsig is opposite to the first field in the second field, the writing order of the adjacent pixels 16 is replaced in the first field and the second field. Therefore, the pixel position at which the potential difference occurs in the first field and the second field is opposite, and as a result, the deviation of the pixel potential is temporally averaged, and the display unevenness is alleviated.

Fig. 5 is a view showing a specific configuration of a gate driver block 22 for performing the aforementioned driving. In addition, in order to simplify the description and illustration, eight gate lines will be described here. At this time, the gate driver block 22 is composed of a 3-bit counter 36, 32 AND gates 38-100, 4 NOT gates 102-108, and 8 OR gates 110-124 (in addition, logic here) The risk countermeasures generated when the input of the circuit is switched at the same time are not important, and therefore are not described for the sake of simplicity. The same applies hereinafter.

That is, the gate clock and the up/down (hereinafter abbreviated as U/D) signals are supplied from the TG section logic circuit 28 in the 3-bit counter counter 36. The U/D signal system is normally displayed as "1" when the shift is not reversed, and becomes "0" when the up-and-down reverse shift is displayed. When the shift is not reversed and the vertical shift is reversed, the scanning direction of the gate line is reversed upside down. As a result, the previously written pixel is opposite to the pixel to be written later, so it is necessary to switch the operation in response to the shift.

Then, the weight for resetting the count value of the 3-bit counter 36 is released. After setting the timing of the signal, the 3-bit counter 36 starts counting in response to the gate clock and the up/down signal.

The Q1 output of the 3-bit counter 36 is supplied to the decoded even-numbered lines X2, X4, X6, X8 for the AND gates 40, 44, 48, 52, and is supplied to the decoded odd-numbered items via the NOT gate 102. Lines X1, X3, X5, X7 are used for AND gates 38, 42, 46, 50. Further, the Q2 output of the aforementioned 3-bit counter 36 is supplied to the aforementioned gates X3, X4, X7, X8 for the AND gates 42, 44, 50, 52, and is supplied to the aforementioned lines X1, X2, X5 via the NOT gate 104, The X6 uses the AND gates 38, 40, 46, 48. Then, the Q3 output of the aforementioned 3-bit counter 36 is supplied to the aforementioned lines X5, X6, X7, X8 for the AND gates 46, 48, 50, 52, and is supplied to the aforementioned lines X1, X2, X3 via the NOT gate 106, The X4 uses the AND gates 38, 40, 42, 44.

The output of the AND gate 38 for the aforementioned line X1 is supplied to the gate line G1, and the second AND gate 54, 56 is used for G2. In the first AND gate 54 for the gate line G1, a field switching (hereinafter abbreviated as FI) signal is supplied from the TG portion logic circuit 28, and the gate line G2 is supplied to the gate electrode G2 via the NOT gate 108. FI signal.

The output of the AND gate 40 for the line X2 is supplied to the gate line G1, and the second AND gates 58, 60 are used for G2. In the second AND gates 58, 60 of the gate lines G1, G2, the gate lines G1, G2 are opposite to the first AND gates 54, 56, and the gate gates G1 are used in the second AND gates 58. The FI signal is supplied via the NOT gate 108, and the FI signal is supplied to the gate gate G2 by the second AND gate 60.

Then, the gate line G1 is supplied to the gate line G1 by the output of the first AND gate 54 and the gate line G1 by the output of the second AND gate 58. The OR gate 110, the gate line G1 uses the output of the OR gate 110, and passes through the gate line G1 controlled by the gate enable signal from the TG portion logic circuit 28 for allowing the gate output at a specific timing. The three AND gates 86 are supplied to the gate line G1. Further, the gate line G2 is supplied to the output of the second AND gate 60 by the output of the first AND gate G2, and is supplied to the OR gate 112 for the gate line G2, and the gate gate G2 is gated by the OR gate 112. The output of the gate line G2 controlled by the gate enable signal is supplied to the gate line G2 by the third AND gate 88.

Hereinafter, in the same manner, the output of the line X3, X5, and the AND gates 42, 46, 50 for X7 is given to the gate line G3, and the G4 is used for the first AND gate 62, 64, the gate line G5, and the G6. An AND gate 70, 72, gate line G7, G8 for the first AND gate 78, 80, the gate line G3, G5, G7 for the first AND gate 62, 70, 78 to supply the aforementioned FI signal, the aforementioned The gate line G4 is used for G6, and the G8 first AND gates 64, 72, and 80 are supplied with the aforementioned FI signal via the NOT gate 108. Further, the aforementioned line X4 is used for X6, the output 44, 48, 52 of the AND gate for X8 is applied to the gate line G3, the second AND gate 66, 68 for G4, the gate line G5, and the second AND gate 74 for G6. 76, the gate line G7, G8 is used for the second AND gate 82, 84, the gate line G3 is used for G5, and the G7 is used for the second AND gate 66, 74, 82, and the aforementioned FI is supplied via the NOT gate 108. The signal is used for the gate line G4, G6, and the G8 is supplied with the FI signal by the second AND gates 68, 76, 84. Then, the gate line G3 is used for G5, G7 is used for the output of the first AND gate 62, 70, 78, and the gate line G3 is used for G5, and the output of the second AND gate 66, 74, 82 is used for G7. , for the gate line G3, G5, G7 with the OR gate 114, 118, 122, the gate line G3, G5, G7 with the output of the OR gate 114, 118, 122, through the gate enable The signal-controlled gate line G3 is used for G5, and the G7 is supplied to the gate lines G3, G5, and G7 by the third AND gates 90, 94, and 98. In addition, the gate line G4 is used for G6, the G8 is used for the output of the first AND gates 64, 72, 80, and the gate line G4 is used for G6, and the output of the second AND gates 68, 76, 84 is used for G8. For supply to gate line G4, G6, G8 for OR gates 116, 120, 124, for gate line G4, for G6, G8 for output of OR gates 116, 120, 124, for gate line controlled by the gate enable signal For G4, G6, G8 is supplied to gate lines G3, G5, G7 with the third AND gate 92, 96, 100.

Fig. 6A is a timing chart showing the first field of the gate driver block 22 thus constructed, which is not inverted, and Fig. 6B is a timing chart showing the second field.

When the shift is not reversed, the first field is as shown in FIG. 6A, and in the lines X1 to X8, the H signal is output in order in a period corresponding to one gate clock portion. That is, the line X1 is selected in a time series (H signal) → the line X2 is selected → the line X3 is selected → the line X4 is selected → the line X5 is selected → the line X6 is selected → the line X7 is Select state → line X8 is the selected state.

Here, the first field supplies an H signal as the aforementioned FI signal. Therefore, while the line X1 is in the selected state, only the gate line G1 is selected by the first AND gate 54, and the third gate is used by the G1 OR gate 110 and the gate line G1 controlled by the gate enable signal. Gate 86, and gate line G1 becomes the selected state. Further, while the line X2 is in the selected state, only the gate line G2 is in the selected state by the second AND gate 60, and the third AND gate is controlled by the G2 OR gate 112 and the gate line G2 controlled by the gate enable signal. Gate 88, and gate line G2 is selected. Hereinafter, similarly, The gate lines G3 to G8 are sequentially selected.

Then, when the second field is reached, as shown in FIG. 6B, in the lines X1 to X8, in the same manner as the first field, according to the line X1 → line X2 → line X3 → line X4 → line X5 → line X6 → line X7 → The order of line X8 becomes the selected state.

Here, the L signal is supplied as the aforementioned FI signal in the second field system. Therefore, while the line X1 is in the selected state, only the gate line G2 is in the selected state by the first AND gate 56, and the third gate is used by the G2 OR gate 112 and the gate line G2 controlled by the gate enable signal. Gate 88, and gate line G2 is selected. Further, while the line X2 is in the selected state, only the gate line G1 is in the selected state by the second AND gate 58, and the gate gate G1 controlled by the gate gate G1 and the third gate are controlled by the gate gate G1. Gate 86, and gate line G1 becomes the selected state. In the same manner, the gate line G4 → gate line G3 → gate line G6 → gate line G5 → gate line G8 → gate line G7 are selected in the same manner.

In addition, FIG. 7A shows a timing chart of the first field when the gate driver block 22 constructed in FIG. 5 is shifted up and down, and FIG. 7B shows the timing chart of the second field (in addition, up and down When the bit is transferred, the reset signal is earlier than the 6th and 6B pictures, and the 1st gate clock phase is decreased. Further, FIGS. 8A and 8B show a sequence diagram in which the video signal Vsig is written in each pixel 16 when the up-and-down reverse shift is performed. Here, Fig. 8A shows the first field, and Fig. 8B shows the second field.

When the up-and-down reverse shift is performed, as shown in FIG. 7A, in the first field line X1 to X8, the H signal is output in the reverse direction in the opposite direction during the period corresponding to one gate clock portion. That is, the line X8 is selected in a timed manner → the line X7 is selected → the line X6 is selected → the line X5 To select the state → line X4 is the selected state → line X3 is the selected state → line X2 is the selected state → line X1 is the selected state.

Here, the first field supplies an H signal as the aforementioned FI signal. Therefore, while the line X8 is in the selected state, only the gate line G8 is selected by the second AND gate 84, and the gate gate G8 controlled by the G8 and the gate line G8 controlled by the gate enable signal are used for the third AND. Gate 100, and gate line G8 is selected. Further, while the line X7 is in the selected state, only the gate line G7 is selected by the first AND gate 78, and the third AND gate is controlled by the G gate OR gate 122 and the gate line G7 controlled by the gate enable signal. Gate 98, and gate line G7 becomes the selected state. Hereinafter, similarly, the gate lines G6 to G1 are sequentially selected.

Therefore, since the video signal Vsig is written to each of the pixels 16 in the first field, as shown in FIG. 7A, the order is performed in the reverse direction of the gate lines, so that it is shown in FIG. 8A. Thereby, a drain voltage is generated between the pixels in which the inter-pixel parasitic capacitance 204 exists in the portion of the passive electrode line, and the potential of the previously written pixel 16 is changed by the potential of the pixel 16 to be written later.

Then, when the second field is reached, as shown in Fig. 7B, in the lines X1 to X8, in the same manner as the first field, according to the line X8 → line X7 → line X6 → line X5 → line X4 → line X3 → line X2 → The order of line X1 becomes the selected state.

Here, the L signal is supplied as the aforementioned FI signal in the second field system. Therefore, while the line X8 is in the selected state, only the gate line G7 is in the selected state by the second AND gate 82, and the third AND gate is controlled by the G gate OR gate 122 and the gate line G7 controlled by the gate enable signal. Gate 98, and gate line G7 becomes the selected state. Further, while the line X7 is in the selected state, only the gate line G8 is in the selected state by the first AND gate 80. The third AND gate 100 is used for the G8 OR gate 124 and the gate line G8 controlled by the gate enable signal, and the gate line G8 is selected. In the same manner, the gate line G5 → gate line G6 → gate line G3 → gate line G4 → gate line G1 → gate line G2 are selected in the same manner.

Therefore, in the pixel field in which the number of source lines is halved in the second field, as shown in FIG. 7B, since the image signal Vsig is written to each pixel 16 to be adjacently arranged in connection with the connection with different source lines. Since the selection of the two gate lines of the two pixels 16 is performed in the reverse order of the opposite order, it is shown in Fig. 8B. Thereby, in the second field, a drain voltage occurs between the pixels in which the inter-pixel parasitic capacitance 204 of the portion of the passive polar line exists, and the potential of the previously written pixel 16 is changed by the potential of the pixel 16 to be written later. .

However, the pixel 16 whose potential changes in the second field is different from the pixel 16 whose potential changes in the first field. That is, since the writing order of the image signal Vsig is opposite to the first field in the second field, the writing order of the adjacent pixels 16 is replaced in the first field and the second field. Therefore, the pixel position at which the potential difference occurs in the first field and the second field is reversed, and as a result, the deviation of the pixel potential is averaged in time, and the display unevenness is alleviated.

As described above, in the first embodiment, when the plurality of gate lines are sequentially selected by the gate driver block 22 for each field replacement, two pixels adjacent to each other are connected adjacent to the source lines. The order of selection of the gate lines can be made uniform by reducing the potential difference of the pixels, thereby reducing display inhomogeneity.

Then, as the second field is as shown in FIG. 3, the data order of the odd-numbered columns and the even-numbered columns is replaced by the replacement of the gate lines, and the output is output. According to the combination of the video signal Vsig outputted from the source driver block 24 to the above-mentioned complex source line, the display can be performed without confusion. In addition, in the change of the output order of the combination of the image signals Vsig in the second field, the TG portion logic circuit 28 may also maintain a combination of the image signals Vsig of at least one line portion, replacing the data order of the odd columns and the even columns. The data is supplied to the source driver block 24, or the data order of the odd-numbered columns and the even-numbered columns may be replaced in the source driver block 24, or the side of the image signal may be supplied to the active matrix type display device. In the second field, the data of the odd-numbered columns and the even-numbered columns of the image signal are replaced and supplied (this is basically the same as the operation performed when the up-and-down reverse shift is performed), but the detailed circuit configuration is not particularly illustrated.

(When the up-and-down reverse shift is performed, the field memory is required, but when the up-and-down reverse shift is not performed, the line memory can be realized).

[Modification]

In the first embodiment, the order of the two gate lines corresponding to the two pixels adjacent to each other connected to the different source lines is sequentially selected for each field switching, but as shown in FIG. Switch every 2 gate lines (per 1H period, in other words, 2 scan periods).

Thus, since the video signal Vsig is written to each of the pixels 16, the first field is in the order shown in FIG. 10A, and the second field is in the order shown in FIG. 10B. Therefore, even pixels affected by the parasitic capacitance are in the same In the field, because the longitudinal direction is inconsistent, the vertical stripes can be avoided.

An example of a circuit for realizing such a drive is shown in FIG. It is the same except that the mutual exclusion or (XOR) gate 126 is added in Fig. 5, and the FI signal and the Q2 signal are input, and the FI' signal is output instead of the FI signal.

The circuit operation of Fig. 11 when the shift is not reversed is shown in Fig. 12A and Fig. 12B.

The operation of the circuit in Fig. 11 is shown in Fig. 13A and Fig. 13B (in addition, when the up-and-down reverse shift is performed, the reset signal is one gate earlier than the 12A and 12B). The pulse is partially reduced).

A more suitable example of this circuit is the order of selection of the gate lines for every two gate lines (per 1H period, in other words, every 2 scan periods).

This drive can be implemented by implementing a simple change in the gate driver block of Figure 5.

Further, this can also be applied to the LCD panel 10 in which the pixel and the TFT are wired as shown in Fig. 14.

At this time, the gate lines are sequentially selected in the order shown in FIGS. 15A and 15B. In the case of the pixel wiring of Fig. 14, the example of the circuit for realizing the driving can be used in the fifth drawing. The circuit example shown in FIG. 5 is suitable for the gate of the active matrix display device in which each pixel column corresponds to one source line and each pixel row corresponds to one gate line. Extreme drive.

As described above, since the present modification performs such driving, even if the vertical stripes themselves are staggered stripes in the same field, the effect of the vertical stripes itself is not easily seen.

In addition, here is a more suitable example of the selection order of switching the gate lines per field. However, even if the method of selecting the order of the gate lines is not in each field, the vertical stripes themselves are interlaced. Stripes, so it is difficult to see the effect of the vertical stripes themselves. In this case, it is only necessary to fix the FI signal in the circuit of Fig. 11.

In addition, here, every 2 gate lines are switched, but every 2j (j is an integer of 2 or more) gate line (should be shorter).

[Second embodiment]

Next, a second embodiment of the present invention will be described.

In the active matrix display device, in addition to the strip-like arrangement in which the pixels 16 are arranged vertically and horizontally as shown in FIG. 1B, it is also known that a triangular arrangement in which three types of RGB pixels are arranged in a triangular shape is also known.

Fig. 16 is a schematic view showing the pixel wiring of the LCD panel in such a triangular arrangement. The triangular array is not formed as shown in FIG. 1B, and the plurality of source lines S1 to S480 are linearly arranged in a strip shape, and as shown in FIG. 16, the interdigitation is formed between the pixels 16 and The pixels corresponding to the rows of the odd-numbered items and the pixels corresponding to the rows of the even-numbered items are arranged such that the adjacent pixel pitches of the respective column directions are each separated by half.

FIG. 17A is a sequence diagram showing the image signal Vsig written in each pixel 16 in the first field in the second embodiment when the shift is not reversed, and FIG. 17B shows that it is in the second field. A sequence diagram of the video signal Vsig is written in each pixel 16.

In the second embodiment, as shown in Fig. 3, the selection order of the plurality of gate lines G1 to G480 is changed every field.

That is, the first field gate driver block 22 performs the first driving, and the plurality of gate lines G1 G G480 are sequentially selected every 1/2 horizontal periods in this order. Then, the source driver block 24 will respectively write a combination of the image signals Vsig corresponding to the pixels 16 of the selected gate line, and output to the plurality of source lines S1 to S480 at a time during 1/2 horizontal period. Therefore, in this first field, the video signal Vsig is written to each of the pixels 16 and is executed in the order of the gate lines as shown in FIG. 3, so that it is as shown in FIG. 17A. borrow As a result, a drain voltage is generated between pixels in the parasitic capacitance 204 between the portions of the passive line, and the potential of the previously written pixel 16 is changed by the potential of the pixel 16 to be written later.

In addition, in the second field, as shown in FIG. 3, the gate driver block 22 performs a second driving, which will correspond to two gate lines of two pixels 16 adjacent to each other connected to different source lines. The order in which the groups are selected forms the opposite of the first field. Then, while the selection order of the gate lines is replaced, the source driver block 24 will respectively write the combination of the image signals Vsig corresponding to the pixels 16 of the selected gate line in accordance with the selection order thereof, at 1 The /2 horizontal periods are output to the complex source lines S1 to S480 at a time. Therefore, in the second field, the video signal Vsig is written to each of the pixels 16, and as shown in FIG. 3, two gates corresponding to the two pixels 16 arranged adjacent to each other and connected to different source lines are provided. The order in which the selection order of the polar lines is reversed is performed, and therefore, it is shown in Fig. 17B. Thereby, in the second field, a drain voltage occurs between the pixels in which the inter-pixel parasitic capacitance 204 exists in the portion of the passive polar line, and the potential of the previously written pixel 16 is affected by the potential of the pixel 16 to be written later. Variety.

However, the pixel 16 of the second field potential change is different from the pixel 16 of the potential change in the first field. That is, since the writing order of the image signal Vsig is opposite to the first field in the second field, the writing order of the adjacent pixels 16 is replaced in the first field and the second field. Therefore, the pixel position at which the potential difference occurs in the first field and the second field is opposite, and as a result, the deviation of the pixel potential is temporally averaged, and the display unevenness is alleviated.

In addition, FIG. 18A shows that in the first field when the gate driver block 22 constructed in FIG. 5 is shifted upside down, the image is written in each pixel 16. The sequence diagram of No. Vsig, and Fig. 18B shows a sequence diagram in which the image signal Vsig is written in each pixel 16 in the second field when the up-and-down shift is reversed.

When the up-and-down reverse shift is performed, since the video signal Vsig is written to each of the pixels 16 in the first field, as shown in FIG. 7A, the order is reversed in the order of the gate lines, and thus the image shown in FIG. 18A is shown. Thereby, a drain voltage is generated between the pixels in which the parasitic capacitance 204 between the pixels in the passive polar line portion exists, and the potential of the previously written pixel 16 is changed by the potential of the pixel 16 to be written later.

Then, when the second field is reached, since the image signal Vsig is written to each of the pixels 16, as shown in FIG. 7B, two gates of two pixels 16 adjacent to each other are connected to be connected to different source lines. The selection order of the polar lines is performed in the reverse order of the reverse order, and thus becomes as shown in Fig. 18B. Thereby, in the second field, a drain voltage occurs between the pixels in which the inter-pixel parasitic capacitance 204 exists in the portion of the passive polar line, and the potential of the previously written pixel 16 is affected by the potential of the pixel 16 to be written later. Variety.

However, the pixel 16 of the second field potential change is different from the pixel 16 of the potential change in the first field. That is, since the writing order of the image signal Vsig is opposite to the first field in the second field, the writing order of the adjacent pixels 16 is replaced in the first field and the second field. Therefore, the pixel position at which the potential difference occurs in the first field and the second field is opposite, and as a result, the deviation of the pixel potential is temporally averaged, and the display unevenness is alleviated.

As described above, even if the triangular array is used, the same driving as in the first embodiment can be performed, and display unevenness can be reduced in the same manner.

Furthermore, in the case where the pixels 16 are arranged in a triangle shape, the display is not uniform (e.g., corresponding to the case of the strip arrangement of the first embodiment). The vertical stripes in Fig. 16 are meandered, so there is also an effect that is less noticeable than the strip arrangement.

Further, by the driving as shown in the modified example (Fig. 9) of the first embodiment, the formation of the meander is made more complicated, and the vertical stripes can be made more difficult.

The present invention has been described above based on the embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and applications can be made without departing from the scope of the invention.

When the order of writing between adjacent pixels is replaced per field, the order of selection of each of the gate lines G1 to G480 is not limited to the order of the above embodiment.

Further, in the above embodiment, the writing order is switched every one field, but even if switching is performed every two fields (per frame), substantially the same effect can be obtained.

Furthermore, it is also possible to switch every k fields (k is an integer of 3 or more), but it is preferable to have a short period.

Here, the case of the liquid crystal display device of the normal white mode in which the voltage applied to the pixel is increased and the transmittance is lowered (darkened) is also applied. Of course, the higher the voltage applied to the pixel, the higher the transmittance ( The case of a normal black mode liquid crystal display device that is brightened.

In addition, here, the liquid crystal displayed in color is taken as an example, and it is of course also possible to display liquid crystal in monochrome (black and white).

Furthermore, the switching element is not limited to the TFT, and may of course be a diode or the like. Further, the number of gate lines and source lines is of course not limited to the example of Fig. 1.

Further, the pixels of the active matrix display device are not limited to liquid crystals, and in the case of capacitive elements, parasitic capacitance between pixels occurs, so that display unevenness can be similarly reduced by the present invention.

10‧‧‧LCD panel

12‧‧‧Drive circuit

14‧‧‧Vcom circuit

16‧‧‧ pixels

18‧‧‧TFT

20‧‧‧ wiring

22‧‧‧ Gate Driver Block

24‧‧‧Source Driver Block

26‧‧‧bit shift circuit

28‧‧‧ Timing generator part logic

30‧‧‧Gamma Circuit Block

32‧‧‧Charge pump/regulator block

34‧‧‧ analog block

36‧‧‧3 bit counter

38‧‧‧AND gate

40‧‧‧AND gate

42‧‧‧AND gate

44‧‧‧AND gate

46‧‧‧AND gate

48‧‧‧AND gate

50‧‧‧AND gate

52‧‧‧AND gate

54‧‧‧First AND gate

56‧‧‧First AND gate

58‧‧‧Second AND gate

60‧‧‧Second AND gate

62‧‧‧First AND gate

64‧‧‧First AND gate

66‧‧‧Second AND gate

68‧‧‧Second AND gate

70‧‧‧First AND gate

72‧‧‧First AND gate

74‧‧‧Second AND gate

76‧‧‧Second AND gate

78‧‧‧First AND gate

80‧‧‧First AND gate

82‧‧‧Second AND gate

84‧‧‧Second AND gate

86‧‧‧ Third AND gate

88‧‧‧ Third AND gate

90‧‧‧ Third AND gate

92‧‧‧ Third AND gate

94‧‧‧ Third AND gate

96‧‧‧ Third AND gate

98‧‧‧ Third AND gate

100‧‧‧ third AND gate

102‧‧‧NOT gate

104‧‧‧NOT gate

106‧‧‧NOT gate

108‧‧‧NOT gate

110‧‧‧OR gate

112‧‧‧OR gate

114‧‧‧OR gate

116‧‧‧OR gate

118‧‧‧OR gate

120‧‧‧OR gate

122‧‧‧OR gate

124‧‧‧OR gate

200‧‧ ‧ pixels

202‧‧‧TFT

204‧‧‧Parasitic capacitance between pixels

Fig. 1 is a schematic block diagram showing the overall configuration of an active matrix display device according to a first embodiment of the present invention.

Fig. 1B is a schematic view showing the pixel wiring of the LCD panel (display panel) in Fig. 1A.

Fig. 2 is a block diagram showing the driving circuit of Fig. 1A.

Fig. 3 is a timing chart showing an output sequence of a combination of image signals according to information to be displayed and a selection order of a plurality of gate lines, which are output to the complex source line of the first embodiment.

Fig. 4A is a sequence diagram showing the writing of image signals in respective pixels in the first field of the first embodiment.

Fig. 4B is a sequence diagram showing the writing of video signals in each pixel in the second field of the first embodiment.

Fig. 5 is a view showing a specific configuration of a gate driver block of the first embodiment in Fig. 2.

Fig. 6A is a timing chart showing the first field when the gate driver block of Fig. 5 is not inverted.

Fig. 6B is a timing chart showing the second field when the gate driver block of Fig. 5 is not inverted.

Fig. 7A is a timing chart showing the first field when the gate driver block of Fig. 5 is shifted upside down.

Fig. 7B is a timing chart showing the second field when the gate driver block of Fig. 5 is shifted upside down.

Fig. 8A is a sequence diagram showing the writing of a video signal in each pixel in the first field when the first embodiment is vertically shifted up and down.

Fig. 8B is a sequence diagram showing the writing of a video signal in each pixel in the second field in the case where the first embodiment is vertically shifted up and down.

Fig. 9 is a timing chart showing the output sequence of the combination of the video signals to be displayed and the selection order of the complex gate lines, which are output to the complex source line in the modified example of the first embodiment.

Fig. 10A is a sequence diagram showing the writing of a video signal in each pixel in the first field of the modified example of the first embodiment.

Fig. 10B is a sequence diagram showing the writing of a video signal in each pixel in the second field of the modified example of the first embodiment.

Fig. 11 is a view showing a specific configuration of a gate driver block in a modified example of the first embodiment.

Fig. 12A is a timing chart showing the first field when the gate driver block of Fig. 11 is not inverted.

Fig. 12B is a timing chart showing the second field when the gate driver block of Fig. 11 is not inverted.

Fig. 13A is a timing chart showing the first field when the gate driver block of Fig. 11 is shifted upside down.

Fig. 13B is a timing chart showing the second field when the gate driver block of Fig. 11 is shifted upside down.

Fig. 14 is a schematic view showing another pixel wiring of an LCD panel (display panel).

Fig. 15A is a sequence diagram showing the writing of image signals in respective pixels in the first field of the pixel wiring of Fig. 14.

Figure 15B is a sequence diagram showing the writing of image signals in each pixel in the second field of the pixel wiring of Figure 14.

Fig. 16 is a schematic view showing the pixel wiring of the LCD panel of the triangular arrangement according to the second embodiment of the present invention.

Fig. 17A is a sequence diagram showing the writing of image signals in each pixel in the first field in the case where the shift is not reversed in the second embodiment of the present invention.

Fig. 17B is a sequence diagram showing the writing of image signals in each pixel in the second field in the case where the shift is not reversed in the second embodiment of the present invention.

Fig. 18A is a sequence diagram showing the writing of image signals in each pixel in the first field when the shift is reversed in the second embodiment of the present invention.

Fig. 18B is a sequence diagram showing the writing of image signals in each pixel in the second field when the shift is reversed in the second embodiment of the present invention.

Fig. 19 is a schematic view showing the pixel wiring of the display panel in which the previous active matrix type display device halved the number of source lines.

Fig. 20 is a scanning timing chart showing the pixel wiring of Fig. 19.

Fig. 21 is a sequence diagram showing the writing of image signals in respective pixels in the pixel wiring of Fig. 19.

Fig. 22 is an equivalent circuit diagram showing the display panel of Fig. 19.

Fig. 23 is a view showing an example of display unevenness on the display panel of Fig. 19.

Fig. 24 is a view showing the configuration of each pixel when the display panel is a TFTLCD panel.

Fig. 25A shows a scanning timing chart.

Fig. 25B is a diagram showing a pixel potential waveform formed by horizontal line inversion driving without parasitic capacitance between pixels.

Fig. 26A is a graph showing the pixel potential waveform formed by the horizontal line inversion driving in consideration of the parasitic capacitance between pixels, and showing the amplitude of the common voltage as The waveform of the pixel potential when the write voltage of the pixel before 5.0V is 2.0V, and the write voltage of the pixel after R is 4.0V to the common voltage is 5.0V.

Fig. 26B is a waveform diagram showing the pixel potential formed by the horizontal line inversion driving in consideration of the parasitic capacitance between pixels, and shows that the amplitude of the common voltage is 5.0 V, and the write voltage of the pixel before G is 2.0 V for the common voltage, R The pixel potential waveform of the write voltage of the subsequent pixel to the common voltage of 1.0V.

Fig. 27A is a diagram showing a pixel potential waveform formed by dot inversion driving in consideration of parasitic capacitance between pixels, and shows that the amplitude of the common voltage is 5.0 V, and the write voltage of the pixel before G is 2.0 V for the common voltage, after R A pixel potential waveform diagram of a write voltage of a pixel to a common voltage of 4.0V.

Fig. 27B is a waveform diagram showing the pixel potential formed by the dot inversion driving in consideration of the parasitic capacitance between pixels, and shows that the amplitude of the common voltage is 5.0 V, and the writing voltage of the pixel before G is 2.0 V for the common voltage, after R A pixel potential waveform diagram of a write voltage of a pixel to a common voltage of 1.0V.

Claims (11)

A driving circuit for an active matrix display device, wherein the active matrix display device has a plurality of scanning lines, a plurality of signal lines, and a plurality of pixels, and one of the foregoing signal lines is arranged in units of two pixels arranged along a scanning line direction. Two of the pixels adjacent to each other across the signal line share the signal line, and each of the two scanning lines adjacent to each other across one of the pixels is connected via a switching element, and includes a scanning line driving circuit. Selecting the plurality of scanning lines; and a signal line driving circuit for outputting a signal according to information to be displayed to the plurality of signal lines; wherein the scanning line driving circuit is adjacent to the two scanning lines adjacent to the pixel Each of the scanning line groups divides the plurality of scanning lines into a plurality of scanning line groups adjacent to each other, and sequentially selects the scanning line groups in the same order in the first specific period and the second specific period. In the specific period, the two scanning lines of the scanning line groups are selected in the first order, and the second specific period is in the first order with respect to the first order. Conversely the second sequentially selecting each scanning line the two groups of scan lines. The driving circuit of the active matrix display device according to the first aspect of the invention, wherein the first specific period and the second specific period are k fields (k: an integer of 1 or more). The driving circuit of the active matrix display device according to the first aspect of the invention, wherein the signal line driving circuit outputs a signal corresponding to a selection order of the scanning lines by the scanning line driving circuit to the complex signal line. A driving method of an active matrix display device having a plurality of scanning lines, a plurality of signal lines, and a plurality of pixels, wherein one of the aforementioned signal lines is arranged in units of two pixels arranged along a scanning line direction. The two adjacent pixels that sandwich the signal line share the signal line, and are connected to each of the two scanning lines adjacent to each other with one pixel interposed therebetween via a switching element, and the plurality of scanning lines sandwich the aforementioned scanning line The two scanning lines adjacent to each other are divided into a plurality of scanning line groups adjacent to each other as one scanning line group, and the scanning is sequentially selected in the same order in the first specific period and the second specific period. The line group selects the two scanning lines of the scanning line groups in the first order in the first specific period, and selects the scanning lines in the second order in the second specific period opposite to the first order. The above two scan lines of the group. The driving method of the active matrix display device according to the fourth aspect of the invention, wherein the first specific period and the second specific period are k fields (k: an integer of 1 or more). A driving method of an active matrix type display device according to claim 4, wherein the signals to be displayed on the plurality of signal lines are output in accordance with a selection order of the scanning lines. An active matrix display device having: The display panel has a plurality of scanning lines arranged in the column direction, a plurality of signal lines arranged along the row direction, and a plurality of pixels arranged two-dimensionally along the column and the row direction, and two of them are arranged along the column direction. One of the signal lines is arranged in units of the pixels, and the two adjacent pixels that sandwich the signal line share the signal line, and are connected to two scanning lines adjacent to each other with one pixel interposed therebetween via a switching element. a scanning line driving circuit that selects the plurality of scanning lines; and a signal line driving circuit that outputs a signal according to information to be displayed to the plurality of signal lines; the scanning line driving circuit sandwiches the pixels The two adjacent scanning lines are divided into one scanning line group, and the plurality of scanning lines are divided into a plurality of scanning line groups adjacent to each other, and sequentially selected in the same order in the first specific period and the second specific period. Each of the scanning line groups selects the two scanning lines of the scanning line groups in the first order in the first specific period, and in the second specific period, in the first order Instead of selecting the second sequence of the group 2 of each scanning line of scanning lines. The active matrix display device according to claim 7, wherein the first specific period and the second specific period are k fields (k: an integer of 1 or more). The active matrix display device according to claim 7, wherein the signal line driving circuit outputs a signal corresponding to a selection order of the scanning lines by the scanning line driving circuit to the complex signal line. The active matrix type display device of claim 7, wherein the display panel is arranged in a strip-like arrangement of the plurality of pixels. The display panel. The active matrix display device according to claim 7, wherein the display panel is a display panel in which the plurality of pixels are arranged in a triangular triangular arrangement.