TWI410527B - Electroplating apparatus and method for plating conducting layer on substrate - Google Patents

Electroplating apparatus and method for plating conducting layer on substrate Download PDF

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TWI410527B
TWI410527B TW99114478A TW99114478A TWI410527B TW I410527 B TWI410527 B TW I410527B TW 99114478 A TW99114478 A TW 99114478A TW 99114478 A TW99114478 A TW 99114478A TW I410527 B TWI410527 B TW I410527B
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substrate
plated
plating solution
electroplating
sealing ring
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TW99114478A
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TW201139747A (en
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Yung Chi Lin
Y F Lin
Ting Yueh Chen
Jing Cheng Lin
Shau Lin Shue
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Abstract

According to an embodiment of the present invention, an electroplating apparatus is provided, which includes a holder used to support a carrier substrate and a to-be-plated substrate disposed on the carrier substrate, wherein the to-be-plated substrate has a patterned material layer thereon, and the patterned material layer has at least an opening exposing a to-be-plated region on the to-be-plated substrate, and a seal ring used to be disposed on the to-be-plated substrate to confine an electroplating solution on the to-be-plated region, wherein the seal ring includes at least a protruding portion used to contact with the carrier substrate to block the electroplating solution from passing to the holder.

Description

電鍍輔助裝置及於基板上電鍍導電層之方法Plating auxiliary device and method for plating conductive layer on substrate

本發明係有關於電鍍裝置,且特別是有關於電鍍裝置中之密封環。This invention relates to electroplating apparatus, and in particular to sealing rings in electroplating apparatus.

在半導體積體電路之製作中,金屬導線層用以形成半導體晶圓中各種元件之間的內連線。電鍍製程為用以形成金屬導線層的方法之一。例如,可透過電鍍製程而於半導體晶圓上形成所需的導電圖案,其例如是圖案化銅層。In the fabrication of semiconductor integrated circuits, metal wire layers are used to form interconnects between various components in a semiconductor wafer. The electroplating process is one of the methods for forming a metal wiring layer. For example, a desired conductive pattern can be formed on a semiconductor wafer through an electroplating process, such as a patterned copper layer.

為了增進半導體元件之可靠度與良率,改良電鍍裝置以減低電鍍製程期間對半導體元件造成傷害之風險成為重要課題。In order to improve the reliability and yield of semiconductor components, it has become an important issue to improve the plating apparatus to reduce the risk of damage to semiconductor components during the plating process.

本發明一實施例提供一種電鍍裝置,包括基座,用以承載承載基板及設置於承載基板上之待電鍍基板,其中待電鍍基板上具有圖案化材料層,圖案化材料層具有至少一開口,露出待電鍍基板上之待電鍍區,以及密封環,用於設置於待電鍍基板上以將電鍍液侷限於待電鍍區之上,其中密封環包括至少一凸出部分,用以接觸承載基板以阻擋電鍍液溢流至基座上。An embodiment of the present invention provides a plating apparatus including a susceptor for carrying a carrier substrate and a substrate to be plated disposed on the carrier substrate, wherein the substrate to be plated has a patterned material layer, and the patterned material layer has at least one opening. Exposing a region to be plated on the substrate to be plated, and a sealing ring for being disposed on the substrate to be plated to limit the plating solution to the region to be plated, wherein the sealing ring includes at least one protruding portion for contacting the carrier substrate Block the plating solution from overflowing onto the pedestal.

本發明一實施例提供一種於基板上電鍍導電層之方法,包括提供待電鍍基板,於待電鍍基板上形成圖案化材料層,圖案化材料層具有至少一開口,露出待電鍍基板上之待電鍍區,提供承載基板,並將待電鍍基板設置於承載基板上,將承載基板及待電鍍基板設置於基座上,將密封環設置於待電鍍基板上,其中密封環包括至少一凸出部分,使凸出部分接觸承載基底,於待電鍍區上提供電鍍液,其中密封環將電鍍液侷限於待電鍍區之上,且凸出部分阻擋電鍍液溢流至基座上,以及對待電鍍區施加電壓而於待電鍍區上形成導電層。An embodiment of the present invention provides a method for plating a conductive layer on a substrate, comprising: providing a substrate to be plated, forming a patterned material layer on the substrate to be plated, the patterned material layer having at least one opening to expose a substrate to be plated to be plated a mounting substrate is provided, and the substrate to be plated is disposed on the carrier substrate, the carrier substrate and the substrate to be plated are disposed on the base, and the sealing ring is disposed on the substrate to be plated, wherein the sealing ring includes at least one protruding portion. The protruding portion is brought into contact with the carrier substrate, and a plating solution is provided on the region to be plated, wherein the sealing ring limits the plating solution to the upper portion to be plated, and the protruding portion blocks the plating solution from overflowing onto the pedestal, and the plating region is applied The voltage forms a conductive layer on the region to be plated.

以下,將詳細討論本發明實施例之形成與使用方式。然應注意的是,實施例提供許多可應用於廣泛應用面之發明特點。所討論之特定實施例僅為舉例說明製作與使用本發明實施例之特定方式,不可用以限制本發明實施例之範圍。Hereinafter, the formation and use of the embodiments of the present invention will be discussed in detail. It should be noted, however, that the embodiments provide a number of inventive features that can be applied to a wide range of applications. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the invention, and are not intended to limit the scope of the embodiments.

此外,在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明,不一定代表所討論之不同實施例及/或結構之間具有任何關連性。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。且在圖式中,實施例之形狀或是厚度可擴大,以簡化或是方便標示。再者,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式。Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not necessarily to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers. In the drawings, the shape or thickness of the embodiment may be expanded to simplify or facilitate the marking. Furthermore, elements not shown or described in the figures are in the form known to those of ordinary skill in the art.

第1圖顯示發明人所知的一種電鍍裝置的剖面示意圖。然而,應注意的是,其並非為用以判定本發明之可專利性的習知技術,僅用以顯示發明人所發現的問題。Figure 1 shows a schematic cross-sectional view of a plating apparatus known to the inventors. However, it should be noted that it is not a conventional technique for determining the patentability of the present invention, but merely to show the problems discovered by the inventors.

如第1圖所示,電鍍裝置10包括用以承載待電鍍基板100之基座104。待電鍍基板100例如為矽晶圓,其厚度可介於約1微米至約800微米之間。當待電鍍基板100之厚度較薄時,可將其承載於承載基板102之上以方便後續製程之進行。As shown in FIG. 1, the plating apparatus 10 includes a susceptor 104 for carrying a substrate 100 to be plated. The substrate to be plated 100 is, for example, a germanium wafer, and may have a thickness between about 1 micrometer and about 800 micrometers. When the thickness of the substrate to be plated 100 is thin, it can be carried on the carrier substrate 102 to facilitate the subsequent process.

如第1圖所示,在待電鍍基板100上可形成有一圖案化材料層106,其例如是一光阻層。圖案化材料層106可具有一開口(未顯示),其露出待電鍍基板100之待電鍍區(未顯示)。As shown in FIG. 1, a patterned material layer 106, which is, for example, a photoresist layer, may be formed on the substrate 100 to be plated. The patterned material layer 106 can have an opening (not shown) that exposes a region to be plated (not shown) of the substrate 100 to be plated.

為了於待電鍍基板100上電鍍所需之導電層,可於待電鍍基板100上設置密封環110。在第1圖之實施例中,密封環110係圍繞待電鍍基板100之待電鍍區而設置,而可將電鍍所需之電鍍液108侷限於待電鍍區之上。密封環110包括凸出部110a及110b,用以分別抵住圖案化材料層106及待電鍍基板100,並避免電鍍液108溢流至基座104。此外,電鍍裝置10還可包括導電電極112,其例如為一導電探針。導電電極112係與待電鍍基板100上之待電鍍區電性連接,可用以對待電鍍區施加電壓,並使電鍍液108中之導電離子還原並沉積於待電鍍區上而形成所需之導電層。In order to plate the conductive layer required for plating on the substrate 100 to be plated, a sealing ring 110 may be disposed on the substrate 100 to be plated. In the embodiment of Fig. 1, the sealing ring 110 is disposed around the region to be plated of the substrate 100 to be plated, and the plating solution 108 required for electroplating can be limited to the region to be plated. The seal ring 110 includes projections 110a and 110b for respectively resisting the patterned material layer 106 and the substrate 100 to be plated, and avoiding the plating solution 108 from overflowing to the susceptor 104. Additionally, electroplating apparatus 10 can also include a conductive electrode 112, such as a conductive probe. The conductive electrode 112 is electrically connected to the region to be plated on the substrate 100 to be plated, and can be used to apply a voltage to the plated region, and the conductive ions in the plating solution 108 are reduced and deposited on the region to be plated to form a desired conductive layer. .

然而,本案發明人發現,在電鍍一段時間之後,電鍍液108可能會穿越密封環110之阻擋而溢流至基座104。如第1圖所示,部分的電鍍液108a溢流至基座104上。其中,部分的電鍍液108a可能滲入承載基板102與基座104之間的界面處而增加承載基板102與基座104彼此間之黏著力。當電鍍製程完成而需將承載基板102連同其上之待電鍍基板100自基座104取下時,因承載基板102與基座104彼此間之黏著力增加而需施加較大力量方能使承載基板102與基座104分離。在此情形下,待電鍍基板100易因受到外力之彎折而使內部之線路及/或元件受到破壞。However, the inventors of the present invention have found that after a period of plating, the plating solution 108 may overflow through the seal ring 110 and overflow to the susceptor 104. As shown in Fig. 1, a portion of the plating solution 108a overflows onto the susceptor 104. Wherein, part of the plating solution 108a may penetrate into the interface between the carrier substrate 102 and the susceptor 104 to increase the adhesion between the carrier substrate 102 and the susceptor 104. When the plating process is completed and the carrier substrate 102 and the substrate 100 to be plated thereon are removed from the susceptor 104, a large force is required to increase the adhesion between the carrier substrate 102 and the susceptor 104. The substrate 102 is separated from the susceptor 104. In this case, the substrate 100 to be plated is liable to be damaged by external force and the internal wiring and/or components are damaged.

為了避免如第1圖實施例所述之情形發生,本發明實施例提供一種電鍍裝置,其具有特殊設計之密封環,可有效避免及/或減少電鍍液溢流至基座所造成之各種問題。以下,將配合圖式說明本發明實施例之電鍍裝置。In order to avoid the situation as described in the embodiment of FIG. 1 , an embodiment of the present invention provides a plating apparatus having a specially designed sealing ring, which can effectively avoid and/or reduce various problems caused by overflow of the plating solution to the susceptor. . Hereinafter, a plating apparatus according to an embodiment of the present invention will be described with reference to the drawings.

第2圖顯示根據本發明一實施例之電鍍裝置的剖面示意圖。如第2圖所示,電鍍裝置20包括用以承載待電鍍基板200之基座204。待電鍍基板200可為半導體晶圓(例如矽晶圓)其厚度可介於約1微米至約800微米之間。當待電鍍基板200之厚度較薄時(例如約1微米至約100徵米),可將其承載於承載基板202之上以方便後續製程之進行。Fig. 2 is a cross-sectional view showing a plating apparatus according to an embodiment of the present invention. As shown in FIG. 2, the plating apparatus 20 includes a susceptor 204 for carrying a substrate 200 to be plated. The substrate to be plated 200 can be a semiconductor wafer (eg, a germanium wafer) having a thickness between about 1 micrometer and about 800 micrometers. When the thickness of the substrate to be plated 200 is relatively thin (for example, about 1 micrometer to about 100 micrometers), it can be carried on the carrier substrate 202 to facilitate the subsequent process.

承載基板202可包括(但不限於)半導體材料或絕緣材料。在一實施例中,承載基板202之尺寸大於待電鍍基板200。例如,當待電鍍基板200為一晶圓時,承載基板202可為一直徑較大之晶圓或玻璃基板等。The carrier substrate 202 can include, but is not limited to, a semiconductor material or an insulating material. In an embodiment, the size of the carrier substrate 202 is larger than the substrate 200 to be plated. For example, when the substrate to be plated 200 is a wafer, the carrier substrate 202 may be a wafer having a larger diameter or a glass substrate or the like.

如第2圖所示,在待電鍍基板200上可形成有一圖案化材料層206,其例如是一光阻層。圖案化材料層206可具有一開口(未顯示),其露出待電鍍基板200之待電鍍區(未顯示)。然應注意的是,圖案化材料層206不限於為光阻層。在其他實施例中,圖案化材料層206可為介電層、導電層、或其他材料層。As shown in FIG. 2, a patterned material layer 206, which is, for example, a photoresist layer, may be formed on the substrate 200 to be plated. The patterned material layer 206 can have an opening (not shown) that exposes a region to be plated (not shown) of the substrate 200 to be plated. It should be noted that the patterned material layer 206 is not limited to being a photoresist layer. In other embodiments, the patterned material layer 206 can be a dielectric layer, a conductive layer, or other material layer.

為了於待電鍍基板200上電鍍所需之導電層,可於待電鍍基板200上設置密封環210。密封環210之材質例如包括(但不限於)絕緣材料。在一實施例中,密封環210之材質可包括具彈性、抗酸鹼腐蝕之絕緣材料,例如是丁腈橡膠(Nitrile Butadiene Rubber,NBR)、氫化丁腈橡膠(HNBR)、氟素橡膠(FKM)、或全氟化橡膠(FFKM)。在第2圖之實施例中,密封環210係圍繞待電鍍基板200之待電鍍區而設置,而可將電鍍所需之電鍍液208侷限於待電鍍區之上。在第2圖之實施例中,密封環210係經特殊設計而包括至少一凸出部210c。凸出部210c用以接觸並抵住承載基底202而可避免電鍍液208溢流至基座204。In order to plate the conductive layer required for plating on the substrate 200 to be plated, a sealing ring 210 may be disposed on the substrate 200 to be plated. The material of the seal ring 210 includes, for example, but not limited to, an insulating material. In an embodiment, the material of the sealing ring 210 may include an elastic material resistant to acid and alkali corrosion, such as Nitrile Butadiene Rubber (NBR), hydrogenated nitrile rubber (HNBR), and fluorocarbon rubber (FKM). ), or perfluorinated rubber (FFKM). In the embodiment of Fig. 2, the sealing ring 210 is disposed around the area to be plated of the substrate 200 to be plated, and the plating solution 208 required for electroplating can be limited to the area to be plated. In the embodiment of Fig. 2, the seal ring 210 is specifically designed to include at least one projection 210c. The protrusion 210c is used to contact and abut the carrier substrate 202 to prevent the plating solution 208 from overflowing to the susceptor 204.

此外,密封環210還可選擇性包括至少一凸出部210a及至少一凸出部210b,用以分別接觸並抵住圖案化材料層206及待電鍍基板200,可進一步避免電鍍液208溢流至基座204。在第2圖之實施例中,由於密封環210之凸出部210c接觸並抵住承載基底202,即使部分的電鍍液208a溢流至承載基底202之上,接觸並抵住承載基底202之凸出部210c可有效阻擋溢流之電鍍液208a,可避免電鍍液208a溢流至基座204。因此,當電鍍製程完成而需將承載基板202連同其上之待電鍍基板200自基座204取下時,因承載基板202與基座204彼此間之界面未滲入電鍍液208a,在此情形下,可輕易地將承載基板202及待電鍍基板200取下,避免待電鍍基板100受到外力之彎折而使內部之線路及/或元件受到破壞。In addition, the sealing ring 210 may further include at least one protruding portion 210a and at least one protruding portion 210b for respectively contacting and abutting the patterned material layer 206 and the substrate 200 to be plated, thereby further preventing the plating solution 208 from overflowing. To the pedestal 204. In the embodiment of FIG. 2, since the projection 210c of the seal ring 210 contacts and abuts the carrier substrate 202, even if a portion of the plating solution 208a overflows over the carrier substrate 202, it contacts and abuts against the projection of the carrier substrate 202. The outlet portion 210c can effectively block the overflow plating solution 208a, and the plating solution 208a can be prevented from overflowing to the susceptor 204. Therefore, when the plating process is completed and the carrier substrate 202 and the substrate 200 to be plated thereon are removed from the susceptor 204, the interface between the carrier substrate 202 and the susceptor 204 does not penetrate into the plating solution 208a, in which case The carrier substrate 202 and the substrate to be plated 200 can be easily removed, and the substrate 100 to be plated is prevented from being bent by an external force to damage the internal wiring and/or components.

此外,電鍍裝置20還可包括導電電極212,其例如為一導電探針。導電電極212係與待電鍍基板200上之待電鍍區電性連接,可用以對待電鍍區施加電壓,並使電鍍液208中之導電離子還原並沉積於待電鍍區上而形成所需之導電層。例如,在一實施例中,導電電極212係與待電鍍區上所預先形成之晶種層電性連接。在一實施例中,導電電極212可為密封環210之一部分。在另一實施例中,導電電極212非密封環210之一部分而不與密封環210相連。Additionally, plating apparatus 20 can also include a conductive electrode 212, such as a conductive probe. The conductive electrode 212 is electrically connected to the region to be plated on the substrate 200 to be plated, and can be used to apply a voltage to the plated region, and the conductive ions in the plating solution 208 are reduced and deposited on the region to be plated to form a desired conductive layer. . For example, in one embodiment, the conductive electrode 212 is electrically connected to a seed layer previously formed on the region to be plated. In an embodiment, the conductive electrode 212 can be part of the seal ring 210. In another embodiment, the conductive electrode 212 is not part of the seal ring 210 and is not connected to the seal ring 210.

第3A-3F圖顯示根據本發明一實施例於基板上電鍍導電層的一系列製程剖面示意圖,其係採用本發明實施例之電鍍裝置進行。3A-3F are schematic cross-sectional views showing a series of processes for electroplating a conductive layer on a substrate in accordance with an embodiment of the present invention, which is performed using a plating apparatus according to an embodiment of the present invention.

如第3A圖所示,提供待電鍍基板300,其例如可為半導體晶圓。在一實施例中,待電鍍基板300中預先定義有一孔洞324,其自待電鍍基板300之表面300a朝另一表面300b延伸。待電鍍基板300上還形成有絕緣層322,其形成於表面300a上,並延伸於孔洞324之側壁及底部上。在孔洞324中還填充有導電插塞326。在後續的研磨製程之後,導電插塞326將成為待電鍍基板300中之穿基底導電結構(through-substrate via,TSV)。絕緣層322之材質例如包括(但不限於)氧化矽、氮化矽、氮氧化矽、或前述之組合。導電插塞326之材質例如包括(但不限於)銅、鋁、金、鉑、鎢、或前述之組合。As shown in FIG. 3A, a substrate 300 to be plated is provided, which may be, for example, a semiconductor wafer. In an embodiment, a hole 324 is defined in the substrate to be plated 300, which extends from the surface 300a of the substrate 300 to be plated toward the other surface 300b. An insulating layer 322 is also formed on the substrate to be plated 300, which is formed on the surface 300a and extends on the sidewalls and the bottom of the hole 324. A conductive plug 326 is also filled in the hole 324. After the subsequent polishing process, the conductive plug 326 will become a through-substrate via (TSV) in the substrate 300 to be plated. The material of the insulating layer 322 includes, for example, but not limited to, cerium oxide, cerium nitride, cerium oxynitride, or a combination thereof. The material of the conductive plug 326 includes, for example, but not limited to, copper, aluminum, gold, platinum, tungsten, or a combination thereof.

接著,如第3B圖所示,提供承載基板302,並將待電鍍基板300設置於其上。例如,可於待電鍍基板300之表面300a與承載基板302之間塗佈黏著層(未顯示)而將待電鍍基板300固定於承載基板302之上。承載基板302可包括(但不限於)半導體材料或絕緣材料。Next, as shown in FIG. 3B, a carrier substrate 302 is provided, and the substrate 300 to be plated is placed thereon. For example, an adhesive layer (not shown) may be applied between the surface 300a of the substrate 300 to be plated and the carrier substrate 302 to fix the substrate 300 to be plated on the carrier substrate 302. The carrier substrate 302 can include, but is not limited to, a semiconductor material or an insulating material.

如第3C圖所示,接著自待電鍍基板300之表面300b開始進行薄化製程以薄化待電鍍基板300而使導電插塞326露出。適合的薄化製程例如是機械研磨或化學基械研磨等。在一實施例中,在待電鍍基板300薄化之後,導電插塞326之一端係凸出於待電鍍基板300之表面300b。此外,在待電鍍基板300薄化之後,原先形成於待電鍍基板300中之孔洞324現已貫穿待電鍍基板300而成為穿孔324’。As shown in FIG. 3C, a thinning process is then started from the surface 300b of the substrate 300 to be plated to thin the substrate 300 to be plated to expose the conductive plug 326. Suitable thinning processes are, for example, mechanical or chemical mechanical polishing. In one embodiment, after the substrate 300 to be plated is thinned, one end of the conductive plug 326 protrudes from the surface 300b of the substrate 300 to be plated. In addition, after the substrate 300 to be plated is thinned, the holes 324 originally formed in the substrate 300 to be plated are now passed through the substrate 300 to be plated to become the through holes 324'.

接著,如第3D圖所示,於表面300及露出的導電插塞326上形成晶種層328以方便後續電鍍製程之進行。晶種層328可例如以物理氣相沉積法形成,其材質例如為銅。此外,晶種層328與待電鍍基板300之間較佳形成有擴散阻障層(未顯示),其材質例如是Ti或TiN,可避免導電材料(例如,銅)擴散進入待電鍍基板300,並可增加晶種層328與待電鍍基板300之間的黏著性。Next, as shown in FIG. 3D, a seed layer 328 is formed on the surface 300 and the exposed conductive plugs 326 to facilitate subsequent plating processes. The seed layer 328 can be formed, for example, by physical vapor deposition, and the material thereof is, for example, copper. In addition, a diffusion barrier layer (not shown) is preferably formed between the seed layer 328 and the substrate 300 to be plated, and the material thereof is, for example, Ti or TiN, to prevent the conductive material (for example, copper) from diffusing into the substrate 300 to be plated. The adhesion between the seed layer 328 and the substrate 300 to be plated can be increased.

如第3D圖所示,在形成晶種層328之後,於待電鍍基板300上形成圖案化材料層306。圖案化材料層306可包括介電層、導電層、絕緣層、光阻層或其他材料層。在一實施例中,圖案化材料層306為一光阻層,且具有至少一開口307。開口307露出待電鍍基板300上之一待電鍍區(即,開口307中所露出之晶種層328所佔區域)。圖案化材料層306可避免在電鍍製程時,導電材料電鍍沉積在待電鍍基板300上不需形成導電層之區域。As shown in FIG. 3D, after the seed layer 328 is formed, a patterned material layer 306 is formed on the substrate 300 to be plated. The patterned material layer 306 can include a dielectric layer, a conductive layer, an insulating layer, a photoresist layer, or other material layers. In one embodiment, the patterned material layer 306 is a photoresist layer and has at least one opening 307. The opening 307 exposes a region to be plated (i.e., a region occupied by the seed layer 328 exposed in the opening 307) on the substrate 300 to be plated. The patterned material layer 306 can prevent the conductive material from being electroplated on the substrate to be plated 300 without forming a conductive layer during the electroplating process.

接著,如第3E圖所示,將承載基板302及待電鍍基板300設置於基座304之上。接著,將密封環310設置於待電鍍基板300上。在第3E圖之實施例中,密封環310係圍繞待電鍍基板300之待電鍍區而設置,而可將電鍍所需之電鍍液308侷限於待電鍍區之上。密封環310係經特殊設計而包括至少一凸出部310c。凸出部310c用以接觸並抵住承載基底302而可避免電鍍液308溢流至基座304。Next, as shown in FIG. 3E, the carrier substrate 302 and the substrate 300 to be plated are placed on the susceptor 304. Next, the sealing ring 310 is placed on the substrate 300 to be plated. In the embodiment of FIG. 3E, the sealing ring 310 is disposed around the region to be plated of the substrate 300 to be plated, and the plating solution 308 required for electroplating can be limited to the region to be plated. The seal ring 310 is specifically designed to include at least one projection 310c. The protrusion 310c is used to contact and abut the carrier substrate 302 to prevent the plating solution 308 from overflowing to the susceptor 304.

此外,密封環310還可選擇性包括至少一凸出部310a及至少一凸出部310b,用以分別接觸並抵住圖案化材料層306及待電鍍基板300,可進一步避免電鍍液308溢流至基座304。在第3E圖之實施例中,由於密封環310之凸出部310c接觸並抵住承載基底302,即使部分的電鍍液308a溢流至承載基底302之上,接觸並抵住承載基底302之凸出部310c可有效阻擋溢流之電鍍液308a,可避免電鍍液308a溢流至基座304。In addition, the sealing ring 310 can further include at least one protruding portion 310a and at least one protruding portion 310b for respectively contacting and abutting the patterned material layer 306 and the substrate to be plated 300, thereby further preventing the plating solution 308 from overflowing. To the pedestal 304. In the embodiment of FIG. 3E, since the projection 310c of the seal ring 310 contacts and abuts the carrier substrate 302, even if a portion of the plating solution 308a overflows onto the carrier substrate 302, it contacts and abuts against the projection of the carrier substrate 302. The outlet portion 310c can effectively block the overflow plating solution 308a, and the plating solution 308a can be prevented from overflowing to the susceptor 304.

接著,可透過對待電鍍基板300之待電鍍區(即開口307底部之晶種層328之上)施加電源以使電鍍液中之金屬離子沉積還原於晶種層328之上。例如,可透過導電電極312而將電鍍所需之電源施加至晶種層328。Next, a power source can be applied through the region to be plated (i.e., above the seed layer 328 at the bottom of the opening 307) of the substrate 300 to be plated to reduce metal ion deposition in the plating solution over the seed layer 328. For example, a power source required for electroplating can be applied to the seed layer 328 through the conductive electrode 312.

因此,如第3F圖所示,可透過上述之電鍍製程而於待電鍍區上形成出導電層330。接著,可選擇性移除圖案化材料層及其正下方之晶種層。當電鍍製程完成而需將承載基板302連同其上之待電鍍基板300自基座304取下時,因承載基板302與基座304彼此間之界面未滲入電鍍液308a。在此情形下,可輕易地將承載基板302及待電鍍基板300取下,避免待電鍍基板300受到外力之彎折而使內部之線路及/或元件受到破壞。Therefore, as shown in FIG. 3F, the conductive layer 330 can be formed on the region to be plated through the above-described plating process. Next, the layer of patterned material and the seed layer directly beneath it can be selectively removed. When the plating process is completed and the carrier substrate 302 and the substrate to be plated 300 to be plated are removed from the susceptor 304, the interface between the carrier substrate 302 and the susceptor 304 does not penetrate into the plating solution 308a. In this case, the carrier substrate 302 and the substrate to be plated 300 can be easily removed, and the substrate to be plated 300 is prevented from being bent by an external force to damage the internal wiring and/or components.

在一實施例中,本發明實施例之密封環係包括複數個凸出部,其分別與不同高度之表面接觸以阻擋電鍍液之溢流。然應注意的是,本發明實施例之密封環不限於此。例如,密封環之凸出部可為一體成型之連續結構。第4A-4C圖顯示根據本發明數個實施例之電鍍裝置的剖面示意圖,其分別具有不同的密封環設計。In one embodiment, the seal ring of the embodiment of the present invention includes a plurality of projections that respectively contact surfaces of different heights to block overflow of the plating solution. It should be noted that the seal ring of the embodiment of the present invention is not limited thereto. For example, the projection of the seal ring can be an integrally formed continuous structure. 4A-4C are cross-sectional views showing plating apparatus according to several embodiments of the present invention, each having a different seal ring design.

在第4A圖之實施例中,電鍍裝置40包括基座404及密封環410。基座404用以承載承載基板402及設至於其上之待電鍍基板400,其中待電鍍基板400上形成有圖案化材料層406,其開口露出待電鍍基板400上之待電鍍區。電鍍裝置40還包括導電電極412,用以提供電鍍導電層時所需之電源。電鍍裝置40之密封環410係晶特別設計,其凸出部410a除了接觸承載基板402之外,還接觸待電鍍基板400及圖案化材料層406,可有效避免電鍍液408溢流至基座404上。In the embodiment of FIG. 4A, the plating apparatus 40 includes a base 404 and a seal ring 410. The susceptor 404 is configured to carry the carrier substrate 402 and the substrate to be plated 400 disposed thereon. The substrate to be plated 400 is formed with a patterned material layer 406 whose opening exposes a region to be plated on the substrate 400 to be plated. The plating apparatus 40 also includes a conductive electrode 412 for providing a power source required to plate the conductive layer. The sealing ring 410 of the electroplating device 40 is specially designed. The protruding portion 410a contacts the substrate to be plated 400 and the patterned material layer 406 in addition to the carrier substrate 402, thereby effectively preventing the plating solution 408 from overflowing to the susceptor 404. on.

第4B圖顯示另一實施例之電鍍裝置50,其結構與第4A圖之實施例相似,因此相同或相似之元件將採用相同或相似之標號標示。電鍍裝置50與40之間的主要差異在於密封環之設計。在電鍍裝置50中,密封環410包括凸出部410a及凸出部410c,其中凸出部410a接觸待電鍍基板400及圖案化材料層406,而另一凸出部410c接觸承載基板402。相似地,電鍍裝置50之密封環410可有效避免電鍍液408溢流至基座404上。Fig. 4B shows a plating apparatus 50 of another embodiment, the structure of which is similar to that of the embodiment of Fig. 4A, and therefore the same or similar elements will be designated by the same or like numerals. The main difference between electroplating devices 50 and 40 is the design of the seal ring. In the plating apparatus 50, the seal ring 410 includes a projection 410a and a projection 410c, wherein the projection 410a contacts the substrate 400 to be plated and the patterned material layer 406, and the other projection 410c contacts the carrier substrate 402. Similarly, the seal ring 410 of the plating apparatus 50 can effectively prevent the plating solution 408 from overflowing onto the susceptor 404.

第4C圖顯示另一實施例之電鍍裝置60,其結構與第4A圖之實施例相似,因此相同或相似之元件將採用相同或相似之標號標示。電鍍裝置60與40之間的主要差異在於密封環之設計。在電鍍裝置60中,密封環410包括凸出部410a及凸出部410c,其中凸出部410a接觸圖案化材料層406,而另一凸出部410c接觸待電鍍基板及承載基板402。相似地,電鍍裝置60之密封環410可有效避免電鍍液408溢流至基座404上。4C shows a plating apparatus 60 of another embodiment, the structure of which is similar to that of the embodiment of FIG. 4A, and therefore the same or similar elements will be designated by the same or similar reference numerals. The main difference between electroplating devices 60 and 40 is the design of the seal ring. In the plating apparatus 60, the seal ring 410 includes a projection 410a and a projection 410c, wherein the projection 410a contacts the patterned material layer 406, and the other projection 410c contacts the substrate to be plated and the carrier substrate 402. Similarly, the seal ring 410 of the plating apparatus 60 can effectively prevent the plating solution 408 from overflowing onto the susceptor 404.

如上所述,在本發明實施例之電鍍裝置中,透過密封環之設置而使密封環上之凸出部抵住並接觸承載基板,可有效阻擋電鍍液之溢流。尤其,當承載基板所設置之待電鍍基板中因需形成穿基底導電結構而薄化時,確實且有效地避免電鍍製程所用之電鍍液滲透至基座更形重要。採用本發明實施例之電鍍裝置來於待電鍍基板(例如,薄化後之晶圓)上形成導電層,可使所形成元件之良率與可靠度提升。As described above, in the plating apparatus of the embodiment of the present invention, the projection on the seal ring is pressed against and contacts the carrier substrate through the arrangement of the seal ring, so that the overflow of the plating solution can be effectively blocked. In particular, when the substrate to be plated provided on the carrier substrate is thinned by the formation of the through-substrate conductive structure, it is more important to effectively and effectively prevent the plating solution used in the electroplating process from penetrating into the pedestal. The electroplating device of the embodiment of the present invention is used to form a conductive layer on a substrate to be plated (for example, a thinned wafer), so that the yield and reliability of the formed device can be improved.

雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

10、20、40、50、60...電鍍裝置10, 20, 40, 50, 60. . . Plating device

100、200、300、400...待電鍍基板100, 200, 300, 400. . . Substrate to be plated

102、202、302、402...承載基板102, 202, 302, 402. . . Carrier substrate

104、204、304、404...基座104, 204, 304, 404. . . Pedestal

106、206、306、406...材料層106, 206, 306, 406. . . Material layer

108、108a、208、208a、308、308a、408...電鍍液108, 108a, 208, 208a, 308, 308a, 408. . . Plating solution

110、210、310、410...密封環110, 210, 310, 410. . . Sealing ring

110a、110b、210a、210b、210c、310a、310b、310c、410a、410c...凸出部110a, 110b, 210a, 210b, 210c, 310a, 310b, 310c, 410a, 410c. . . Protrusion

112、212、312、412...導電電極112, 212, 312, 412. . . Conductive electrode

300a、300b...表面300a, 300b. . . surface

307...開口307. . . Opening

322...絕緣層322. . . Insulation

324...孔洞324. . . Hole

324’...穿孔324’. . . perforation

326...導電插塞326. . . Conductive plug

328...晶種層328. . . Seed layer

330...導電層330. . . Conductive layer

第1圖顯示發明人所知的一種電鍍裝置的剖面示意圖。Figure 1 shows a schematic cross-sectional view of a plating apparatus known to the inventors.

第2圖顯示根據本發明一實施例之電鍍裝置的剖面示意圖。Fig. 2 is a cross-sectional view showing a plating apparatus according to an embodiment of the present invention.

第3A-3F圖顯示根據本發明一實施例於基板上電鍍導電層的一系列製程剖面示意圖。3A-3F are schematic cross-sectional views showing a series of processes for plating a conductive layer on a substrate in accordance with an embodiment of the present invention.

第4A-4C圖顯示根據本發明數個實施例之電鍍裝置的剖面示意圖4A-4C are cross-sectional views showing a plating apparatus according to several embodiments of the present invention.

300...待電鍍基板300. . . Substrate to be plated

302...承載基板302. . . Carrier substrate

304...基座304. . . Pedestal

306...材料層306. . . Material layer

308、308a...電鍍液308, 308a. . . Plating solution

310...密封環310. . . Sealing ring

310a、310b、310c...凸出部310a, 310b, 310c. . . Protrusion

312...導電電極312. . . Conductive electrode

300a、300b...表面300a, 300b. . . surface

307...開口307. . . Opening

322...絕緣層322. . . Insulation

324’...穿孔324’. . . perforation

326...導電插塞326. . . Conductive plug

328...晶種層328. . . Seed layer

330...導電層330. . . Conductive layer

Claims (14)

一種電鍍輔助裝置,包括:一基座,用以承載一承載基板及設置於該承載基板上之一待電鍍基板,其中該待電鍍基板上具有一圖案化材料層,該圖案化材料層具有至少一開口,露出該待電鍍基板上之一待電鍍區;以及一密封環,用於設置於該待電鍍基板上以將一電鍍液侷限於該待電鍍區之上,其中該密封環包括至少一凸出部分,用以接觸該承載基板以阻擋該電鍍液溢流至該基座上。 An electroplating auxiliary device includes: a pedestal for carrying a carrier substrate and a substrate to be plated disposed on the carrier substrate, wherein the substrate to be plated has a patterned material layer, the patterned material layer having at least An opening to expose a region to be plated on the substrate to be plated; and a sealing ring for being disposed on the substrate to be plated to limit a plating solution to the region to be plated, wherein the sealing ring includes at least one And a protruding portion for contacting the carrier substrate to block the plating solution from overflowing onto the base. 如申請專利範圍第1項所述之電鍍輔助裝置,其中該至少一凸出部分接觸該待電鍍基板及/或該圖案化材料層以阻擋該電鍍液溢流至該基座上。 The electroplating auxiliary device according to claim 1, wherein the at least one protruding portion contacts the substrate to be plated and/or the patterned material layer to block the plating solution from overflowing onto the susceptor. 如申請專利範圍第1項所述之電鍍輔助裝置,其中該密封環更包括至少一第二凸出部,用以接觸該待電鍍基板以阻擋該電鍍液溢流至該基座上。 The electroplating auxiliary device of claim 1, wherein the sealing ring further comprises at least one second protrusion for contacting the substrate to be plated to block the plating solution from overflowing onto the base. 如申請專利範圍第1或2項所述之電鍍輔助裝置,其中該密封環更包括至少一第三凸出部,用以接觸該圖案化材料層以阻擋該電鍍液溢流至該基座上。 The plating auxiliary device of claim 1 or 2, wherein the sealing ring further comprises at least one third protruding portion for contacting the patterned material layer to block the plating solution from overflowing onto the base . 如申請專利範圍第1項所述之電鍍輔助裝置,其中該圖案化材料層包括一光阻層。 The electroplating aid device of claim 1, wherein the patterned material layer comprises a photoresist layer. 如申請專利範圍第1項所述之電鍍輔助裝置,其中該待電鍍基板包括一半導體晶圓。 The electroplating auxiliary device according to claim 1, wherein the substrate to be plated comprises a semiconductor wafer. 如申請專利範圍第6項所述之電鍍輔助裝置,其中該半導體晶圓之厚度介於約1微米至約800微米之間。 The electroplating aid of claim 6, wherein the semiconductor wafer has a thickness of between about 1 micrometer and about 800 micrometers. 如申請專利範圍第1項所述之電鍍輔助裝置,更包括一導電電極,電性連接該待電鍍基板上之該待電鍍區。 The electroplating auxiliary device according to claim 1, further comprising a conductive electrode electrically connected to the region to be plated on the substrate to be plated. 如申請專利範圍第1項所述之電鍍輔助裝置,其中該待電鍍基板包括一穿基底導電結構。 The electroplating auxiliary device according to claim 1, wherein the substrate to be plated comprises a through-substrate conductive structure. 一種於基板上電鍍導電層之方法,包括:提供一待電鍍基板;於該待電鍍基板上形成一圖案化材料層,該圖案化材料層具有至少一開口,露出該待電鍍基板上之一待電鍍區;提供一承載基板,並將該待電鍍基板設置於該承載基板上;將該承載基板及該待電鍍基板設置於一基座上;將一密封環設置於該待電鍍基板上,其中該密封環包括至少一凸出部分,使該至少一凸出部分接觸該承載基底;於該待電鍍區上提供一電鍍液,其中該密封環將該電鍍液侷限於該待電鍍區之上,且該至少一凸出部分阻擋該電鍍液溢流至該基座上;以及對該待電鍍區施加電壓而於該待電鍍區上形成一導電層。 A method for plating a conductive layer on a substrate, comprising: providing a substrate to be plated; forming a patterned material layer on the substrate to be plated, the patterned material layer having at least one opening to expose one of the substrates to be plated a plating substrate; a carrier substrate is disposed, and the substrate to be plated is disposed on the carrier substrate; the carrier substrate and the substrate to be plated are disposed on a base; and a sealing ring is disposed on the substrate to be plated, wherein The sealing ring includes at least one protruding portion, the at least one protruding portion contacting the carrier substrate; a plating solution is provided on the region to be plated, wherein the sealing ring limits the plating solution to the region to be plated, And the at least one protruding portion blocks the plating solution from overflowing onto the base; and applying a voltage to the region to be plated to form a conductive layer on the region to be plated. 如申請專利範圍第10項所述之於基板上電鍍導電層之方法,其中該密封環更包括至少一第二凸出部,當使該至少一凸出部分接觸該承載基底時,該至少一第二凸出部接觸該待電鍍基板以阻擋該電鍍液溢流至該基座上。 The method of electroplating a conductive layer on a substrate according to claim 10, wherein the sealing ring further comprises at least one second protrusion, the at least one protruding portion contacting the carrier substrate, the at least one The second protrusion contacts the substrate to be plated to block the plating solution from overflowing onto the base. 如申請專利範圍第10或11項所述之於基板上電鍍導電層之方法,其中該密封環更包括至少一第三凸出部,當使該至少一凸出部分接觸該承載基底時,該至少一第三凸出部接觸該圖案化材料層以阻擋該電鍍液溢流至該基座上。 The method of electroplating a conductive layer on a substrate according to claim 10 or 11, wherein the sealing ring further comprises at least one third protrusion, when the at least one protruding portion is brought into contact with the carrier substrate, At least one third protrusion contacts the layer of patterned material to block the plating solution from overflowing onto the susceptor. 如申請專利範圍第10項所述之於基板上電鍍導電層之方法,其中當使該密封環之該至少一凸出部分接觸該承載基底時,該至少一凸出部分接觸該待電鍍基板及/或該圖案化材料層以阻擋該電鍍液溢流至該基座上。 The method of electroplating a conductive layer on a substrate according to claim 10, wherein when the at least one protruding portion of the sealing ring contacts the carrier substrate, the at least one protruding portion contacts the substrate to be plated and / or the patterned material layer to block the plating solution from overflowing onto the susceptor. 如申請專利範圍第10項所述之於基板上電鍍導電層之方法,其中該待電鍍基板包括一穿基底導電結構。A method of plating a conductive layer on a substrate as described in claim 10, wherein the substrate to be plated comprises a through-substrate conductive structure.
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