TWI408689B - 存取儲存裝置的方法及相關控制電路 - Google Patents

存取儲存裝置的方法及相關控制電路 Download PDF

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TWI408689B
TWI408689B TW098112304A TW98112304A TWI408689B TW I408689 B TWI408689 B TW I408689B TW 098112304 A TW098112304 A TW 098112304A TW 98112304 A TW98112304 A TW 98112304A TW I408689 B TWI408689 B TW I408689B
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storage unit
storage
control circuit
mapping
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TW201037717A (en
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Chao Yin Liu
Sheng Hsuan Wang
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Jmicron Technology Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7201Logical to physical mapping or translation of blocks or pages
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7202Allocation control and policies
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7205Cleaning, compaction, garbage collection, erase control

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Description

存取儲存裝置的方法及相關控制電路
本發明係關於缺陷區塊管理的方法及相關控制電路,尤指一種用於包含有複數個快閃記憶體的儲存裝置(如:一多通道固態硬碟機)的缺陷區塊管理的方法及相關電路。
由快閃記憶體所組成的各種儲存裝置,已逐漸普及於嵌入式系統與攜帶式裝置。當人們對儲存裝置所提供的容量與效能要求越高時,也間接帶動快閃記憶體裝置的發展,最終,快閃記憶體裝置漸漸地在各個領域取代習知儲存裝置(例如傳統硬碟)的運用。一個如火如荼且轉向明朗的發展趨勢即是固態硬碟機(Solid State Drive,SSD),其係一種由快閃記憶體所組成的大容量儲存裝置,並且定位於取代傳統硬碟。相較於發展已成熟的傳統硬碟,快閃記憶體先天的物理特性導致其仍有許多亟待改良之處,其一便是資料寫入與讀取速度不佳。為了能有效提升快閃記憶體裝置的讀取與寫入效能,因此設計者引入了冗餘(redundancy)技術於固態硬碟機,主要是透過冗餘技術中一種用以提升儲存裝置之存取速度的資料分割(data stripping)技術,在固態硬碟機中設置複數個快閃記憶體,且分別形成複數個存取通道(channel)。當外部系統存取固態硬碟機時,複數個快閃記憶體可同時進行存取操作,從而提高固態硬碟機的資料存取速度。然而,由於快閃記憶體不論在製造或使用的過程中,可能因為某些原因而造成內部儲存單位的故障,又因為快閃記憶體的資料抹除係以區塊(block)為單位,因此故障的儲存單位會進一步造成其所屬的整個區塊不能再度進行抹除與儲存操作,進而形成缺陷區塊(bad block)。
傳統上,快閃記憶體的控制電路都有處理與管理缺陷區塊的機制(bad block management)。在眾多習知作法中,最簡單的一種就是區塊忽略法(Skip block method),當一儲存資料的目標位址對應於一缺陷區塊的位址時,則該筆儲存資料會被儲存至該缺陷區塊之後的下一個良好區塊(good block),亦即跳過該缺陷區塊。但此種方法若運用於多通道固態硬碟機(multi-channel SSD)中,則會因為不同存取通道之快閃記憶體間存在著區塊關聯性,若跳過某個快閃記憶體之一缺陷區塊,則其它快閃記憶體中對應於該缺陷區塊的關聯區塊,不論其是否為缺陷區塊都會被跳過,因而導致無謂的儲存空間浪費。
此外,在習知技藝中除了區塊忽略法外,亦有透過蒐集缺陷區塊的資訊(如:缺陷區塊的位址),而避免於這些已知的缺陷區塊上執行寫入或讀取操作;並且透過良好區塊(good block)來置換這些缺陷區塊以進行讀取或寫入操作,其中,缺陷區塊的位址將會被重新映射(remapping)至良好區塊以進行區塊置換操作,這些重新映射結果(remapping result)會被記錄於固態硬碟機中之控制電路。當控制電路欲對缺陷區塊進行寫入或讀取操作時,此時會依據重新映射結果轉而向缺陷區塊所對應之置換區塊進行寫入或讀取操作。一般而言,置換區塊的來源通常有兩種方式,第一種方式即是從同一快閃記憶體中,透過特定的演算法來找一個良好區塊以作為置換區塊,因此每個快閃記憶體擁有個別的重新映射結果,控制電路會依據每個快閃記憶體的重映射結果來分別存取快閃記憶體,然而,此種方法將導致控制電路的負擔過大,此外控制電路必須依據重新映射結果,依序將每個缺陷區塊替換為置換區塊,故造成較多的電路延遲;第二種方式即是在快閃記憶體中配置保留區塊(reserved block)以作為置換區塊之用,然而,此種作法的主要問題在於會增加快閃記憶體的製造成本,亦即由於相同快閃記憶體中必須保留一部分空間作為保留區塊,使得真正可規劃為儲存之用的區塊較少。
綜上所述,對於提升固態硬碟機的資料存取效能而言,習知技術仍存有許多改進的空間。
有鑑於此,為了解決習知缺陷區塊管理技術於多通道固態硬碟之應用上往往效能過低的問題,本發明便提出一種創新的缺陷區塊管理方法以及相關控制電路,來解決習知固態硬碟機之效能不彰的問題。
依據本發明之一實施例,其係提供一種用以存取一儲存裝置的方法。該儲存裝置包含有複數個儲存單元分別對應複數個存取通道,每一儲存單元分別包含有複數個區塊,該複數個存取通道係於該儲存裝置進行一資料存取操作時同時動作,以及該複數個儲存單元包含有一第一儲存單元與至少一第二儲存單元。該方法包含有:依據該複數個儲存單元中無法正常操作之缺陷區塊(bad block)來產生分別對應至該複數個儲存單元之複數個缺陷區塊列表;依據該第一儲存單元所對應之一缺陷區塊列表所指出之至少一缺陷區塊,將每一第二儲存單元中對應於該缺陷區塊且可正常操作之一良好區塊(good block)設定為一置換區塊;依據每一第二儲存單元之一缺陷區塊列表與每一置換區塊來產生相對應之一映射結果;以及依據該第一儲存單元所對應之該缺陷區塊列表與每一第二儲存單元所對應之該映射結果來存取該儲存裝置。
依據本發明之另一實施例,其係提供一種用於存取一儲存裝置之控制電路。該儲存裝置包含有複數個儲存單元分別對應複數個存取通道,每一儲存單元分別包含有複數個區塊,該複數個存取通道係於該儲存裝置進行一資料存取操作時同時動作,以及該複數個儲存單元包含有一第一儲存單元與至少一第二儲存單元。該控制電路包含有一處理單元、一儲存單元以及複數個映射單元。該處理單元會依據該複數個儲存單元中無法正常操作之缺陷區塊(bad block)來產生分別對應至該複數個儲存單元之複數個缺陷區塊列表、依據該第一儲存單元所對應之一缺陷區塊列表所指出之至少一缺陷區塊而將每一第二儲存單元中對應於該缺陷區塊且可正常操作之一良好區塊(good block)設定為一置換區塊以及依據每一第二儲存單元之一缺陷區塊列表與每一置換區塊來產生相對應之一映射結果。該儲存單元係耦接於該處理單元,用以儲存該第一儲存單元所對應之該缺陷區塊列表。該複數個映射單元分別耦接於該處理單元以及該複數個儲存單元,並且用以依據該複數個映射結果進行以相對應之設定,其中該控制電路係利用該複數個映射單元與儲存於該儲存元件之該第一儲存單元所對應之該缺陷區塊列表來存取該複數個儲存單元。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求相當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。此外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段,因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或者透過其他裝置或連接手段間接地電氣連接至該第二裝置。
請參考第1圖,其係本發明方法之一實施例的示意圖。如圖所示,固態硬碟機100為一個具有四個存取通道(4-channel)之儲存裝置,分別包含有快閃記憶體A、B、C以及D。快閃記憶體A、B、C以及D分別包含有7個區塊,而區塊的編號(即代表對應於不同位址之區塊)如圖示之標記所示,且圖示中以”X”來代表缺陷區塊。本發明之一技術特徵係在於以多通道固態硬碟機其中之一存取通道所對應之快閃記憶體的缺陷區塊狀態為基準,來產生其它快閃記憶體所對應之缺陷區塊的(重新)映射結果。因此,基於解釋上之方便,本實施例中係以快閃記憶體A之缺陷區塊狀態為基準來作為說明。應當注意的是,選用其它快閃記憶體B、C或D來作為缺陷區塊之映射結果的產生基準亦屬本發明之範疇。此外,本實施例所利用之固態硬碟機的通道數目亦非本發明之限制,換言之,本發明方法適用於採用任何其它通道數目的固態硬碟機,更甚者,熟知本發明技術領域之人,在詳讀本說明書之內容之後,亦可將本發明透過適當地修改或重新詮釋,將本發明方法應用於任何採用冗餘技術之儲存裝置,此亦屬本發明的涵蓋範圍。
由圖可知,當選定快閃記憶體A的缺陷區塊為其它快閃記憶體之映射結果的產生基準時,區塊2與區塊5會被當作基準,並將快閃記憶體B、C以及D中之對應區塊2與對應區塊5分別視為該快閃記憶體中之置換區塊,以取代該快閃記憶體中之缺陷區塊。因此,於快閃記憶體B中,區塊2本來為良好區塊,但為配合快閃記憶體A的缺陷區塊2,因此被用來做為快閃記憶體B之缺陷區塊1之置換區塊,而良好區塊5則被用來作為對應缺陷區塊6之置換區塊。同樣的,在快閃記憶體C中,良好區塊2被用來作為缺陷區塊3之置換區塊,而良好區塊5則被用來作為對應缺陷區塊4之置換區塊,而在快閃記憶體D中,區塊2本來就是缺陷區塊,因此不被用來作為置換區塊,而良好區塊5則被用來作為缺陷區塊7之置換區塊。經由以上的替換關係,缺陷區塊位址便映射至置換區塊位址以產生每一快閃記憶體的缺陷區塊映射結果,如此一來,便避免於區塊忽略法中,由於這些置換區塊因為對應至快閃記憶體A的缺陷區塊而被忽略,進而導致儲存空間浪費的情形。應當特別注意的是,於每一快閃記憶體中,置換區塊被選來替換哪一缺陷區塊的方法並非本發明所欲強調的重點,亦即,上述實施例中所描述的選擇方法僅做為範例說明之用,實非本發明之限制。
總結來說,在應用本發明方法之後,對於上述實施例中的固態硬碟機100來說,所有快閃記憶體中僅有區塊2以及區塊5是無法使用的,其餘皆可正常進行資料儲存。然而,為解決習知技藝中,每一通道之快閃記憶體擁有各自的映射結果而導致控制電路必須依序依據這些映射結果來執行位址映射的動作而耗費過多的效能與功率的問題,因此本發明另外於控制電路中為每個快閃記憶體設計一映射單元以執行位址映射的動作。請參考第2圖,映射單元200係為一硬體映射單元,設計來執行一接線式(hardwired)映射。
於初始化時,映射單元200會依據一映射結果來進行設定,接著,當指向於一缺陷區塊的一輸入位址被輸入映射單元200後,映射單元200即會依據該映射結果來將該輸入位址轉換為該缺陷區塊所對應之一置換區塊的位址,再將該置換區塊的位址輸入至快閃記憶體的位址輸入埠,因而完成位址映射。應當注意的是,若該輸入位址指向一良好區塊,則該輸入位址會被旁通(bypass)至快閃記憶體之位址輸入埠。透過這樣的映射單元,因此可以減少控制電路的工作負擔。另外,儘管上述內容將映射單元描述為設置於控制電路內,但若將任何源自本發明精神所設計之映射單元設置於控制電路外亦屬本發明的範疇。
基於上述實施例所建立的基礎,本發明所提供的方法可進一步歸納為以下步驟,並繪示於第3圖所示之流程中的步驟310~340。本發明方法所執行的流程依序可描述為:依據一儲存裝置之複數個儲存單元中無法正常操作之缺陷區塊來產生分別對應至該複數個儲存單元之複數個缺陷區塊列表;依據該複數個儲存單元中一第一儲存單元所對應之一缺陷區塊列表所指出之至少一缺陷區塊,將該複數個儲存單元中每一第二儲存單元中對應於該缺陷區塊且可正常操作之一良好區塊設定為一置換區塊;依據每一第二儲存單元之一缺陷區塊列表與每一置換區塊來產生相對應之一映射結果;以及依據該第一儲存單元所對應之該缺陷區塊列表與每一第二儲存單元所對應之該映射結果來存取該儲存裝置。
依據上述方法所揭露的精神與概念,本發明從而提供一種設置於快閃記憶體裝置中之控制電路,該控制電路按上述的缺陷區塊管理機制來進行快閃記憶體裝置(例如多通道固態硬碟機)的缺陷區塊管理。請參考第4圖,其係應用本發明控制電路之多通道固態硬碟機的實施示意圖。如圖所示,控制電路410設置於一多通道固態硬碟機400中,用以同時利用複數個存取通道491~494以對快閃記憶體401a、401b、401c以及401d進行資料存取操作。由於利用複數個存取通道來對儲存裝置進行資料寫入與讀取係為熟知本發明所屬技術領域之人所明瞭之資料分割技術的應用且亦非屬本發明之技術特徵所在,因此其詳細操作及原理在此便不多作贅述。再者,控制電路410包含有一處理單元420、一儲存單元430以及複數個錯誤校正碼處理單元442、444、446以及448,此外,複數個映射單元452、454、456以及458係分別設置於複數個錯誤校正碼處理單元442、444、446以及448中。基本上,任何寫入至快閃記憶體或讀取自快閃記憶體的資料都必須先經過錯誤校正碼處理單元的處理,因此第4圖所示之實施例便將映射單元整合於錯誤校正碼處理單元,然而依據本發明其它實施例,映射單元452、454、456以及458亦可設置於控制電路410內部的其他電路模組中或是設置於控制電路410之外。再者,映射單元452、454、456以及458的詳細操作與功能已於第2圖所代表的實施例中闡述過,在此便不贅述。
於多通道固態硬碟機400初始化時,處理單元420會分別檢查快閃記憶體401a、401b、401c以及401d之所有區塊是否能正常運作,以分別產生對應於快閃記憶體401a、401b、401c以及401d之缺陷區塊列表TE、TF、TG以及TH。通常來說,快閃記憶體401a、401b、401c以及401d於製造之初(亦即出廠時)就可能已帶有缺陷區塊,因此在每一區塊中的特定位置會被填入非0xff的值,用以指出該區塊為缺陷區塊。再者,多通道固態硬碟機400在實際使用的過程中,也會因為各種操作不當或快閃記憶體本身儲存單元先天上的有限存取次數而產生新的缺陷區塊,處理單元420會在特定位置標上非0xff的值。因此,處理單元420會檢查每一個區塊是否為缺陷區塊來產生缺陷區塊列表TE、TF、TG以及TH或者自快閃記憶體401a、401b、401c以及401d載入已產生的缺陷區塊列表TE、TF、TG以及TH,並且將缺陷區塊列表TE、TF、TG以及TH儲存於儲存單元430中。接著,處理單元420會依據缺陷區塊列表TE、TF、TG以及TH的資訊,選擇其中一缺陷區塊列表TE、TF、TG以及TH所對應之快閃記憶體的缺陷區塊狀態來作為上述發明內容中的映射結果產生基準。此處假設處理單元所選定的基準為快閃記憶體401b。
於此,處理單元420找出缺陷區塊列表TF所有的缺陷區塊,並依據這(些)缺陷區塊,將快閃記憶體401a、401c以及401d的對應於該(些)缺陷區塊且為可正常運作之良好區塊分別作為快閃記憶體401a、401c以及401d的置換區塊。請注意,此處所謂的區塊對應係源自於快閃記憶體401a、401b、401c以及401d間的冗餘關係。此外,若快閃記憶體401a、401c以及401d中對應於快閃記憶體401b之缺陷區塊的關聯區塊亦為缺陷區塊時,則其不會被使用來作為快閃記憶體401a、401c以及401d的置換區塊。當處理單元420依據缺陷區塊列表TF來分別決定出快閃記憶體401a、401c以及401d的置換區塊後,接著,處理單元420會再依據缺陷區塊列表TE、TG以及TH與每一置換區塊來分別產生相對應之映射結果ME、MG以及MH,其中,映射結果是指快閃記憶體中之缺陷區塊的位址與置換區塊之位址的映射關係,其可能以映射表(mapping table)的形式寫入儲存單元430中,因此,在不違背本發明方法的精神下,由處理單元420直接至儲存單元430讀取這些快閃記憶體的映射表以執行位址轉換亦是可行的。此外,於本實施例中,映射單元452、454、456以及458係透過接線式(hardwired)映射來進行置換區塊之實體位址與缺陷區塊之實體位址間的映射,然而,此非本發明之唯一限制,任何透過硬體手段來完成映射的技術皆應屬本發明之範疇。
簡言之,一快閃記憶體中的所有置換區塊,將會分別被對應到該快閃記憶體已存在的缺陷區塊,以產生該快閃記憶體之映射結果。最後,處理單元420將會依據映射結果ME、MG以及MH來分別設定映射單元452、456、458,使得之後的存取操作中不會存取到那些已存在的缺陷區塊,而是透過映射單元的幫助將資料儲存於相對應的置換區塊中。於本實施例中,由於映射單元的存在,使得處理單元420不用另外進行置換區塊與缺陷區塊間的位址轉換,因而得以減少處理單元420的工作負擔。當映射結果順利產生後,往後,多通道固態硬碟機400的資料存取便會由控制電路410參考儲存單元中的缺陷區塊列表F來執行。舉例來說,當資料寫入時,控制電路410接收到該資料的邏輯區塊位址(Logic Block Address,LBA)後,首先將其轉換為實體區塊位址,接著會參考缺陷區塊列表F來決定該實體區塊位址是否為可用的實體區塊位址(舉例來說,於第1圖代表的實施例中,區塊2與區塊5所對應的實體區塊位址就是不可用的),若為可用,則將該實體區塊位址指定給該邏輯區塊位址;否則的話,則另指定一實體區塊位址給該資料的邏輯區塊位址。接著,依據資料分割的原理,該資料的段落會被分別寫入至快閃記憶體401a、401b、401c以及401d中的良好區塊或是置換區塊,因此,處理單元420僅需依據快閃記憶體的缺陷區塊位址來發出一指定的實體區塊位址,映射單元接收該實體區塊位址會視情況進行位址映射以避免資料可能寫入到該實體區塊位址所指向的缺陷區塊。於資料讀取的時候,便透過實體區塊位址與邏輯區塊位址的關係來將資料分別自快閃記憶體401a、401b、401c以及401d取出。由於映射單元已經將快閃記憶體401a、401c以及401d的缺陷區塊利用置換區塊來取代,因此控制電路410在進行資料存取的時候,完全不需考慮快閃記憶體401a、401c以及401d的缺陷區塊,而僅需考慮快閃記憶體401b的缺陷區塊,並且避免將邏輯區塊位址指定至快閃記憶體401b的缺陷區塊的實體位址即可。
相較於先前技術的作法,本發明大幅減輕了處理單元的工作負擔,另一方面又避免快閃記憶體中無謂的儲存空間浪費,故對於採用資料分割技術之儲存裝置(例如多通道固態硬碟機)而言,本發明提供一個絕佳的缺陷區塊管理方法與相關控制電路。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100、400...多通道固態硬碟機
401a~401d...快閃記憶體
200、452~458...映射單元
310~340...步驟
410...控制電路
420...處理單元
430...儲存單元
442~448...錯誤校正碼處理單元
491~494...存取通道
第1圖係本發明方法的應用示意圖。
第2圖係本發明映射單元之實施例的示意圖。
第3圖係本發明方法之範例流程圖。
第4圖係應用本發明控制電路的固態硬碟機與本發明控制電路之實施例的示意圖。
400...多通道固態硬碟機
401a~401d...快閃記憶體
452~458...映射單元
410...控制電路
420...處理單元
430...儲存單元
442~448...錯誤校正碼處理單元
491~494...存取通道

Claims (14)

  1. 一種用以存取一儲存裝置的方法,該儲存裝置包含有複數個儲存單元分別對應複數個存取通道,每一儲存單元分別包含有複數個區塊,該複數個存取通道係於該儲存裝置進行一資料存取操作時同時動作,該複數個儲存單元包含有一第一儲存單元與至少一第二儲存單元,該方法包含有:依據該複數個儲存單元中無法正常操作之缺陷區塊(bad block)來產生分別對應至該複數個儲存單元之複數個缺陷區塊列表;依據該第一儲存單元所對應之一缺陷區塊列表所指出之至少一缺陷區塊,將每一第二儲存單元中對應於該缺陷區塊且可正常操作之一良好區塊(good block)設定為一置換區塊;依據每一第二儲存單元之一缺陷區塊列表與每一置換區塊來產生相對應之一映射結果;以及依據該第一儲存單元所對應之該缺陷區塊列表與每一第二儲存單元所對應之該映射結果來存取該儲存裝置。
  2. 如申請專利範圍第1項所述之方法,其中該儲存裝置係以資料分割方式(data striping)將資料儲存於該複數個儲存單元。
  3. 如申請專利範圍第1項所述之方法,其中依據每一第二儲存單元之該缺陷區塊列表與每一置換區塊來產生相對應之該映射結果的步驟包含有:將每一第二儲存單元中至少一缺陷區塊的位址映射至同一儲存單元中一置換區塊的位址以產生該映射結果。
  4. 如申請專利範圍第3項所述之方法,其中每一第二儲存單元中之該缺陷區塊的位址係透過一接線式(hardwired)映射方式而映射至同一儲存單元中之該置換區塊的位址。
  5. 如申請專利範圍第1項所述之方法,其中每一儲存單元係為一非揮發性記憶體。
  6. 如申請專利範圍第5項所述之方法,其中該非揮發性記憶體係為一快閃記憶體。
  7. 如申請專利範圍第1項所述之方法,其中該儲存裝置係為一多通道固態硬碟機(multi-channel solid state drive)。
  8. 一種用於存取一儲存裝置之控制電路,該儲存裝置包含有複數個儲存單元分別對應複數個存取通道,每一儲存單元分別包含有複數個區塊,該複數個存取通道係於該儲存裝置進行一資料存取操作時同時動作,該複數個儲存單元包含有一第一儲存單元與至少一第二儲存單元,該控制電路包含有:一處理單元,依據該複數個儲存單元中無法正常操作之缺陷區塊(bad block)來產生分別對應至該複數個儲存單元之複數個缺陷區塊列表;依據該第一儲存單元所對應之一缺陷區塊列表所指出之至少一缺陷區塊,將每一第二儲存單元中對應於該缺陷區塊且可正常操作之一良好區塊(good block)設定為一置換區塊;依據每一第二儲存單元之一缺陷區塊列表與每一置換區塊來產生相對應之一映射結果;一儲存單元,耦接於該處理單元,係用以儲存該第一儲存單元之該缺陷區塊列表;以及複數個映射單元,分別耦接於該處理單元以及該複數個儲存單元,用以依據該複數個映射結果進行以相對應之設定,其中該控制電路係利用該複數個映射單元與儲存於該儲存單元之該第一儲存單元所對應之該缺陷區塊列表來存取該複數個儲存單元。
  9. 如申請專利範圍第8項所述之控制電路,其中該控制電路係以資料分割方式(data striping)將資料儲存於該複數個儲存單元。
  10. 如申請專利範圍第8項所述之控制電路,其中該控制電路將每一第二儲存單元中至少一缺陷區塊的位址映射至同一儲存單元中一置換區塊的位址以產生該映射結果。
  11. 如申請專利範圍第10項所述之控制電路,其中該複數個映射單元係透過一接線式(hardwired)映射方式而將每一第二儲存單元中之該缺陷區塊的位址而映射至同一儲存單元中之該置換區塊的位址。
  12. 如申請專利範圍第8項所述之控制電路,其中該控制電路所控制之儲存單元係為非揮發性記憶體。
  13. 如申請專利範圍第12項所述之控制電路,其中該控制電路所控制之非揮發性記憶體係為快閃記憶體。
  14. 如申請專利範圍第8項所述之控制電路,其中該控制電路所控制之該儲存裝置係為一多通道固態硬碟機(multi-channel solid state drive)。
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