TWI408475B - Active device array substrate and fabricating mothod thereof - Google Patents

Abstract

An active device array substrate includes a substrate, scan lines, data lines, display units, scan signal transmission lines, a dielectric layer, a common line and a capacitor dielectric layer. Each display unit is electrically connected to two of the scan lines and one of the data line, respectively. Each display unit includes a first sub-pixel and a second sub-pixel. Two adjacent display units are electrically connected to the different data lines in the same row of the display units, respectively. Each scan signal transmission line is electrically connected to one of the scan lines, respectively. The dielectric layer covers the scan lines, data lines, a first and a second active devices of the first and the second sub-pixels. The common line is disposed between the dielectric layer and a first and a second pixel electrodes of the first and the second sub-pixels. The capacitor dielectric layer is disposed between the common line and the first and the second pixel electrodes.

Description

Active device array substrate and manufacturing method thereof

The present invention relates to an array substrate and a method of fabricating the same, and more particularly to an active device array substrate and a method of fabricating the same.

Generally, the liquid crystal display panel is mainly composed of an active device array substrate, a pair of substrates, and a liquid crystal layer sandwiched between the active device array substrate and the opposite substrate, wherein the active device array substrate can be divided into display regions. (display region) and non-display region, wherein a plurality of pixel units arranged in an array are arranged on the display area, and each pixel unit includes a thin film transistor (TFT) and a thin film transistor Connected pixel electrode. In addition, a plurality of scan lines and data lines are disposed in the display area, and the thin film transistors of each pixel unit are electrically connected to the corresponding scan lines and data lines. In the non-display area, a signal line, a source driver, and a gate driver are disposed.

When the liquid crystal display panel is to display an image screen, it must sequentially open each column of pixels in the display panel through the gate driver, and each column of pixels will correspondingly receive the data provided by the source driver during the opening time. Voltage. In this way, the liquid crystal molecules in each column of pixels are properly arranged according to the data voltage they receive.

However, as the resolution of the liquid crystal display panel increases, the liquid crystal display must increase the resolution by increasing the number of gate drivers and source drivers, and the number of gate drivers and source drivers increases. Make the area of the non-display area (or border) larger. For the above reasons, the production cost of the liquid crystal display increases with the number of gate drivers and source drivers, and the frame size is also increasing. If the number of gate drivers and/or source drivers can be reduced, it is easy to solve the problem that the cost cannot be reduced and to make a narrow frame, that is, a product with a small non-display area.

The invention provides an active device array substrate, which can greatly reduce the parasitic capacitance between the data line and the common line through the design of the dielectric layer.

The invention also provides a method for manufacturing an active device array substrate, wherein the common line can also serve as a reflective layer, which can effectively reduce the process steps.

The invention provides an active device array substrate, which comprises a substrate, a plurality of scan lines, a plurality of data lines, a plurality of display units, a plurality of scan signal transmission lines, a dielectric layer, a common line and a capacitor dielectric layer. . The scan line is disposed on the substrate. The data lines are disposed on the substrate and interleaved with the scan lines to define a plurality of display areas. The display unit is disposed in the display area, and each display unit is electrically connected to two of the scan lines and one of the data lines. Each display unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first active component and a first pixel electrode electrically connected to the first active component. The second sub-pixel includes a second active component and a second pixel electrode electrically connected to the second active component. The first active component and the second active component are electrically connected to different scan lines, and the second active component is electrically connected to the corresponding data line through the first active component. In the display unit of the same column, the two adjacent display units are electrically connected to different data lines respectively. Each scan signal transmission line is electrically connected to one of the scan lines. The dielectric layer covers the scan line, the data line, the first active component, and the second active component, and the first pixel electrode and the second pixel electrode are disposed on the dielectric layer. The common line is disposed between the first pixel electrode and the dielectric layer and between the second pixel electrode and the dielectric layer. The capacitor dielectric layer is disposed between the first pixel electrode and the common line and between the second pixel electrode and the common line.

In an embodiment of the invention, the extending direction of the scan line is substantially perpendicular to the extending direction of the data line.

In an embodiment of the invention, the number of scan signal transmission lines is less than or equal to the number of data lines.

In an embodiment of the invention, each of the scan signal transmission lines is located between two adjacent data lines.

In an embodiment of the invention, the extending direction of the scanning signal transmission line is substantially parallel to the extending direction of the data line.

In an embodiment of the invention, each of the scan signal transmission lines includes a first conductive pattern and a second conductive pattern. The second conductive pattern is electrically connected to the first conductive pattern, wherein the second conductive pattern is staggered with the scan lines.

In one embodiment of the invention, the dielectric layer has a thickness between 1.5 micrometers (μm) and 4 micrometers (μm).

In an embodiment of the invention, the dielectric layer has a plurality of bumps, and the common lines cover the bumps.

In an embodiment of the invention, the material of the common line includes a reflective material.

In an embodiment of the invention, the common line is above the scan signal transmission line.

In an embodiment of the invention, the first pixel electrode and the second pixel electrode are partially overlapped with the common line.

In an embodiment of the present invention, the active device array substrate further includes a protective layer, wherein the protective layer covers the scan line, the data line, the first active device, and the second active device, and one of the protective layer and the dielectric layer The bottom surface is in contact.

The present invention also provides a method of fabricating an active device array substrate comprising the steps described below. First, a plurality of scan lines, a plurality of data lines, a plurality of active elements, and a plurality of scan signal transmission lines are formed on a substrate. Next, a dielectric layer is formed to cover the scan lines, the data lines, the active elements, and the scan signal transfer lines. A common line is formed on the dielectric layer. Then, a capacitor dielectric layer is formed on the common line and the dielectric layer. Finally, a plurality of pixel electrodes are formed on the dielectric layer and the capacitor dielectric layer, wherein each of the pixel electrodes is electrically connected to one of the active elements.

In an embodiment of the invention, the method for manufacturing the scan line, the data line, the active device, and the scan signal transmission line includes: first, forming a plurality of scan lines on the substrate, and plurality of gates electrically connected to the scan lines. a pole and a first conductive pattern. Next, a gate insulating layer is formed on the substrate to cover the scan lines, the gates, and the first conductive pattern. Then, a plurality of semiconductor patterns are formed on the gate insulating layer. Finally, a plurality of data lines, a plurality of sources electrically connected to the data lines, a plurality of drain electrodes, and a second conductive pattern electrically connected to the first conductive pattern are formed on the gate insulating layer, wherein the gate and the semiconductor are formed The pattern, the source and the drain constitute an active element, and the first conductive pattern and the second conductive pattern constitute a scan signal transmission line.

In an embodiment of the invention, the method for fabricating the active device array substrate further includes forming a protective layer to cover the data line, the active device, and the scan signal transmission line before forming the dielectric layer.

In one embodiment of the invention, the dielectric layer has a thickness between 1.5 micrometers (μm) and 4 micrometers (μm).

In an embodiment of the invention, the method for fabricating the active device array substrate further includes forming a plurality of bumps on a top surface of the dielectric layer.

Based on the above, the active device array substrate of the present invention is designed to use a common line of reflective materials, so that the common line can also be regarded as a reflective layer, which can reduce the manufacturing steps and reduce the production cost. In addition, the dielectric layer of the present embodiment is designed to increase the distance between the common line and the data line to achieve a capacitance value that reduces parasitic capacitance. Furthermore, since the active device array substrate of the present invention has a common line that can be coupled to the pixel electrode to be a storage capacitor, it contributes to an increase in the capacitance value of the storage capacitor.

The above described features and advantages of the present invention will be more apparent from the following description.

1A is a top plan view of an active device array substrate according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along line I-I of Fig. 1A. Fig. 1C is a schematic cross-sectional view taken along line II-II of Fig. 1A. Figure 1D is a schematic cross-sectional view taken along line III-III of Figure 1A. Referring to FIG. 1A and FIG. 1B , the active device array substrate 100 of the present embodiment includes a substrate 110 , a plurality of scan lines 120 , a plurality of data lines 130 , a plurality of display units 140 , and a plurality of scan signal transmission lines 150 . The dielectric layer 160, a common line 170, and a capacitor dielectric layer 180.

In detail, the scan line 120 and the data line 130 are all disposed on the substrate 110 , wherein the extending direction of the scan line 120 is substantially perpendicular to the extending direction of the data line 130 . In the present embodiment, the data line 130 and the scan line 120 are interleaved to define a plurality of display areas R, and the display unit 140 is disposed in the display area R. In particular, in the embodiment, each display unit 140 is electrically connected to two scanning lines 120 and one of the data lines 130, respectively. Each display unit 140 includes a first sub-pixel 140a and a second sub-pixel 140b. The first sub-pixel 140a includes a first active element 142a and a first pixel electrode 144a electrically connected to the first active element 142a. The second sub-pixel 140b includes a second active element 142b and a second pixel electrode 144b electrically connected to the second active element 142b. Referring to FIG. 1A and FIG. 1C simultaneously, the active device 142 (including the first active component 142a and the second active component 142b) of the embodiment is, for example, a gate G, a gate insulating layer GI, a semiconductor pattern 143, and an ohmic contact. A thin film transistor (TFT) composed of a layer 145, a source S, and a drain D.

Further, the first active component 142a and the second active component 142b of the embodiment are electrically connected to different scan lines 120, and the second active component 142b is electrically connected to the corresponding data line 130 through the first active component 142a. . In other embodiments, the first active component 142a is electrically connected to the corresponding data line 130 through the second active component 142a. In other words, in the active device array substrate 100 of the present embodiment, not all of the active devices 142 are electrically connected to the data line 130. Of course, in other feasible embodiments, each active component 142 can also be electrically connected to the corresponding data line 130. In addition, in the display unit 140 of the same column, the two adjacent display units 140 are electrically connected to different data lines 130, respectively.

In short, the active device array substrate 100 of the present embodiment is designed such that two adjacent first sub-pixels 140a and second sub-pixels 140b are electrically connected to the same data line 130, thereby enabling the required The number of data lines 130 is halved, thereby reducing the number of source drivers (not shown) used. Here, the design of the pixel structure is a so-called Half Source Driving (HSD) architecture.

Referring to FIG. 1A and FIG. 1B simultaneously, in the embodiment, each of the scan signal transmission lines 150 is electrically connected to one of the scan lines 120. In detail, each of the scan signal transmission lines 150 of the embodiment is located between the adjacent two data lines 130, and the extending direction of the scan signal transmission lines 150 is substantially parallel to the extending direction of the data lines 130. In other words, the design of the scan signal transmission line 150 of the present embodiment can effectively reduce the number of fan-out traces at the end of the scan line 120. The design of the scan signal transmission line 150 described herein is a wiring structure of a Tracking Gate-line in Pixel (TGP).

Further, each of the scan signal transmission lines 150 of the embodiment includes a first conductive pattern 152 and a second conductive pattern 154, and the first conductive pattern 152 is formed simultaneously when the scan line 120 is formed, and the second conductive The pattern 154 is formed simultaneously when the data line 130 is fabricated. The second conductive pattern 154 is electrically connected to the first conductive pattern 152 , wherein the second conductive pattern 154 is interdigitated with the scan line 120 , that is, the second conductive pattern 154 spans the scan line 120 . In other words, each of the scan signal transmission lines 150 of the embodiment is electrically connected to one of the scan lines 120 and electrically insulated from the other scan lines 120. It is worth mentioning that the number of scan signal transmission lines 150 may be less than or equal to the number of data lines 130, which is not limited herein.

Referring to FIG. 1A and FIG. 1C simultaneously, the dielectric layer 160 of the present embodiment covers the scan line 120, the data line 130, the active device 142 (including the first active device 142a and the second active device 142b), and the pixel electrode 144 The first pixel electrode 144a and the second pixel electrode 144b are disposed on the dielectric layer 160. In particular, in the present embodiment, the thickness of the dielectric layer 160 is, for example, between about 1.5 micrometers (μm) and about 4 micrometers (μm). In addition, the dielectric layer 160 has a plurality of bumps 162, and the bumps 162 are, for example, surface microstructures formed on the dielectric layer 160.

Referring to FIG. 1A , FIG. 1B and FIG. 1D , the common line 170 is disposed between the first pixel electrode 144 a and the dielectric layer 160 and between the second pixel electrode 144 b and the dielectric layer 160 . The common line 170 of the present embodiment is, for example, a common-ring, and belongs to different film layers from the scan line 120 and the data line 130. In particular, the common line 170 of the present embodiment is located above the scan signal transmission line 150, and the common line 170 covers the bump 162. The first pixel electrode 144a and the second pixel electrode 144b partially overlap the common line 170, respectively, and the material of the common line 170 is, for example, a reflective material.

In the present embodiment, since the active device array substrate 100 is designed to use the common line 170 of the reflective material, the common line 170 can also be regarded as a reflective layer. It should be noted that, in this embodiment, the position where the common line 170 is disposed can be regarded as a reflective area, for example, the area where the common line 170 overlaps the pixel electrode 144, and the position where the common line 170 is not disposed is visible. A penetrating region is, for example, a region where the pixel electrode 144 does not overlap the common line 170. In other words, each sub-pixel (for example, the first sub-pixel 140a or the second sub-pixel 140b) may have both a penetrating region and a reflecting region. Therefore, when the active device array substrate 100 of the present embodiment is combined with a pair of substrates (not shown) and a liquid crystal layer (not shown) to form a display panel (not shown), the display panel can have reflection at the same time. Light and the function of penetrating the light source, this is a transflective display panel (Transflective LCD, TR-LCD). Moreover, since the thickness of the dielectric layer 160 of the embodiment is, for example, between about 1.5 micrometers (μm) and about 4 micrometers (μm), the distance between the common line 170 and the data line 130 can be increased. The power consumption caused by reducing the capacitance between the common line 170 and the data line 130 is achieved.

It should be noted that the present invention does not limit the form of the common line 170, although the common line 170 mentioned herein is embodied as a ring-shaped common line, and a part of the common line 170 is located above the data line 130, but other In the embodiment not shown, the common line 170 may also be strip, L-shaped, U-shaped, H-shaped or other suitable shape, which can reduce the capacitance between the common line 170 and the signal line (data line and scan line). The power consumption is caused by the power consumption; or the common line 170 may not be disposed above the data line 130 to reduce the power consumption caused by the capacitance between the common line 170 and the data line 130; or the common line 170 extends to the first part. The pixel electrode 144a and the portion of the second pixel electrode 144b directly underneath to increase the area of the reflective region of the transflective display panel, and also increase the storage capacitance between the pixel electrode 144 and the common line 170. The value of the capacitor does not cause a loss of aperture ratio. In short, the shape of the common line 170 can be varied according to different usage requirements, and the structural design of the common line 170 illustrated in FIG. 1A is only for illustration, so that the general knowledge in this field can be The invention is not intended to limit the scope of the invention as intended.

Referring to FIG. 1A and FIG. 1D simultaneously, in the embodiment, the capacitor dielectric layer 180 is disposed between the first pixel electrode 144a and the common line 170 and between the second pixel electrode 144b and the common line 170. The pixel electrode 144 (including the first pixel electrode 144a and the second pixel electrode 144b) can be coupled to the common line 170 to form a storage capacitor Cst, which helps to increase the capacitance value of the storage capacitor.

In addition, referring to FIG. 1A and FIG. 1C, the active device array substrate 100 of the present embodiment further includes a protective layer 190, wherein the protective layer 190 covers the scan line 120, the data line 130, and the active device 142 (including the first active device 142a). And a second active component 142b), and the protective layer 190 is in contact with a bottom surface of the dielectric layer 160. It is worth mentioning that in the present embodiment, the dielectric layer 160 has at least one contact window 164 penetrating the protective layer 190, wherein the contact window 164 exposes the drain D of the active device 142, and the pixel electrode 144 passes through the contact window. The 164 is directly electrically connected to the drain D of the active component 142.

In short, since the present embodiment uses a half-source driving (HSD) pixel architecture in combination with the design of the scanning signal transmission line 150 (ie, the wiring structure of the TGP), the number of data lines 130 can be effectively reduced and effectively By reducing the number of fan-out traces at the end of the scan line 120, narrow boundary and borderless design requirements can be easily achieved. In addition, the design of the dielectric layer 160 of the present embodiment can increase the distance between the common line 170 and the data line 130, and can reduce the power consumption caused by the capacitance between the common line 170 and the data line 130. Furthermore, since the active device array substrate 100 of the present embodiment has the common line 170 that can be coupled to the pixel electrode 144 to store the capacitor, it contributes to increasing the capacitance value of the storage capacitor.

Only the structure of the active device array substrate 100 of the present invention will be described above, and the method of manufacturing the active device array substrate 100 of the present invention will not be described. In this regard, the active device array substrate 100 of FIG. 1A will be exemplified below, and the manufacturing method of the active device array substrate of the present invention will be described in detail with reference to FIGS. 2A to 2F.

2A to 2F are schematic flow charts showing a method of manufacturing an active device array substrate according to an embodiment of the present invention. According to the manufacturing method of the active device array substrate according to the embodiment, referring to FIG. 1A and FIG. 2A, a plurality of scan lines 120, a plurality of data lines 130, a plurality of active elements 142, and a plurality of scans are formed on a substrate 110. Signal transmission line 150. The manufacturing method of the scan line 120, the data line 130, the active device 142, and the scan signal transmission line 150 includes the following steps: First, a plurality of scan lines 120 are formed on the substrate 110, and a plurality of scan lines 120 are electrically connected to the scan lines 120. The gate G and the first conductive pattern 152. That is, the first conductive pattern 152 is formed simultaneously when the scan line 120 is formed. Next, a gate insulating layer GI is formed on the substrate 110 to cover the scan line 120, the gate G, and the first conductive pattern 152.

Then, a plurality of semiconductor patterns 143 and an ohmic contact layer 145 over the semiconductor pattern 143 are formed on the gate insulating layer GI. Finally, a plurality of data lines 130, a plurality of source electrodes S electrically connected to the data lines 130, a plurality of drain electrodes D, and a second conductive pattern electrically connected to the first conductive patterns 152 are formed on the gate insulating layer GI. 154. That is, the second conductive pattern 154 is formed simultaneously when the data line 130 is fabricated. In particular, in the present embodiment, the gate G, the semiconductor pattern 143, the source S, and the drain D constitute the active device 142, and the first conductive pattern 152 and the second conductive pattern 154 constitute the scan signal transmission line 150.

Next, referring to FIG. 2B, a protective layer 190 is formed to cover the data line 130 (please refer to FIG. 1A), the active device 142, and the scan signal transmission line 150. Also, the scan signal transmission line 150 is separated from the scan line 120.

Next, referring to FIG. 2C, a dielectric layer 160 is formed to cover the scan line 120, the data line 130, the active device 142, and the scan signal transfer line 150. In this embodiment, the thickness of the dielectric layer 160 is, for example, between about 1.5 micrometers (μm) and about 4 micrometers (μm), and a plurality of bumps 162 are formed on a top surface of one of the dielectric layers 160. The bumps 162 are, for example, surface microstructures formed on the dielectric layer 160. Moreover, the dielectric layer 160 of the present embodiment has at least one contact window 164 extending through the protective layer 190, wherein the contact window 164 exposes the drain D of the active element 142. The dielectric layer 160 may be a single layer or a multilayer structure, and the material thereof comprises an organic material (for example: photoresist, enzocyclobutane (BCB), cycloolefin, polyfluorene). Imines, polyamines, polyesters, polyalcohols, polyethylene oxides, polyphenyls, resins, polyethers, polyketones, or other suitable materials, or combinations thereof, Inorganic materials (e.g., tantalum nitride, hafnium oxide, niobium oxynitride, other suitable materials, or combinations thereof), other suitable materials, or combinations thereof.

Then, referring to FIG. 1A and FIG. 2D, a common line 170 is directly formed on the dielectric layer 160, wherein the common line 170 is, for example, a common-ring. In particular, the common line 170 of the present embodiment is located above the scan signal transmission line 150, and the common line 170 covers the bump 162. In addition, the common line 170 may be a single layer or a multilayer structure, and the material thereof is, for example, a reflective material, for example, gold, silver, copper, aluminum, titanium, tantalum, tungsten, molybdenum, the above alloy, the above oxide, the above Nitride, other suitable compounds, other suitable materials, or combinations thereof.

Since the present embodiment is a common line 170 using a reflective material, the common line 170 can also be regarded as a reflective layer. Therefore, in this embodiment, the manufacturing process of the conventional reflective layer can be omitted, and the production cost can be effectively reduced.

It is worth mentioning that in the present embodiment, the position where the common line 170 is disposed can be regarded as a reflection area, and the position where the common line 170 is not provided can be regarded as a penetration area. Moreover, since the thickness of the dielectric layer 160 of the embodiment is, for example, between about 1.5 micrometers (μm) and about 4 micrometers (μm), the distance between the common line 170 and the data line 130 can be increased. Achieve the effect of reducing the capacitance value and power consumption.

Then, referring to FIG. 2E, a capacitor dielectric layer 180 is directly formed on the common line 170 and the dielectric layer 160.

Finally, please refer to 2F, in the dielectric layer 160 and the capacitor dielectric layer 180 A plurality of pixel electrodes 144 are directly formed on the pixel electrode 144, wherein each of the pixel electrodes 144 is electrically connected to the drain D of one of the active devices 142 through the contact window 164, and the capacitor dielectric layer 180 is located at the pixel electrode 144. Between lines 170. In particular, in the present embodiment, the pixel electrode 144 can be coupled to the common line 170 to form a storage capacitor Cst, which helps to increase the capacitance value of the storage capacitor. So far, the fabrication of the active device array substrate 100 has been completed.

In summary, since the present invention adopts a half source driving (HSD) pixel structure with a scan signal transmission line design (ie, a TGP wiring structure), the number of data lines can be effectively reduced and the scanning can be effectively reduced. The number of fan-out traces at the end of the line makes it easy to achieve narrow boundaries and borderless design requirements. In addition, the active device array substrate of the present invention is designed to use a common line of reflective materials, so that the common line can also be regarded as a reflective layer, which can reduce the manufacturing steps and reduce the production cost. Furthermore, the design of the dielectric layer of the present invention can increase the distance between the common line and the data line, and can reduce the power consumption caused by the capacitance between the common line and the data line. In addition, since the active device array substrate of the present invention has a common line that can be coupled to the pixel electrode to be a storage capacitor, it contributes to an increase in the capacitance value of the storage capacitor.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Active component array substrate

110‧‧‧Substrate

120‧‧‧ scan line

130‧‧‧Information line

140‧‧‧Display unit

140a‧‧‧First subpixel

140b‧‧‧Second subpixel

142‧‧‧Active components

142a‧‧‧First active component

142b‧‧‧Second active component

143‧‧‧ semiconductor pattern

144‧‧‧ pixel electrodes

144a‧‧‧first pixel electrode

144b‧‧‧second pixel electrode

145‧‧ ohmic contact layer

150‧‧‧ scan signal transmission line

152‧‧‧First conductive pattern

154‧‧‧Second conductive pattern

160‧‧‧ dielectric layer

162‧‧‧Bumps

164‧‧‧Contact window

170‧‧‧Common line

180‧‧‧Capacitive dielectric layer

190‧‧‧Protective layer

Cst‧‧‧ storage capacitor

D‧‧‧汲

G‧‧‧ gate

GI‧‧‧ brake insulation

R‧‧‧ display area

S‧‧‧ source

1A is an active device array substrate according to an embodiment of the invention A schematic view of the top.

Fig. 1B is a schematic cross-sectional view taken along line I-I of Fig. 1A.

Fig. 1C is a schematic cross-sectional view taken along line II-II of Fig. 1A.

Figure 1D is a schematic cross-sectional view taken along line III-III of Figure 1A.

2A to 2F are schematic flow charts showing a method of manufacturing an active device array substrate according to an embodiment of the present invention.

100. . . Active device array substrate

120. . . Scanning line

130. . . Data line

140. . . Display unit

140a. . . First subpixel

140b. . . Second subpixel

142. . . Active component

142a. . . First active component

142b. . . Second active component

143. . . Semiconductor pattern

144. . . Pixel electrode

144a. . . First pixel electrode

144b. . . Second pixel electrode

150. . . Scanning signal transmission line

152. . . First conductive pattern

154. . . Second conductive pattern

162. . . Bump

170. . . Common line

D. . . Bungee

G. . . Gate

R. . . Display area

S. . . Source

Claims (17)

An active device array substrate includes: a substrate; a plurality of scan lines disposed on the substrate; a plurality of data lines disposed on the substrate and interleaved with the scan lines to define a plurality of display areas; The display unit is disposed in the display areas, and each of the display units is electrically connected to the two scan lines and one of the data lines, and each of the display units includes: a first sub-pixel, including a first active component, and a first pixel electrode electrically connected to the first active component; a second sub-pixel comprising a second active component and a second pixel electrode electrically connected to the second active component, the first An active component and the second active component are respectively electrically connected to different scan lines, and the second active component is electrically connected to the corresponding data line through the first active component, and in the display unit of the same column, two phases The adjacent display units are electrically connected to different data lines respectively; a plurality of scanning signal transmission lines, each of which is electrically connected to one of the scanning lines; a dielectric layer covering The scan lines, the data lines, the first active elements, and the second active elements, and the first pixel electrodes and the second pixel electrodes are disposed on the dielectric layer; a common line And disposed between the first pixel electrode and the dielectric layer and between the second pixel electrode and the dielectric layer; and a capacitor dielectric layer disposed on the first pixel electrode and the common line It And between the second pixel electrode and the common line. The active device array substrate according to claim 1, wherein the scanning lines extend in a direction substantially perpendicular to an extending direction of the data lines. The active device array substrate according to claim 1, wherein the number of the scan signal transmission lines is less than or equal to the number of the data lines. The active device array substrate according to claim 1, wherein each of the scanning signal transmission lines is located between adjacent two data lines. The active device array substrate according to claim 1, wherein the scanning signal transmission lines extend in a direction substantially parallel to the extending direction of the data lines. The active device array substrate of claim 1, wherein each of the scan signal transmission lines comprises: a first conductive pattern; and a second conductive pattern electrically connected to the first conductive pattern, wherein the first The two conductive patterns are interlaced with the scan lines. The active device array substrate of claim 1, wherein the dielectric layer has a thickness of between 1.5 micrometers and 4 micrometers. The active device array substrate of claim 1, wherein the dielectric layer has a plurality of bumps, and the common line covers the bumps. The active device array substrate according to claim 1, wherein the material of the common line comprises a reflective material. Active element array base as described in claim 1 a board, wherein the common line is located above the scan signal transmission lines. The active device array substrate according to claim 1, wherein the first pixel electrodes and the second pixel electrodes respectively overlap the common line portion. The active device array substrate of claim 1, further comprising a protective layer, wherein the protective layer covers the scan lines, the data lines, the first active elements, and the second active elements, And the protective layer is in contact with a bottom surface of the dielectric layer. A method for manufacturing an active device array substrate includes: forming a plurality of scan lines, a plurality of data lines, a plurality of active elements, and a plurality of scan signal transmission lines on a substrate, wherein the scan signal transmission lines and the scan lines Separating; forming a dielectric layer to cover the scan lines, the data lines, the active elements, and the scan signal transmission lines; forming a common line directly on the dielectric layer; and the common line and the Forming a capacitor dielectric layer directly on the dielectric layer; and forming a plurality of pixel electrodes directly on the dielectric layer and the capacitor dielectric layer, and the capacitor dielectric layer is located on the pixel electrodes and the common line And wherein each of the pixel electrodes is electrically connected to one of the active elements. The method for manufacturing an active device array substrate according to claim 13, wherein the scan lines, the plurality of data lines, the plurality of active elements, and the plurality of scan signal transmission lines are formed by: forming on the substrate a plurality of scan lines, a plurality of gates electrically connected to the scan lines, and a first conductive pattern; Forming a gate insulating layer on the substrate to cover the scan lines, the gates and the first conductive pattern; forming a plurality of semiconductor patterns on the gate insulating layer; and forming a plurality of materials on the gate insulating layer a wire, a plurality of sources electrically connected to the data lines, a plurality of drains, and a second conductive pattern electrically connected to the first conductive pattern, wherein the gates, the semiconductor patterns, and the The source and the drains constitute the active components, and the first conductive pattern and the second conductive pattern constitute the scan signal transmission lines. The method for manufacturing an active device array substrate according to claim 13 , further comprising forming a protective layer to cover the data lines, the active elements, and the scan signals before forming the dielectric layer. line. The method of fabricating an active device array substrate according to claim 13, wherein the dielectric layer has a thickness of between 1.5 micrometers and 4 micrometers. The method for manufacturing an active device array substrate according to claim 13, further comprising forming a plurality of bumps on a top surface of the dielectric layer.