TWI408391B - Test apparatus and testing method - Google Patents

Abstract

Provided is a test apparatus that tests a device under test, comprising an upper sequencer that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test; a packet data sequence storing section that stores a data sequence included in each of a plurality of types of packets; and a lower sequencer that reads, from the packet data sequence storing section, a data sequence of a packet designated by the upper sequencer and generates a test data sequence used for testing the device under test.

Description

Test device and test method

The invention relates to a test device and a test method.

In the test apparatus, a data (test vector) indicating a waveform of a test signal and an expected value is obtained by, for example, simulating a model created in a design stage of a component to be tested ( Generated by wave form dump. For example, the test vector can be generated by dumping a waveform obtained by simulating a model representing a netlist level of an internal circuit in accordance with a connection relationship between terminals.

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2001-67395

Moreover, in recent years, in the simulation of a device, a logical design model of a transaction level of an action is expressed in units of a series of exchanges (transactions) between functional blocks. However, in simulations using such models, it is difficult to make test vectors used in previous test devices.

In addition, in recent years, the scale of components has been continuously advanced. Therefore, the test vectors used to test such components have also become bulky, making it difficult to store test vectors in previous test devices.

Moreover, in recent years, the non-deterministic movement of the signal output cycle is not fixed, or the output value changes depending on some states. The components made increase. Therefore, previous test devices using content-determined test vectors are difficult to test for such components.

In order to solve the above problems, a first aspect of the present invention provides a test apparatus and a test method, the test apparatus testing a device under test, and comprising: an acquisition unit that simulates an environment based on an operation of the element to be tested, And obtaining a packet sequence for communication with the device under test; the packet communication program generating unit generates a packet communication program for testing based on the packet sequence, and is executed by the testing device and performed with the device under test The communication of the packet included in the packet sequence; and the testing unit executes the packet communication program to perform packet communication with the device under test for testing.

Further, the summary of the above invention does not recite all of the essential features of the invention. Moreover, the subcombination of these feature groups can also be an invention.

The above described features and advantages of the present invention will be more apparent from the following description.

Hereinafter, the present invention will be described by way of embodiments of the invention, but the following embodiments do not limit the invention of the claims. Further, all of the combinations of the features described in the embodiments are not necessarily required for the solution of the invention.

FIG. 1 is a view showing the configuration of the test apparatus 100 of the present embodiment and the device under test 500. Test device 100 is with at least one component under test Packet communication is performed between 500 to test the component under test 500. That is, the test apparatus 100 tests the tested component 500 by transmitting a packet to the device under test 500 and receiving the packet from the device under test 500.

The test apparatus 100 includes a simulator 200, a conversion section 300, and a test section 400. The simulator 200 simulates the action of the device under test 500 by a simulation environment 600. The simulation environment 600 includes a device simulation model 610 that is fabricated at the design stage of the component under test 500. As an example, the component simulation model 610 describes the internal actions of the unit representation of a series of exchanges (transactions) between functional blocks at the transaction level.

The conversion unit 300 generates a packet communication program for testing the test element 500 to be executed by the test device 100 based on the simulation environment 600 simulating the operation of the device under test 500. The conversion unit 300 compiles and stores the generated packet communication program for testing in the test unit 400. Further, the simulator 200 and the conversion unit 300 may be realized by a computer such as a workstation provided outside the test apparatus body including the test unit 400.

The test unit 400 executes the test packet communication program generated by the conversion unit 300, and performs packet communication with the device under test 500 to test the device under test 500. In more detail, the test unit 400 transmits a packet containing the test data to the device under test 500, and receives the packet output from the device under test 500 corresponding thereto. Next, the testing unit 400 compares the data contained in the received packet with the expected data to determine that the data is Test component 500 is good or not.

Here, the packet communication program for testing includes a procedure and a packet function. The program describes the sequence of tests performed on the component under test 500. As an example, the program describes a test sequence that corresponds to the simulation order within the transaction units executed in the simulation environment 600. The program may, for example, describe a test sequence corresponding to the simulation order under the exchange unit of the packet.

The program contains the call of the packet function as the control sequence. In addition, the program includes a conditional branch, an unconditional branch, and a control statement that calls a subroutine call of another program as a test sequence.

Moreover, the program can process variables. The variable can store the data column in the packet instead of the value obtained according to the arithmetic expression, the substitution formula, and the like in the program. As an example, a program can receive a transmission variable from a packet function.

The packet function contains the data column of the packet and the command column used to generate the data column. The packet communication program for testing can include a variety of packet functions. As an example, the packet communication program for testing may include various packet functions for generating write packets, read packets, and idle packets.

Fig. 2 shows the hierarchical structure of the packet communication program for testing according to the present embodiment. The packet communication program for testing includes, for example, one or more programs. Each program contains one or more packet lists.

The packet list contains a series of packets that communicate with the component under test 500. As an example, the packet list includes an instruction column, and a variable for sequentially invoking communication with the device under test 500. A plurality of packet functions corresponding to the plurality of packets, the variables being used to receive and transmit the individual data changed for each packet with the packet function.

The package contains multiple pieces of information. As an example, a packet contains a fixed material regardless of the type of packet. As an example, the packet includes a start code and an end code of the packet.

Moreover, as an example, the packet may also contain shared material that is common to each packet type. As an example, the packet may also include a command indicating the type of packet as a shared material.

Moreover, as an example, the packet may also include individual data that is changed for each packet. As an example, the packet may also contain the address as well as the entity's profile. Individual data is specified by variables submitted by the program or the package list.

Additionally, as an example, the packet may also contain material that varies depending on the status. Moreover, as an example, the packet may also include a check code for detecting an error in the data column contained in the packet.

The packet communication program for such testing divides the content communicated with the device under test 500 into a program indicating the communication order of the packets and a hierarchy of the packet function indicating the contents of the data of each packet. Thereby, the test apparatus 100 can set the program to a description corresponding to the simulation order of the transaction unit executed in the simulation environment 600.

Moreover, the packet communication program for such testing allows the program to repeatedly call the same packet function. Therefore, according to the packet communication program for testing, a shared packet function can be used to describe the data columns repeatedly generated in the test. Therefore, the amount of data stored in the test apparatus 100 can be reduced.

FIG. 3 shows a first example of the configuration of the simulator 200 and the conversion unit 300 of the present embodiment. The simulator 200 of the first example simulates the operation of the device under test 500 at the transaction level. Such a simulated environment 600 includes a component simulation model 610 and a transaction stimulus (Transaction‧Stimulus) 620.

The component simulation model 610 contains a logical model of the tested component 500 that is described at the transaction level. The transaction source 620 specifies the reception and transmission of signals between the device under test 500 and the outside in a transaction unit.

The transaction source 620 may also be a description of the reception of the packet input from the external input to the device under test 500 and the packet outputted from the device under test 500 to the outside. The simulation environment 600 performs simulation using the component simulation model 610 and the transaction source 620, and determines whether the device under test 500 has performed an appropriate action.

The conversion unit 300 of the first example includes a packet definition data storage unit 310, an acquisition unit 320, and a packet communication program generation unit 330. The packet definition data storage unit 310 stores the packet definition data, and the packet definition data defines a data column included in each of the plurality of packets.

The acquisition unit 320 extracts a description of the transaction source 620 included in the simulation environment 600, and acquires a packet sequence for communication between the test device 100 and the device under test 500. As an example, the acquisition unit 320 specifies the type and order of the packets to be communicated between the test device 100 and the device under test 500 based on the packet definition data and based on the description of the transaction source 620. Further, as an example, the acquisition unit 320 specifies the material included in each packet based on the description of the transaction source 620.

The packet communication program generation unit 330 generates a test for performing communication between the test device 100 and the packet included in the packet sequence, which is executed by the test device 100, based on the packet sequence acquired by the acquisition unit 320. Packet communication program. As an example, the packet communication program generation unit 330 generates a program indicating the communication order of the packet based on the type and order of the packets indicated by the acquisition unit 320.

Further, as an example, the packet communication program generation unit 330 generates a packet function based on the type of the packet indicated by the acquisition unit 320. Further, as an example, the packet communication program generation unit 330 generates a variable value based on the data included in each packet indicated by the acquisition unit 320. According to such a conversion unit 300, a packet communication program for testing can be automatically generated based on the description of the transaction source 620 in the simulation environment 600.

FIG. 4 shows a second example of the configuration of the simulator 200 and the conversion unit 300 of the present embodiment. The simulator 200 and the conversion unit 300 of the second example have substantially the same configuration and function as those of the first example. Therefore, descriptions other than the differences will be omitted below.

The simulator 200 of the second example is included in the execution of the simulation and is capable of monitoring the monitoring point of the packet communicated by the device under test 500. The acquisition unit 320 of the second example monitors the packet communicated by the device under test 500 during the execution of the simulation of the simulation environment 600, and acquires a packet sequence for communication between the test device 100 and the device under test 500. As an example, the acquisition unit 320 indicates the type of the packet communicated by the device under test 500 monitored during the execution of the simulation based on the packet definition data. That is, for example, the acquisition unit 320 checks the monitored packet and the package. Which packet in the package definition data defines a match, and indicates the type of the packet to be monitored based on the result of the check.

According to the conversion unit 300, the packet communication program for testing can be automatically generated based on the packet communicated by the device under test in the simulation execution at the transaction level.

Fig. 5 shows a third example of the configuration of the simulator 200 and the conversion unit 300 of the present embodiment. The simulator 200 and the conversion unit 300 of the third example have substantially the same configurations and functions as those of the first example. Therefore, descriptions other than the differences will be omitted below.

The simulation environment 600 of the third example includes a component simulation model 610, a transaction source 620, and an adapter 630. The simulator 200 of the third example simulates the operation of the device under test 500 at a netlist level. The component simulation model 610 of the third example is described at the netlist level.

The adapter 630 performs the conversion between the transaction described in the transaction source 620 and the received signal received by the component simulation model 610 described in the netlist hierarchy. The simulation environment 600 performs simulation using the component simulation model 610, the transaction source 620, and the adapter 630, and determines whether the device under test 500 has performed an appropriate action.

The conversion unit 300 of the third example further includes a waveform dump memory unit 340. The waveform dump memory unit 340 obtains the result of the simulation of the execution of the simulation environment 600, and the obtained waveform of the input/output signal of the device under test 500 is dumped and memorized.

Further, the acquisition unit 320 of the third example is extracted from the test device 100 and tested according to the waveform dump stored in the waveform dump memory unit 340. A packet sequence that communicates between components 500. As an example, the acquisition unit 320 compares the waveform dumps stored in the waveform dump memory unit 340 with the data defined by the packet definition data to indicate the type of the packet communicated by the device under test 500.

According to the conversion unit 300, the packet communication program for testing can be automatically generated based on the waveform dump of the signal communicated by the device under test in the simulation execution at the transaction level.

FIG. 6 shows an example of the configuration of the test unit 400 of the present embodiment. The test unit 400 executes the packet communication program for testing (hereinafter also referred to as a test program) generated by the conversion unit 300, and tests at least one of the tested elements 500.

The test unit 400 includes an arithmetic processing unit 410, one or a plurality of execution processing units 420, one or more communication processing units 430, a test program storage unit 440, and a program supply unit 450. Each execution processing unit 420 is connected to the arithmetic processing unit 410 via, for example, a bus. Each communication processing unit 430 can be connected to any execution processing unit 420.

The arithmetic processing unit 410 processes the arithmetic expression in the test program. Each execution processing unit 420 indicates a packet list to be executed by each communication processing unit 430 connected to the execution processing unit 420 among the plurality of packet lists in the test program. Each of the communication processing units 430 and the corresponding device under test 500 sequentially communicates the packets included in the packet list specified by the corresponding execution processing unit 420.

As an example, the test unit 400 may include one arithmetic processing unit 410, eight execution processing units 420, and 256 communication processing units 430. at this time, As an example, 32 communication processing units 430 are connected to each of the eight execution processing units 420. The test unit 400 is not limited to such a connection configuration, and may be configured as another connection.

The test program storage unit 440 memorizes the test program. The program supply unit 450 loads the test program into the arithmetic processing unit 410, the execution processing unit 420, and the communication processing unit 430 before the test.

FIG. 7 shows an example of the configuration of the arithmetic processing unit 410 of the present embodiment, and one execution processing unit 420 and a communication processing unit 430 which are representative of the plurality of execution processing units 420 and the plurality of communication processing units 430. The arithmetic processing unit 410 includes a variable storage unit 412 and an arithmetic unit 414. Each execution processing unit 420 includes a flow control unit 426. Further, each communication processing unit 430 includes a packet list storage unit 432 and a packet communication unit 434. The packet list storage unit 432 is provided outside the packet communication unit 434, but may be provided inside the packet communication unit 434.

The program supply unit 450 extracts a plurality of packet lists each including a series of packets communicated by the corresponding communication processing unit 430 from the test program stored in the test program storage unit 440, and stores the package lists in the corresponding ones. The packet list storage unit 432 in the communication processing unit 430. Then, the program supply unit 450 generates a control program describing the control flow and supplies it to the flow control unit 426, which causes the plurality of packet lists extracted from the test program to be sequentially executed. Next, the program supply unit 450 generates a calculation program and supplies it to the calculation unit 414, which executes the calculation formula extracted from the test program.

The flow control unit 426 is based on the execution flow of the test program. The packet communication unit 434 in the communication processing unit 430 specifies the order in which each of the plurality of packet lists is executed. More specifically, the flow control unit 426 executes the control program supplied from the program supply unit 450, and indicates the plurality of package lists stored in the package list storage unit 432 for the packet communication unit 434 in the corresponding communication processing unit 430. The list of packets that should be executed next. As an example, the flow control unit 426 transmits the address in the packet list storage unit 432 of the packet list to be executed next to the packet communication unit 434.

Further, when the control program includes the arithmetic expression, the flow control unit 426 calls the calculation program for executing the arithmetic expression and causes the calculation unit 414 in the arithmetic processing unit 410 to execute the calculation program. Further, the flow control unit 426 indicates the packet list to be executed next based on the calculation result of the arithmetic expression of the arithmetic processing unit 410. At this time, the flow control unit 426 may wait for the indication of the next packet list until the calculation result of the arithmetic processing unit 410 is received, and select the indicated packet list based on the calculation result.

The packet list storage unit 432 stores a plurality of packet lists supplied from the program supply unit 450. The packet communication unit 434 performs a communication between the series of packets included in the packet list sequentially designated by the flow control unit 426 in the corresponding execution processing unit 420, and sequentially with the corresponding device under test 500. Corresponding tested component 500.

As an example, the packet communication unit 434 reads out the packet list from the address received from the flow control unit 426, and between the series of packets included in the read packet list and the corresponding tested component 500. Communicate in sequence. Moreover, the packet communication unit 434 will receive from the device under test 500. The data value included in the packet is transmitted as a variable value to the variable memory unit 412 in the arithmetic processing unit 410 via the flow control unit 426.

The variable storage unit 412 stores the data values received from the plurality of packet communication units 434 included in the plurality of communication processing units 430 as variable values. The calculation unit 414 executes the arithmetic expression included in the test program, and transmits the execution result to the flow control unit 426 in the plurality of execution processing units 420. Further, when the calculation unit includes the data value received from the device under test 500, the calculation unit 414 reads the variable value of the parameter as the arithmetic expression from the variable memory unit 412, and specifies the value of the parameter. Calculation. Further, the calculation unit 414 may transmit the data value included in the packet transmitted to the device under test 500 to the packet communication unit 434 as a variable value.

In the test unit 400, the arithmetic processing unit 410 of the upper side executes the arithmetic expression in the test program, and the flow control unit 426 and the packet communication unit 434 on the lower side perform flow control. According to the test unit 400, the upper processing unit 410 can be realized by the processor having a high computing capability, and the variables can be collectively managed, and the processor or sequencer having a high operating frequency can be used. By implementing the flow control unit 426 and the packet communication unit 434 on the lower side, it is possible to construct a system that is efficient overall.

Further, the test unit 400 stores the data value received from the device under test 500 as a variable in the arithmetic processing unit 410 on the upper side. Therefore, according to the test unit 400, the contents of the packet received from one of the devices under test 500 can be reflected on the other tested components 500. In the sent packet.

Fig. 8 shows the configuration of the program supply unit 450 of the present embodiment. The program supply unit 450 includes a communication block extraction unit 442, a package list generation unit 444, a control block extraction unit 446, and a control program generation unit 448.

The test program can be divided into a communication block including a series of packets that should be sequentially communicated, an operation block including an arithmetic expression, and a control block, which includes a conditional branch, an unconditional branch, and a secondary program call, and indicates The communication block that should be executed next. The program supply unit 450 extracts a plurality of communication blocks in the test program including a series of packets to be sequentially communicated. The packet list generating unit 444 generates a plurality of packet lists corresponding to the plurality of communication blocks extracted by the communication block extracting unit 442, and stores the packet lists in the packet list storage unit 432.

The control block extracting unit 446 extracts a plurality of control blocks, and the control blocks execute at least one of the conditional branch, the unconditional branch, and the secondary program call in the test program, and indicate the communication block to be executed next. The control program generation unit 448 generates a control program and supplies it to the flow control unit 426, which executes a plurality of control blocks extracted by the control block extraction unit 446.

The arithmetic block extracting unit 452 extracts a plurality of arithmetic blocks including the arithmetic expressions in the test program. The calculation program generation unit 454 generates a calculation program and supplies it to the calculation unit 414, which executes a plurality of operation blocks extracted by the operation block extraction unit 452.

Such a program supply unit 450 can cause the packet communication unit 434 to execute without Contains a conditional branch, an unconditional branch, or a subroutine call, and contains a list of packets of instructions that are executed sequentially. Further, the program supply unit 450 can cause the arithmetic processing unit 410 to calculate an arithmetic expression. Further, the program supply unit 450 can cause the flow control unit 426 to indicate the packet list to be executed next after the packet communication unit 434 executes the conditional branch, the unconditional branch, or the secondary program call based on the calculation result.

Fig. 9 shows the configuration of the packet communication unit 434 of the present embodiment. The packet communication section 434 includes a transmitting side block 12 and a receiving side block 14. The transmitting side block 12 transmits a packet to the device under test 500 in the order specified by the packet list. The receiving side block 14 receives the packet from the device under test 500, and compares the packet specified by the packet list with the received packet to determine whether the tested component 500 is good or not.

Fig. 10 shows the configuration of the transmission side block 12 of the present embodiment. The transmission side block 12 includes a packet list storage unit 432, a packet list processing unit 22, a packet instruction column storage unit 24, a packet data column storage unit 26, a lower sequencer 28, a material processing unit 32, a data conversion unit 34, and a transmission. Part 36. The packet list storage unit 432 stores a plurality of packet lists supplied from the program supply unit 450.

The packet list processing unit 22 executes the packet list specified by the flow control unit 426 among the plurality of packet lists stored in the packet list storage unit 432, and sequentially specifies the packets to be communicated with the device under test 500. As an example, the packet list processing unit 22 executes the packet list from the address received from the flow control unit 426, and sequentially specifies the packet to be transmitted to the device under test 500.

As an example, the packet list processing unit 22 specifies an address on the packet instruction column storage unit 24 in which the command sequence for generating the specified packet is stored. Further, as an example, the packet list processing unit 22 specifies the address of the data column included in the packet in the packet data column storage unit 26 for the packet to be communicated with the device under test 500 (for example, the data column) Pre-address).

In this manner, the packet list processing unit 22 individually specifies the address of the command line for generating the packet and the address of the data column included in the packet. Furthermore, in this case, when two or more packets in the packet list are assigned a common command column or data column, the packet list processing unit 22 may also specify the two or more packets. The address of the same instruction column or the address of the same data column.

The packet instruction column storage unit 24 stores an instruction sequence for generating each of a plurality of packets for each packet. As an example, the packet instruction column storage unit 24 memorizes an instruction sequence for generating a write packet, an instruction sequence for generating a read packet, and an instruction sequence for generating an idle packet.

The packet data column storage unit 26 stores the data columns included in each of the plurality of packets for each packet. As an example, the packet data column storage unit 26 may include a data column included in the write packet, a data column included in the read packet, and a data column included in the idle packet.

As an example, the packet data column storage unit 26 may include a shared data storage unit 40, a shared material indicator (pointer) 42, a first individual data storage unit 44-1, a second individual data storage unit 44-2, and a first individual. The data indicator 46-1 and the second individual data indicator 46-2. Shared data memory The unit 40 memorizes the shared data shared by each packet among the data columns included in each of the plurality of packets. As an example, the shared material storage unit 40 stores, for each packet, a start code indicating the start of the packet, a termination code indicating the end of the packet, and an instruction code for identifying the type of the packet.

The shared material indicator 42 acquires the preamble address of the block in which the shared material included in the packet specified by the packet list processing unit 22 is stored, from the packet list processing unit 22. In addition, the shared material indicator 42 retrieves an offset position within the block from the lower sequencer 28. Moreover, the shared material indicator 42 provides the shared data storage unit 40 with an address specified according to the preamble address and the offset position (for example, an address obtained by adding an offset position to the preamble address), and the data is obtained. The processing unit 32 provides the shared material stored in the address.

The first and second individual data storage units 44-1 and 44-2 store individual data changed for each packet among the data columns included in each of the plurality of packets. As an example, the first and second individual data storage units 44-1 and 44-2 can memorize the entity data included in each packet and transmitted to the device under test 500 or the entity data received from the device under test 500. .

The first individual data storage unit 44-1 stores individual data that is predetermined in advance regardless of the executed packet list. The second individual data storage unit 44-2 stores the individual data changed in accordance with each of the executed packet lists. As an example, the second individual data storage unit 44-2 receives the transmission of the individual material from the flow control unit 426 in the execution processing unit 420 as appropriate before or during the test.

The first and second individual material indicators 46-1 and 46-2 receive the preamble of the block in which the individual data included in the packet specified by the packet list processing unit 22 is stored, from the packet list processing unit 22. site. Further, the first and second individual data indicators 46-1 and 46-2 acquire the offset position in the block from the lower sequencer 28. Further, the first and second individual data indicators 46-1 and 46-2 provide the first and second individual data storage units 44-1 and 44-2 with addresses determined based on the front address and the offset position. (For example, the address obtained by adding the offset position to the preamble address), and the data processing unit 32 is provided with the individual data stored in the address.

The lower sequencer 28 reads out the command sequence of the packet specified by the packet list processing unit 22, that is, the command line in which the address list processing unit 22 specifies the address, from the packet sequence storage unit 24, and executes the program sequentially. Read each instruction contained in the command line. Further, the lower sequencer 28 causes the data column of the packet specified by the packet list processing unit 22, that is, the data column in which the address list processing unit 22 specifies the address, to sequentially self-package the data column in accordance with the execution of the command line. The portion 26 outputs and generates a test data column for testing with the component under test 500.

As an example, the lower sequencer 28 supplies the shared material indicator 42, the first individual data indicator 46-1, and the second individual data indicator 46-2 in the packet specified by the packet list processing unit 22, The offset position of the data position corresponding to the executed instruction in the block of the included data column. At this time, the lower sequencer 28 may also generate an initial value at the initial instruction and generate an incremented count value as an offset position each time the executed instruction is transferred.

Further, each time the instruction is executed, the lower sequencer 28 supplies the data processing unit 32 and the data conversion unit 34 with control data indicating that the specified processing (operation or data conversion) is performed on the read individual data and the shared data. ). Thereby, the lower sequencer 28 can use the specified data portion of the packet specified by the packet list processing unit 22 as the material that has been subjected to the designation processing on the read data.

Further, each time the command is executed, the lower sequencer 28 specifies the material processing unit 32 to change the shared data and the individual data (the individual data that is predetermined in advance regardless of the executed packet list or the list of each executed packet. The individual data) and the data processed by the data processing unit 32 are output. That is, each time the command is executed, the lower sequencer 28 specifies the data processing unit 32 from the shared data storage unit 40, the first individual data storage unit 44-1, the second individual data storage unit 44-2, or the data processing unit. The one of the registers in the 32 that stores the data on which the specified processing has been executed reads and outputs the data.

Thereby, the lower sequencer 28 can generate, based on the individual data read from the individual data storage unit 44, the data portion to be changed for each packet among the packets specified by the packet list processing unit 22. Further, the lower sequencer 28 can generate a data portion shared by each packet among the packets designated by the packet list processing unit 22 based on the shared data read from the shared data storage unit 40. Further, the lower sequencer 28 can perform a designated process on the designated data portion in the packet specified by the packet list processing unit 22.

Moreover, the lower sequencer 28 can be based on the packet list processing unit 22 The execution of the instruction sequence of the specified packet is completed, and the packet list processing unit 22 is provided with an end notification. Thereby, the packet list processing unit 22 can sequentially specify the packet in accordance with the progress of the execution of the command sequence of the lower sequencer 28.

Further, the lower sequencer 28 specifies the edge timing of the signal transmitted to the device under test 500 to the transmitting portion 36. As an example, the lower sequencer 28 provides timing signals to the transmitting portion 36 and controls the edge timing for each packet.

Further, the lower sequencer 28 communicates with the lower sequencer 28 on the receiving side included in the receiving side block 14 shown in FIG. Thereby, the lower sequencer 28 on the transmitting side included in the transmitting side block 12 can perform handshaking with the lower sequencer 28 on the receiving side included in the receiving side block 14, thereby being compatible with the receiving side. The lower sequencer 28 executes the command columns synchronously.

As an example, the lower sequencer 28 on the transmitting side notifies the lower sequencer 28 on the receiving side that the test data column of the pre-specified packet has been transmitted to the device under test 500. Thereby, the lower sequencer 28 on the transmitting side can prohibit the quality determination of the received data column until the lower sequencer 28 on the receiving side receives the notification from the lower sequencer 28 on the transmitting side.

Further, as an example, the lower sequencer 28 on the transmitting side generates a test of the pre-specified packet after receiving the notification of the data column that has received the test data column from the lower sequencer 28 on the receiving side. Data column. Thereby, the lower sequencer 28 on the transmitting side can transmit the pre-test to the device under test 500 after receiving the specified packet from the device under test 500. The specified packet.

The data processing unit 32 reads out the data sequence of the packet specified by the packet list processing unit 22 from the packet data column storage unit 26, and generates a test data sequence for the test of the device under test 500. As an example, the data processing unit 32 inputs data from the shared material storage unit 40, the first individual data storage unit 44-1, and the second individual data storage unit 44-2, and implements the input sequence by the lower sequencer. After the processing specified by 28, it is output as the data of the test data column.

Furthermore, the data processing unit 32 can also directly output the input data as data of the test data column. An example of the configuration of the material processing unit 32 will be described with reference to Fig. 11 .

The data conversion unit 34 performs data conversion on the test data sequence output from the data processing unit 32 at the timing specified by the lower sequencer 28. As an example, the data conversion unit 34 performs 8b-10b conversion or the like on the test data column based on a table or the like set in advance. Further, as an example, the data conversion unit 34 may perform a scramble processing on the test data column. Further, the data conversion unit 34 outputs the converted data list.

The transmitting unit 36 transmits the test data sequence generated by the data conversion unit 34 to the device under test 500. An example of the configuration of the transmitting unit 36 will be described with reference to Fig. 12 .

FIG. 11 shows an example of the configuration of the material processing unit 32 in the transmission side block 12 of the present embodiment. As an example, the data processing unit 32 in the transmission side block 12 includes at least one temporary storage unit 52, a front stage selection unit 54, at least one arithmetic unit 56, and a rear stage selection unit 60.

Operation processing of at least one temporary memory 52 for each previous cycle of memory result. In this example, the data processing unit 32 includes a first register 52-1 and a second register 52-2.

In each cycle, the preceding stage selection unit 54 selects the shared material from the shared data storage unit 40 and the respective data storage unit 44 (in this example, the first individual data storage unit 44-1 and the second individual data storage unit 44- 2) The individual data and the data specified by the lower sequencer 28 among the data of each of the registers 52 (in this example, the first register 52-1 and the second register 52-2) . Further, in each cycle, the preceding stage selecting unit 54 supplies each of the selected materials to the arithmetic unit 56 or the rear stage selecting unit 60 designated by the lower sequencer 28.

Each of the at least one arithmetic unit 56 is provided corresponding to each of at least one of the temporary registers 52. In the present example, the data processing unit 32 includes a first arithmetic unit 56-1 corresponding to the first temporary storage unit 52-1 and a second arithmetic unit 56-2 corresponding to the second temporary storage unit 52-2. . As an example, each of the arithmetic units 56 performs arithmetic operations such as logical operations, four arithmetic operations, generation of pseudo-random numbers, and generation of error-correcting codes. In each cycle, each of the arithmetic units 56 performs an operation designated by the lower sequencer 28 on the data selected by the previous stage selecting unit 54 and stores it in the corresponding register 52.

In each cycle, the subsequent stage selection unit 60 selects the material selected by the previous stage selection unit 54 (in this example, the shared data storage unit 40, the first individual data storage unit 44-1, or the second individual data storage unit 44-2). The data and the data specified by the lower sequencer 28 in the data in at least one of the registers 52. Moreover, the later stage selection unit 60 uses the selected material as a test capital. The data of the stock list is output.

FIG. 12 shows an example of the configuration of the transmitting unit 36 in the transmitting side block 12 of the present embodiment. As an example, the transmitting portion 36 includes a serializer 72, a format controller 74, and a driver 76.

The serializer 72 converts the test data column received from the data processing unit 32 into a serial waveform pattern. The format controller 74 generates a signal having a waveform corresponding to the waveform pattern received from the serializer 72. Additionally, format controller 74 outputs a signal that produces a varying waveform at the edge timing specified by lower sequencer 28. The driver 76 supplies a signal output from the format controller 74 to the device under test 500.

Fig. 13 shows the configuration of the receiving side block 14 of the present embodiment. The receiving side block 14 has substantially the same configuration and function as the transmitting side block 12 shown in FIG. Among the members included in the receiving side block 14, members having substantially the same configuration and function as those of the members included in the transmitting side block 12 are denoted by the same reference numerals, and descriptions other than the differences will be omitted.

The receiving side block 14 includes a packet list storage unit 432, a packet list processing unit 22, a packet instruction column storage unit 24, a packet data column storage unit 26, a lower sequencer 28, a material processing unit 32, a data conversion unit 34, and a receiving unit. 82. The determination unit 84. The receiving unit 82 receives the data column of the packet from the device under test 500. An example of the configuration of the receiving unit 82 will be described with reference to Fig. 14 .

The data conversion unit 34 in the receiving side block 14 performs data conversion on the data column received by the receiving unit 82 at the timing designated by the lower sequencer 28. As an example, the data conversion unit 34 in the receiving side block 14 The received data column is subjected to 8b-10b conversion or the like according to a preset table or the like. Further, as an example, the data conversion unit 34 in the receiving side block 14 may perform descrambling processing on the received data column. Further, the data conversion unit 34 in the receiving side block 14 outputs the converted data column.

Then, the data conversion unit 34 in the reception side block 14 supplies the converted data sequence to the determination unit 84. Further, the data conversion unit 34 in the receiving side block 14 may store the converted data column in the designated address of the second individual data storage unit 44-2 in the packet data column storage unit 26. Thereby, the flow control unit 426 can read out the data received from the device under test 500 as a variable value, and read it from the packet data column storage unit 26 and transfer it to the arithmetic processing unit 410.

As an example, the packet list processing unit 22 in the receiving side block 14 executes the packet list from the address received from the flow control unit 426. Moreover, the packet list processing unit 22 in the receiving side block 14 sequentially specifies the desired and received packets from the device under test 500.

The lower sequencer 28 in the receiving side block 14 causes the data sequence of the packet desired to be output from the device under test 500 to be output from the packet data column storage unit 26 as a test data column. Further, the lower sequencer 28 in the receiving side block 14 specifies the strobe timing of the data value of the signal output from the device under test 500 to the receiving unit 82. The data processing unit 32 in the receiving side block 14 supplies the generated test data sequence to the determining unit 84.

The determination unit 84 receives the test data column from the data processing unit 32, and receives The data column received by the data conversion unit 34 is received. The determination unit 84 determines whether or not the communication with the device under test 500 is good or bad based on the result of comparing the received data column with the test data column. As an example, the determination unit 84 includes a logic comparison unit that compares whether the data column received by the receiving unit 82 matches the test data column, and a fail memory that memorizes the comparison result. Further, as an example, the determination unit 84 may notify the lower sequencer 28 that the data column received by the receiving unit 82 and the designated data column coincide with each other.

Further, the lower sequencer 28 in the receiving side block 14 communicates with the lower order sequencer 28 on the transmitting side included in the transmitting side block 12 shown in FIG. Thereby, the lower sequencer 28 on the receiving side included in the receiving side block 14 can perform signal exchange with the lower sequencer 28 on the transmitting side included in the transmitting side block 12, so that it can be compared with the lower side of the transmitting side. The sequencer 28 executes the instruction columns synchronously.

As an example, the lower sequencer 28 on the receiving side notifies the lower sequencer 28 on the transmitting side that the data column that has been matched with the test data column generated by the lower sequencer 28 on the receiving side has been received. Thereby, the lower sequencer 28 on the transmitting side receives the notification of the data column that has received the test data column after receiving the notification from the lower sequencer 28 on the receiving side, and can generate a test data column of the packet specified in advance.

As an example, the lower sequencer 28 on the receiving side does not allow the determination until the lower sequence sequencer 28 from the transmitting side receives the test data sequence of the packet specified in advance to the notification of the device under test 500. The unit 84 determines whether or not the data sequence received by the receiving unit 82 is good or bad. With this, The lower sequencer 28 on the receiving side can determine whether or not the response corresponding to the specified packet is output from the device under test 500 after transmitting the predetermined packet to the device under test 500.

FIG. 14 shows an example of the configuration of the receiving unit 82 in the receiving side block 14 of the present embodiment. As an example, the receiving unit 82 includes a level comparator 86, a timing comparator 88, a deserializer 90, a phase adjustment unit 92, and a hunting unit 94.

The level comparator 86 compares the signal output from the device under test 500 with a threshold value and outputs a logic signal. The timing comparator 88 sequentially acquires the data of the logic signal output by the level comparator 86 at the gate timing designated by the lower sequencer 28.

The deserializer 90 converts the data column obtained by the timing comparator 88 into a parallel data column. The phase adjustment unit 92 detects the pre-designated code of the packet and adjusts the off-phase of the parallel data column converted by the deserializer 90. The search unit 94 compares the data sequence acquired by the timing comparator 88 with the pre-designated code of the packet, and adjusts the pre-position of the packet in units of pits.

Such a receiving portion 82 can receive a packet output from the device under test 500 at an indeterminate timing. Thereby, according to the receiving side block 14, the data column included in the packet output from the device under test 500 at an indeterminate timing can be compared with the test data column expected to be output from the device under test 500.

Fig. 15 shows an example of a packet list in the present embodiment. Packet column The table describes a number of instructions that are executed sequentially. As an example, the NOP instruction, the IDXI instruction, and the EXIT instruction are described in the packet list. The NOP instruction causes execution to be transferred to the next instruction. The IDXI instruction transfers execution to the next instruction after repeating the specified number of executions. The EXIT instruction ends the execution of the packet sequence.

In addition, the packet function is described in correspondence with each instruction in the packet list. As an example, the packet list describes a packet function that generates a write packet, a read packet, and an idle packet that generates a prescribed code.

In addition, in the packet list, the preamble address of the instruction sequence for generating the packet indicated by the packet function, the shared data contained in the packet indicated by the packet function, and the individual are respectively associated with each packet function. The preamble address of the data. By executing such a packet list, the packet list processing unit 22 can call a packet function corresponding to the executed command each time each instruction is sequentially executed.

Fig. 16 shows an example of a packet function loaded into the packet communication unit 434 of this embodiment after compilation. A plurality of instructions sequentially executed are described in the packet function of the load packet communication unit 434.

As an example, a NOP instruction, an IDXI instruction, an RTN instruction, and the like are described in the packet function. After the NOP instruction outputs the data stored in the address specified by the indicator once, the execution is transferred to the next instruction. The IDXI instruction transfers the data stored in the address specified by the indicator repeatedly for a specified number of times, and then transfers the execution to the next instruction. After the RTN instruction outputs the data stored in the address specified by the indicator once, it returns the execution to the packet list.

Further, the control function is described in the packet function corresponding to each instruction. As an example, the control data includes an arithmetic expression supplied to the arithmetic unit 56. In the example of FIG. 16, the control data includes a logical OR of the exclusive or logical AND of the data of the first register 52-1 and the outputted data to the first temporary register 52-1. The expression (REG1=REG1ˆDB1 or REG1=REG1ˆDB2). Instead of this, the control data may also specify the conversion processing of the data conversion unit 34.

Further, in the packet function, information corresponding to the storage location of the data to be output corresponding to the instruction is described corresponding to each instruction. As an example, the packet function designates any of the shared material storage unit 40, the individual data storage unit 44, and the temporary storage unit 52 as a storage location.

In the example of Fig. 16, a hexadecimal value such as 0x0F or 0x01 indicates the address of the shared data storage unit 40 as a storage place for the material. Further, DB1 indicates that the first individual data storage unit 44-1 is a storage location of the material. DB2 indicates that the second individual data storage unit 44-2 is a storage place for the material. REG1 indicates that the first register 52-1 is used as a storage place for data. The lower sequencer 28 can output the data column specified by each packet function by executing the instruction sequence represented by such a packet function.

Fig. 17 shows the processing flow of the test unit 400 of the present embodiment. First, the packet list processing unit 22 executes the packet list, and sequentially specifies the packets to be communicated with the device under test 500 (S11, S16). Next, when the lower sequencer 28 receives the designation of the packet of the packet list processing unit 22, the processing of steps S12 to S15 is repeatedly executed.

If the lower sequencer 28 receives the designation of the packet, the self-packing instruction The column memory unit 24 calls the instruction sequence for generating the packet and executes it sequentially from the pre-set instruction. Each time the respective commands are executed, the lower sequencer 28 performs the processing of steps S13 and S14 (S12, S15).

In step S13, the lower sequencer 28 outputs the material corresponding to the instruction. Moreover, in step S14, the lower sequencer 28 performs an operation or data conversion corresponding to the instruction. The lower sequencer 28 performs step S13 and step S14 in parallel.

When the lower sequencer 28 executes the last command, the process returns to the packet list processing unit 22, and the packet list processing unit 22 receives the designation of the next packet (S15). Then, when the packet list processing unit 22 ends the processing up to the last packet in the packet sequence, the flow is ended (S16).

According to the test unit 400 of the present embodiment as described above, the packet list indicating the packet sequence and the command sequence in the packet can be executed by an individual sequencer. Thereby, according to the test section 400, the description of the program can be simplified. Further, according to the test unit 400, the command line for generating the packet of the common type and the data can be shared, so that the amount of stored information can be reduced.

Further, in the test unit 400 of the present embodiment, the packet list processing unit 22 individually specifies the address of the command line executed by the lower sequencer 28 and the address of the data sequence read by the lower sequencer 28. Thereby, according to the test unit 400, different data columns can be generated by the same command sequence. Therefore, according to the test unit 400, the same command line is not stored a plurality of times, so that the amount of stored information can be reduced.

Further, the test unit 400 of the present embodiment is composed of the data processing unit 32. The specified processing (i.e., calculation or conversion) is performed on the data read from the shared data storage unit 40 and the individual data storage unit 44. That is, the data processing unit 32 can generate a data conversion and an error detection code to be processed based on the specification of the lower layer (layer close to the physical layer) of the packet communication.

Thereby, the test unit 400 only needs to generate a command line and a data column for outputting the data of the upper layer of the packet communication, and individually specify the processing of the lower layer of the packet communication. Therefore, according to the test section 400, the description of the program can be simplified, and the amount of stored information can be reduced.

Further, the test unit 400 of the present embodiment separates the transmission side block 12 and the reception side block 14, and each of the transmission side block 12 and the reception side block 14 includes a packet list processing unit 22 and a lower sequencer. 28. The transmitting side block 12 generates a test data column for transmitting a signal to the device under test 500, and the receiving side block 14 generates a test data column for comparison with a signal received from the device under test 500. According to the test section 400, the programs on the transmitting side and the receiving side can be independently described, and thus the program can be simplified.

Moreover, the test unit 400 can communicate between the lower sequencer 28 on the transmitting side and the lower sequencer 28 on the receiving side. Thereby, the test unit 400 starts the operation on the receiving side by, for example, an event trigger generated by the transmitting side, or starts the operation on the transmitting side by the event trigger generated by the receiving side.

Further, the test unit 400 may be configured as a group including a plurality of transmission side blocks 12 and reception side blocks 14. At this time, the execution processing unit 420 provides an individual sequence for each of the groups of the transmission side block 12 and the reception side block 14. Columns (individual packet lists), and the blocks are executed independently of each other. Thereby, the test unit 400 can operate each of the groups of the transmitting side block 12 and the receiving side block 14 asynchronously with each other.

Further, the execution processing unit 420 can also operate each of the groups of the transmission side block 12 and the reception side block 14 in synchronization with each other. At this time, the execution processing unit 420 supplies the same sequence (the same packet list) to each of the groups of the transmission side block 12 and the reception side block 14, and causes the blocks to start execution in synchronization with each other. Thereby, the test section 400 can test a plurality of tested components 500 including the same type or different kinds of packet communication type interfaces in parallel.

The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope disclosed in the above embodiments. It will be appreciated by those skilled in the art that various modifications or improvements can be made in the above-described embodiments. It is to be understood from the description of the scope of the patent application that such modifications or improvements are also within the technical scope of the invention.

It should be noted that the order of execution of the processes, the procedures, the steps, the stages, and the like in the devices, systems, programs, and methods shown in the claims, the description, and the drawings is not particularly It is indicated that "before", "before", etc., and can be implemented in any order as long as the output of the previous process is not used for the latter process. The use of "first," "second," and the like in the scope of application for patent application, the specification, and the drawings does not necessarily mean that it must be implemented in this order.

Although the invention has been disclosed above by way of example, it is not intended to be limiting The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. Prevail.

100‧‧‧Testing device

200‧‧‧ Simulator

300‧‧‧Transition Department

400‧‧‧Test Department

500‧‧‧Tested components

600‧‧‧simulated environment

610‧‧‧Component simulation model

620‧‧‧ Trading source

630‧‧‧ Adapter

310‧‧‧Package Definition Data Memory Department

320‧‧‧Acquisition Department

330‧‧‧Package Communication Program Generation Department

340‧‧‧ Wave Dump Memory

410‧‧‧Operation Processing Department

420‧‧‧Execution Processing Department

430‧‧‧Communication Processing Department

440‧‧‧Test program memory

450‧‧‧Program Supply Department

412‧‧‧Variable Memory

414‧‧‧ Computing Department

426‧‧‧Process Control Department

432‧‧‧Package List Memory

434‧‧‧Package Communications Department

442‧‧‧Communication Block Extraction Department

444‧‧‧Packing List Generation Department

446‧‧‧Control block extraction department

448‧‧‧Control Program Generation Department

452‧‧‧Operation block extraction department

454‧‧‧Computation Program Generation Department

12‧‧‧Send side block

14‧‧‧ Receiving side block

22‧‧‧Packet List Processing Department

24‧‧‧Packing Instruction List Memory

26‧‧‧Package data in the memory department

28‧‧‧Lower sequencer

32‧‧‧Data Processing Department

34‧‧‧Data Conversion Department

36‧‧‧Send Department

40‧‧‧Shared Data Memory Department

42‧‧‧Shared information indicator

44‧‧‧Individual Data Memory Department

44-1‧‧‧The first individual data memory department

44-2‧‧‧2nd Partial Data Memory Department

46‧‧‧Individual data indicator

46-1‧‧‧1st individual indicator

46-2‧‧‧2nd individual indicator

52‧‧‧Scratch

52-1‧‧‧1st register

52-2‧‧‧2nd register

54‧‧‧Previous selection department

56‧‧‧Operator

56-1‧‧‧1st operator

56-2‧‧‧2nd operator

60‧‧‧Department Selection Department

72‧‧‧Series

74‧‧‧ format controller

76‧‧‧ drive

82‧‧‧ Receiving Department

84‧‧‧Decision Department

86‧‧‧ level comparator

88‧‧‧Timer Comparator

90‧‧‧Deserturizer

92‧‧‧ Phase Adjustment Department

94‧‧ Search Department

S11~S16‧‧‧Steps

FIG. 1 is a view showing the configuration of the test apparatus 100 of the present embodiment and the device under test 500.

Fig. 2 shows the hierarchical structure of the packet communication program for testing according to the present embodiment.

FIG. 3 shows a first example of the configuration of the simulator 200 and the conversion unit 300 of the present embodiment.

FIG. 4 shows a second example of the configuration of the simulator 200 and the conversion unit 300 of the present embodiment.

Fig. 5 shows a third example of the configuration of the simulator 200 and the conversion unit 300 of the present embodiment.

FIG. 6 shows an example of the configuration of the test unit 400 of the present embodiment.

FIG. 7 shows an example of the configuration of the arithmetic processing unit 410 of the present embodiment, and a configuration of a plurality of execution processing units 420 and a representative one of the plurality of communication processing units 430 and the communication processing unit 430.

Fig. 8 shows the configuration of the program supply unit 450 of the present embodiment.

Fig. 9 shows the configuration of the packet communication unit 434 of the present embodiment.

Fig. 10 shows the configuration of the transmission side block 12 of the present embodiment.

FIG. 11 shows an example of the configuration of the material processing unit 32 in the transmission side block 12 of the present embodiment.

FIG. 12 shows an example of the configuration of the transmitting unit 36 in the transmitting side block 12 of the present embodiment.

Fig. 13 shows the configuration of the receiving side block 14 of the present embodiment.

FIG. 14 shows an example of the configuration of the receiving unit 82 in the receiving side block 14 of the present embodiment.

Fig. 15 shows an example of a packet list in the present embodiment.

Fig. 16 shows an example of a packet function of this embodiment.

Fig. 17 shows the processing flow of the test unit 400 of the present embodiment.

100‧‧‧Testing device

200‧‧‧ Simulator

300‧‧‧Transition Department

400‧‧‧Test Department

500‧‧‧Tested components

600‧‧‧simulated environment

610‧‧‧Component simulation model

Claims (10)

A test device for testing a device under test, and comprising: an acquisition unit that obtains a packet sequence for communication with the device under test according to a simulation environment simulating an action of the device under test; and a packet communication program generation a packet communication program executed by the test device according to the packet sequence, and a packet communication program generated by the packet sequence between the packet communication program generation unit and the device under test, and a test unit, Executing the packet communication program, and performing packet communication with the tested component to perform testing; wherein the testing unit includes: a packet list processing unit, executing the packet communication program, and sequentially designating the component to be tested Each packet for communication; the sequencer sequentially executes each command included in the command line of the packet specified by the packet list processing unit, and sequentially outputs the command specified by the packet list processing unit in accordance with the execution of the command line. The data column of the packet is generated and used for testing between the above tested components a test data column; a receiving unit, and a test data column of the packet generated by the sequencer, and a transmitting unit, and the device to be tested are sent by the sequencer a test data column of the generated packet; wherein the obtaining unit monitors a packet communicated by the tested component in the execution of the simulation of the simulated environment, and obtains a packet sequence of communication between the test device and the tested component . A test device for testing a device under test, and comprising: an acquisition unit that obtains a packet sequence for communication with the device under test according to a simulation environment simulating an action of the device under test; and a packet communication program generation a packet communication program executed by the test device according to the packet sequence, and a packet communication program generated by the packet sequence between the packet communication program generation unit and the device under test, and a test unit, Executing the packet communication program, and performing packet communication with the tested component to perform testing; wherein the testing unit includes: a packet list processing unit, executing the packet communication program, and sequentially designating the component to be tested Each packet for communication; the sequencer sequentially executes each command included in the command line of the packet specified by the packet list processing unit, and sequentially outputs the command specified by the packet list processing unit in accordance with the execution of the command line. The data column of the packet is generated and used for testing between the above tested components a test data column; a receiving unit, and a test data column of the packet generated by the sequencer, and a transmitting unit, and the device to be tested are sent by the sequencer a test data column of the generated packet; wherein the obtaining unit scans a waveform of an input/output signal of the device under test obtained by performing a simulation of the simulation environment, and extracts between the test device and the device under test The packet column of the communication. A test device that tests a component under test and includes: The acquisition unit acquires a packet sequence that communicates with the device under test based on a simulation environment in which the operation of the device under test is simulated, and the packet communication program generation unit generates and executes the test device based on the packet sequence. a packet communication program, wherein a packet communication program generated based on the packet sequence is executed between the packet communication program generation unit and the device under test; and a test unit that executes the packet communication program to perform the operation with the device under test The packet communication is performed for testing; wherein the testing unit includes: a packet list processing unit that executes the packet communication program, and sequentially specifies each packet that communicates with the tested component; the sequencer sequentially executes the inclusion Each instruction of the instruction sequence of the packet specified by the packet list processing unit sequentially outputs the data sequence of the packet specified by the packet list processing unit in accordance with the execution of the command line, and generates a data sequence for the device to be tested. Test data column for inter-test; between the receiving unit and the above-mentioned tested component, Receiving a test data column of the packet generated by the sequencer; and transmitting, by the transmitting unit, the test data column of the packet generated by the sequencer between the device under test; wherein the obtaining unit is configured according to A packet definition data defining a data column included in each of the plurality of packets to indicate the type of the packet communicated between the test device and the device under test. The test device according to claim 3, wherein the test unit further includes a packet data column storage unit corresponding to each of the plurality of packets And storing the data column specified by the packet definition data, and the sequencer reads the data column of the packet specified by the packet list processing unit from the packet data column storage unit, and generates a test for the test Test data column for test components. The testing device of claim 4, wherein the testing unit further comprises: a packet list storage unit, which memorizes a series of communications from the packet communication program and includes communication with the device under test. And a plurality of packet lists of each of the packets; and the flow control unit specifies an order in which the plurality of packet lists are executed according to an execution flow of the packet communication program; and the packet list processing unit executes the flow control unit The packet list is sequentially designated, and each packet that communicates with the tested component is sequentially designated to the sequencer. A test method is a method for testing a device under test in a test device, and comprising: obtaining a packet sequence for communication with the device under test according to a simulation environment simulating an action of the device under test; The packet sequence generates a packet communication program executed by the test device, and executes a packet communication program generated according to the packet sequence between the device under test; and the test device includes a test portion, and the test portion executes The above packet communication program performs packet communication with the tested component to perform testing; The test unit includes: a packet list processing unit that executes the packet communication program, and sequentially specifies each packet that communicates with the tested component; and the sequencer sequentially executes the packet specified by the packet list processing unit Each instruction of the instruction sequence of the packet outputs the data column of the packet specified by the packet list processing unit in sequence according to the execution of the command line, and generates a test data column for testing with the device under test; a receiving unit that receives a test data sequence of the packet generated by the sequencer between the device under test, and a transmitting unit that transmits the packet generated by the sequencer to the device under test The test data column, wherein the acquisition unit monitors a packet communicated by the device under test in the execution of the simulation of the simulation environment, and obtains a packet sequence for communication between the test device and the device under test. A test method is a method for testing a device under test in a test device, and comprising: obtaining a packet sequence for communication with the device under test according to a simulation environment simulating an action of the device under test; The packet sequence generates a packet communication program executed by the test device, and executes a packet communication program generated according to the packet sequence between the device under test; and the test device includes a test portion, and the test portion executes The above packet communication program performs packet communication with the tested component to perform testing; The test unit includes: a packet list processing unit that executes the packet communication program, and sequentially specifies each packet that communicates with the tested component; and the sequencer sequentially executes the packet specified by the packet list processing unit Each instruction of the instruction sequence of the packet outputs the data column of the packet specified by the packet list processing unit in sequence according to the execution of the command line, and generates a test data column for testing with the device under test; a receiving unit that receives a test data sequence of the packet generated by the sequencer between the device under test, and a transmitting unit that transmits the packet generated by the sequencer to the device under test a test data column; wherein the acquisition unit extracts a waveform of the input/output signal of the device under test obtained by performing the simulation of the simulation environment, and extracts a packet sequence between the test device and the device under test . A test method is a method for testing a device under test in a test device, and comprising: obtaining a packet sequence for communication with the device under test according to a simulation environment simulating an action of the device under test; The packet sequence generates a packet communication program executed by the test device, and executes a packet communication program generated according to the packet sequence between the device under test; and the test device includes a test portion, and the test portion executes The above packet communication program performs packet communication with the tested component to perform testing; The test unit includes: a packet list processing unit that executes the packet communication program, and sequentially specifies each packet that communicates with the tested component; and the sequencer sequentially executes the packet specified by the packet list processing unit Each instruction of the instruction sequence of the packet outputs the data column of the packet specified by the packet list processing unit in sequence according to the execution of the command line, and generates a test data column for testing with the device under test; a receiving unit that receives a test data sequence of the packet generated by the sequencer between the device under test, and a transmitting unit that transmits the packet generated by the sequencer to the device under test The test data column; wherein the obtaining unit indicates the type of the packet communicated between the test device and the tested component based on the packet definition data defining the data column included in each of the plurality of packets. The test method according to claim 8, wherein the test unit further includes a packet data column storage unit, and stores a data column specified by the packet definition data corresponding to each of the plurality of packets, and the sequencer, A data sequence of the packet specified by the packet list processing unit is read from the packet data column storage unit, and a test data sequence for testing the device under test is generated. The test method of claim 9, wherein the testing unit further comprises: a packet list storage unit, which memorizes a series of communications extracted from the packet communication program and includes communication with the tested component Seal a plurality of packet lists of the packets; and a flow control unit that specifies an order in which the plurality of packet lists are executed according to an execution flow of the packet communication program; and the packet list processing unit executes the flow control unit The packet list is sequentially designated, and each packet that communicates with the tested component is sequentially designated to the sequencer.