TWI407544B - 輸入／輸出靜電放電元件與級聯輸入／輸出靜電放電元件 - Google Patents

輸入／輸出靜電放電元件與級聯輸入／輸出靜電放電元件 Download PDF

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TWI407544B
TWI407544B TW098135394A TW98135394A TWI407544B TW I407544 B TWI407544 B TW I407544B TW 098135394 A TW098135394 A TW 098135394A TW 98135394 A TW98135394 A TW 98135394A TW I407544 B TWI407544 B TW I407544B
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lightly doped
input
drain region
output
region
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TW201108384A (en
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Tung Hsing Lee
I Cheng Lin
Wei Li Tsao
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Mediatek Inc
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    • H01L29/66409—Unipolar field-effect transistors
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Description

輸入/輸出靜電放電元件與級聯輸入/輸出靜電放電元件
本發明有關於積體電路(integrated circuits,以下簡稱為IC)，尤其有關於具有較低的接面崩潰電壓(junction breakdown voltage)和較好的靜電放電(electrostatic discharge,以下簡稱為ESD)防護性能的輸入/輸出(input/output,以下簡稱為I/O)ESD元件。
IC晶片與晶片外(off-chip)的電子元件進行電通信以交換資訊。IC晶片可利用與晶片外電子元件所用電壓不同的電壓。於是，IC晶片和晶片外電子元件之間的介面必須能夠容納電壓差。一個此種介面包含一混合電壓I/O驅動器。
傳統的ESD防護架構包括兩個級聯(casade)結構的N型金屬氧化物半導體(Negative Metal Oxide Semiconductor,NMOS)電晶體，這兩個NMOS電晶體合併為一基底(substrate)的相同有效區(active area)。例如，當在靜電放電期間提供一寄生橫向NPN雙極型電晶體(parasitic lateral NPN bipolar transistor)時，兩個NMOS電晶體允許5V信號在正常運作期間降至3.3V。在ESD條件下，當底端NMOS電晶體的源極和頂端NMOS電晶體的汲極之間產生雙極效應時，堆疊式(stacked)電晶體運作於驟回(snapback)。
當此I/O驅動器已用於一些通用設計，如何平衡ESD防護性能和I/O性能則繼續成為一種挑戰。於是，期望提升級聯MOS驅動器的性能和ESD元件的ESD防護性能。更具體地講，需要從驅動器消除ESD的設計約束以達到最大的I/O性能。
有鑒於此，本發明提供輸入/輸出靜電放電元件與級聯輸入/輸出靜電放電元件。
依據本發明一實施例提供一種輸入/輸出靜電放電元件，包括：閘極電極，位於基底之上；閘極介電層，位於所述閘極電極和所述基底之間；對側壁間隔單元，分別位於所述閘極電極的兩個相對的側壁；第一LDD區域，位於一個所述側壁間隔單元之下；源極區域，與所述第一LDD區域相鄰；第二LDD區域，位於另一個所述側壁間隔單元之下；以及汲極區域，與所述第二LDD區域相鄰；其中所述第二LDD區域的摻雜濃度大於所述第一LDD區域的摻雜濃度。
依據本發明另一實施例提供一種級聯輸入/輸出靜電放電元件，包括：第一MOS電晶體，具有閘極電極、源極架構和汲極架構；以及第二MOS電晶體，通過共用所述第一MOS電晶體的所述源極架構與所述第一MOS電晶體串聯；其中所述第一MOS電晶體的所述源極架構包括第一LDD區域，所述第一MOS電晶體的所述汲極架構包括第二LDD區域，且所述第二LDD區域的摻雜濃度大於所述第一LDD區域的摻雜濃度。
利用本發明能夠減少ESD元件的接面崩潰電壓並獲得更好的ESD性能。
以下係根據多個圖式對本發明之較佳實施例進行詳細描述，本領域習知技藝者閱讀後應可明確了解本發明之目的。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
第1圖是根據本發明一個實施例的ESD元件1的橫斷面示意圖。如第1圖所示，於一I/O P阱(well)12形成ESD元件1，且I/O P阱12設置於半導體基底10(如P型矽基底)上。根據本實施例，ESD元件1是一NMOS電晶體且於I/O元件區域中製造。當然，本發明也適用於P型金屬氧化物半導體(Positive Metal Oxide Semiconductor,PMOS)電晶體。ESD元件1包括I/O P阱12區域上設置的閘極電極20。閘極電極20可為堆疊架構，包括導體和絕緣體，導體例如多晶矽層(polysilicon layer)、金屬或金屬矽化物(metal silicide)；絕緣體例如用於封裝導體的氮化矽(silicon nitride)。當然，閘極電極20可為通常用於I/O元件的任一適合的閘極架構。
可在閘極電極20和I/O P阱12之間設置一閘極介電層22。閘極介電層22可由I/O元件的閘極介電層形成。閘極介電層22可與I/O元件同時形成且因此相較於核心(core)元件的厚度，閘極介電層22具有更厚的厚度。舉例來說，基於65奈米(nm)技藝節點，閘極介電層22有大約35~70埃(angstrom)的厚度，而核心元件(圖中未示)具有10~25埃的厚度。側壁間隔單元(sidewall spacer)24a和側壁間隔單元24b可在閘極電極20的兩個相對的側壁上形成。側壁間隔單元24a和24b可包括介電材料，例如氧化矽(silicon oxide)、氮化矽、氮氧化矽(silicon oxynitride)或其組合。在一個實施例中側壁間隔單元24a和24b進一步包括一襯墊(liner)，比如氧化襯墊。
在閘極電極20的左側，於I/O P阱12中設置源極架構30。源極架構30可包括第一N型輕摻雜汲極(N-type lightly doped drain,NLDD)區域14、N+源極區域15以及自動對準金屬矽化物層(salicide layer)15a。其中，第一NLDD區域14位於側壁間隔單元24a下方，N+源極區域15與第一NLDD區域14相鄰，自動對準金屬矽化物層15a位於N+源極區域15之上。第一NLDD區域14可以是I/O元件的輕摻雜汲極(Lightly Doped Drain,LDD)植入製程所形成的一I/O NLDD區域。
舉例來說，根據一個實施例，第一NLDD區域14可通過植入N型摻雜物(dopant)形成，其中N型摻雜物例如一定量的磷(phosphorus)和砷(arsenic)，比如2×1013 ~8×1013 atoms/cm2 ，且第一NLDD區域14可有大約300~1,000埃的接面深度。在一個實施例中，N+源極區域15可在側壁間隔單元24a和24b形成之後形成。N+源極區域15可通過在I/O P阱12中植入N型摻雜物形成，N型摻雜物例如一定量(如1×1015 ~5×1015 atoms/cm2 )的砷。舉例來說，根據本發明，N+源極區域15可有大約800~1,500埃的接面深度。自動對準金屬矽化物層15a可在與側壁間隔單元24a的邊緣相鄰處形成且不超出第一NLDD區域14，其中自動對準金屬矽化物層15a可以是鈷(cobalt)自動對準金屬矽化物或鎳(nickel)自動對準金屬矽化物。
在閘極電極20的右側，於I/O P阱12設置一汲極架構40，且汲極架構40與源極架構30相對。汲極架構40可包括第二NLDD區域16、P型袋狀(pocket)區域17、N+汲極區域18和自動對準金屬矽化物層18a。其中，第二NLDD區域16位於側壁間隔單元24b下方，P型袋狀區域17在第二NLDD區域16周圍，N+汲極區域18與第二NLDD區域16相鄰，自動對準金屬矽化物層18a在N+汲極區域18之上。N+汲極區域18耦接一I/O焊墊。第二NLDD區域16可以是核心元件的LDD植入製程所形成的一核心LDD區域。本實施例的一個特點就是ESD元件1具有一非對稱的LDD結構。第二NLDD區域16的摻雜濃度(doping concentration)大於第一NLDD區域14的摻雜濃度。為了具有非對稱的LDD結構，本實施例中的ESD元件1在其汲極架構40不包括I/O NLDD或任何額外的ESD植入，而是將第二NLDD區域16與環型佈植(halo implantation)合併，此處的環型佈植例如P型袋狀區域17。通過合併第二NLDD區域16和P型袋狀區域17以及從汲極架構40中消除I/O NLDD，能夠減少ESD元件1的接面崩潰電壓並獲得更好的ESD性能。
第二NLDD區域16可與核心元件的核心NLDD植入同時形成。根據一個實施例，第二NLDD區域16可通過植入N型摻雜物形成，其中N型摻雜物例如一定量(比如5×1014 ~3×1015 atoms/cm2 )的砷，且第二NLDD區域16可有大約200~900埃的接面深度。P型袋狀區域17可由核心元件製程中執行的環型佈植所形成。根據一個實施例，P型袋狀區域17可通過植入P型摻雜物形成，其中P型摻雜物例如一定量(比如1×1013 ~9×1013 atoms/cm2 )的銦(In)、硼(B)或二氟化硼(BF2 )，且P型袋狀區域17可有大約200~900埃的接面深度。例如，自動對準金屬矽化物層18a可以是鈷自動對準金屬矽化物或鎳自動對準金屬矽化物，自動對準金屬矽化物層18a和側壁間隔單元24b的邊緣偏移d以防止洩漏(leakage)。然而，在另一個實施例中，自動對準金屬矽化物層18a和側壁間隔單元24b之間沒有偏移。當然，本發明也可適用於PMOS電晶體，比如將NLDD區域14和N+源極區域15等分別替換為PLDD區域和P+源極區域等。
第2圖是根據本發明另一個實施例的級聯I/O ESD元件2的橫斷面示意圖。如第2圖所示，級聯I/O ESD元件2包括級聯結構的兩個NMOS電晶體100和200，其中NMOS電晶體100具有與第1圖所描述的ESD元件1相似的架構。NMOS電晶體100可包括於I/O P阱12之上設置的閘極電極20。在閘極電極20和I/O P阱12之間設置閘極介電層22。閘極介電層22可由I/O元件的閘極介電層形成。側壁間隔單元24a和側壁間隔單元24b在閘極電極20的兩個相對的側壁形成。側壁間隔單元24a和側壁間隔單元24b可包括介電材料，例如氧化矽、氮化矽、氮氧化矽或其組合。在閘極電極20的左側，在I/O P阱12中設置一源極架構。源極架構可包括第一NLDD區域14、N+源極區域15和自動對準金屬矽化物層15a。其中，第一NLDD區域14位於側壁間隔單元24a下方，N+源極區域15與第一NLDD區域14相鄰。第一NLDD區域14是由I/O元件的LDD植入製程所形成的一I/O NLDD區域。例如，根據一個實施例，第一NLDD區域14可通過植入N型摻雜物形成，其中N型摻雜物例如一定量(比如2×1013 ~8×1013 atoms/cm2 )的磷和砷，且第一NLDD區域14可有大約300~1,000埃的接面深度。在一個實施例中，N+源極區域15可在側壁間隔單元24a和24b形成之後形成。N+源極區域15可通過在I/O P阱12中植入N型摻雜物形成，N型摻雜物例如一定量(如1×1015 ~5×1015 atoms/cm2 )的砷。舉例來說，根據本發明，N+源極區域15可有大約800~1,500埃的接面深度。自動對準金屬矽化物層15a可在與側壁間隔單元24a的邊緣相鄰處形成且不超出第一NLDD區域14，其中自動對準金屬矽化物層15a可以是鈷自動對準金屬矽化物或鎳自動對準金屬矽化物。
在閘極電極20的右側，I/O P阱12所設置的汲極架構耦接於I/O焊墊(pad)。汲極架構可包括第二NLDD區域16、P型袋狀區域17、N+汲極區域18和自動對準金屬矽化物層18a。其中，第二NLDD區域16位於側壁間隔單元24b下方，P型袋狀區域17在第二NLDD區域16周圍，N+汲極區域18與第二NLDD區域16相鄰。第二NLDD區域16可以是由核心元件的LDD植入製程所形成的一核心LDD區域。NMOS電晶體100在其汲極架構中不包括I/O NLDD或任何額外的ESD植入。NMOS電晶體100具有一非對稱的LDD結構。第二NLDD區域16的摻雜濃度大於第一NLDD區域14的摻雜濃度。通過合併第二NLDD區域16和P型袋狀區域17以及從汲極架構中消除I/O NLDD，能夠減少ESD元件的接面崩潰電壓並獲得更好的ESD性能。
第二NLDD區域16可與核心元件的核心NLDD植入同時形成。根據一個實施例，第二NLDD區域16可通過植入N型摻雜物形成，其中N型摻雜物例如一定量(比如5×1014 ~3×1015 atoms/cm2 )的砷，且第二NLDD區域16可有大約200~900埃的接面深度。P型袋狀區域17可由核心元件製程中執行的環型佈植所形成。根據一個實施例，P型袋狀區域17可通過植入P型摻雜物形成，其中P型摻雜物例如一定量(比如1×1013 ~9×1013 atoms/cm2 )的銦、硼或二氟化硼，且P型袋狀區域17可有大約200~900埃的接面深度。例如，自動對準金屬矽化物層18a可以是鈷自動對準金屬矽化物或鎳自動對準金屬矽化物，自動對準金屬矽化物層18a和側壁間隔單元24b的邊緣偏移d以防止洩漏。
NMOS電晶體200通過共用N+源極區域15和NMOS電晶體100串聯，其中N+源極區域15也作為NMOS電晶體200的汲極。NMOS電晶體100是非對稱NMOS電晶體架構，其源極一側具有一I/O NLDD，汲極一側具有核心NLDD/袋狀，不同於NMOS電晶體100，NMOS電晶體200是對稱NMOS電晶體架構，其源極和汲極均具有一I/O NLDD。如第2圖所示，NMOS電晶體200包括I/O P阱12上設置的閘極電極50，且閘極電極50和閘極電極20相鄰。可以在閘極電極50和I/O P阱12之間設置閘極介電層52。閘極介電層52可以由I/O元件的閘極介電層形成。側壁間隔單元54a和側壁間隔單元54b可在閘極電極50的两個相對的側壁處形成。側壁間隔單元54a和54b可包含介電材料，例如氧化矽、氮化矽、氮氧化矽或其組合。在閘極電極50的左側，I/O P阱12設置的源極與VSS或地相連。I/O NLDD 44a位於側壁間隔單元54a下方，I/O NLDD 44b位於側壁間隔單元54b下方，以便NMOS電晶體200具有對稱的LDD結構。N+源極區域45(與I/O NLDD 44a合併)與N+源極區域15和18同時形成，其中I/O NLDD 44a和側壁間隔單元54a相鄰。自動對準金屬矽化物層45a位於N+源極區域45之上。N+源極區域45可在側壁間隔單元44a和44b形成之後形成。N+源極區域45可通過在I/O P阱12中植入N型摻雜物形成，N型摻雜物例如一定量(如1×1015 ~5×1015 atoms/cm2 )的砷。舉例來說，根據本發明，N+源極區域45可有大約800~1,500埃的接面深度。
當然，本發明也可適用於PMOS電晶體，比如將NLDD區域14和N+源極區域45等分別替換為PLDD區域和P+源極區域等。
第3圖是根據本發明另一實施例的ESD元件1a的橫斷面示意圖。可知根據本發明的另一個實施例，第2圖的NMOS電晶體100可由ESD元件1a所取代。如第3圖所示，ESD元件1a具有與第1圖所描述的ESD元件1相似的架構，然而，汲極架構40a是不同的。在閘極電極20的右側，在I/O P阱12中設置汲極架構40a，且汲極架構40a與源極架構30相對。汲極架構40a可包括第二NLDD區域16、P型袋狀區域17、N+汲極區域18、ESD植入區域68和自動對準金屬矽化物層18a。其中，第二NLDD區域16位於側壁間隔單元24b下方，P型袋狀區域17在第二NLDD區域16周圍，ESD植入區域68位於N+汲極區域18之下，自動對準金屬矽化物層18a位於N+汲極區域18之上。ESD元件1a也具有非對稱的LDD結構。第二NLDD區域16的摻雜濃度大於第一NLDD區域14的摻雜濃度。通過合併第二NLDD區域16和P型袋狀區域17以及從汲極架構40a中消除I/O NLDD，能夠減少ESD元件的接面崩潰電壓並獲得更好的ESD性能。第1圖中ESD元件1和第3圖中ESD元件1a的區別之處在於第3圖中ESD元件1a在其汲極架構40a中併入一額外的ESD植入區域68。根據一個實施例，ESD植入區域68為一P型摻雜區域。當然，本發明也可適用於PMOS電晶體，比如，ESD植入區域68可由N型摻雜區域所取代。
第4圖是根據本發明另一個實施例的ESD元件1b的橫斷面示意圖。可知根據本發明另一個實施例，第2圖中的NMOS電晶體100可由ESD元件1b取代。如第4圖所示，ESD元件1b可具有與第1圖所描述的ESD元件1相似的架構，然而，汲極架構40b是不同的。在閘極電極20的右側，在I/O P阱12中設置汲極架構40b，且汲極架構40b與源極架構30相對。汲極架構40b可包括I/O NLDD區域14b、核心NLDD區域16a、P型袋狀區域17、N+汲極區域18和自動對準金屬矽化物層18a。其中，核心NLDD區域16a位於側壁間隔單元24b下方，P型袋狀區域17在核心NLDD區域16a周圍，自動對準金屬矽化物層18a位於N+汲極區域18之上。I/O NLDD區域14a和14b同時形成且因此大致具有相同的摻雜濃度。I/O NLDD區域14b可大致包圍核心NLDD區域16a。ESD元件1b具有非對稱的LDD結構。因此，本實施例中的第二NLDD區域包括核心元件的LDD植入製程所形成的核心NLDD區域16a與I/O元件的LDD植入製程所形成的I/O NLDD區域14b。核心NLDD區域16a的摻雜濃度大於第一NLDD區域14a的摻雜濃度。通過將核心NLDD區域16a和P型袋狀區域17合併進汲極架構40b，能夠減少ESD元件1b的接面崩潰電壓並獲得更好的ESD性能。當然，本發明也可適用於PMOS電晶體，比如將NLDD區域14a和N+源極區域15等分別替換為PLDD區域和P+源極區域等。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1、1a、1b．．．ESD元件
2．．．級聯I/O ESD元件
10．．．半導體基底
12．．．I/O P阱
14．．．第一NLDD區域
14a、14b．．．I/O NLDD區域
15、45．．．N+源極區域
15a、18a、45a．．．自動對準金屬矽化物層
16．．．第二NLDD區域
16a．．．核心NLDD區域
17．．．P型袋狀區域
18．．．N+汲極區域
20、50．．．閘極電極
22、52．．．閘極介電層
24a、24b、54a、54b．．．側壁間隔單元
30．．．源極架構
40、40a、40b．．．汲極架構
44a、44b．．．I/O NLDD
68．．．ESD植入區域
100、200．．．NMOS電晶體
第1圖是根據本發明一個實施例的ESD元件的橫斷面示意圖。
第2圖是根據本發明另一個實施例的級聯I/O ESD元件的橫斷面示意圖。
第3圖是根據本發明另一實施例的ESD元件的橫斷面示意圖。
第4圖是根據本發明另一個實施例的ESD元件的橫斷面示意圖。
1．．．ESD元件
10．．．半導體基底
12．．．I/O P阱
14．．．第一NLDD區域
15．．．N+源極區域
15a、18a．．．自動對準金屬矽化物層
16．．．第二NLDD區域
17．．．P型袋狀區域
18．．．N+汲極區域
20．．．閘極電極
22．．．閘極介電層
24a、24b．．．側壁間隔單元
30．．．源極架構
40．．．汲極架構

Claims (21)

  1. 一種輸入/輸出靜電放電元件，包括：一閘極電極，位於一基底之上；一閘極介電層，位於所述閘極電極和所述基底之間；一對側壁間隔單元，分別位於所述閘極電極的兩個相對的側壁；一第一輕摻雜汲極區域，位於一個所述側壁間隔單元之下；一源極區域，與所述第一輕摻雜汲極區域相鄰；一第二輕摻雜汲極區域，位於另一個所述側壁間隔單元之下；以及一汲極區域，與所述第二輕摻雜汲極區域相鄰；其中所述第二輕摻雜汲極區域的摻雜濃度大於所述第一輕摻雜汲極區域的摻雜濃度，且所述第一輕摻雜汲極區域、所述第二輕摻雜汲極區域、所述源極區域和所述汲極區域均位於一輸入/輸出P阱中。
  2. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，其中所述第一輕摻雜汲極區域是由一輸入/輸出元件之一輕摻雜汲極植入製程所形成的一輸入/輸出輕摻雜汲極區域，所述第二輕摻雜汲極區域是由一核心元件之一輕摻雜汲極植入製程所形成的一核心輕摻雜汲極區域。
  3. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，其中所述第一輕摻雜汲極區域是由一輸入/輸出元件之一輕摻雜汲極植入製程所形成的一輸入/輸出輕摻雜汲極區域，以及所述第二輕摻雜汲極區域是一核心輕摻雜汲極區域加上一輸入/輸出輕摻雜汲極區域，其中所述核心輕摻雜汲極區域是由一核心元件之一輕摻雜汲極植入製程所形成， 以及所述輸入/輸出輕摻雜汲極區域是由一輸入/輸出元件之一輕摻雜汲極植入製程所形成。
  4. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，其中所述汲極區域耦接於一輸入/輸出焊墊。
  5. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，其中所述閘極介電層由一輸入/輸出元件之一閘極介電層所形成。
  6. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，所述輸入/輸出靜電放電元件進一步包括一袋狀區域，位於所述第二輕摻雜汲極區域周圍。
  7. 如申請專利範圍第6項所述之輸入/輸出靜電放電元件，其中所述袋狀區域是由一核心元件製程中執行的一環型佈植所形成。
  8. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，其中所述第一輕摻雜汲極區域是一輸入/輸出N型輕摻雜汲極區域，且所述第一輕摻雜汲極區域具有300~1,000埃的接面深度。
  9. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，其中所述第二輕摻雜汲極區域是一核心N型輕摻雜汲極區域，且所述第二輕摻雜汲極區域具有200~900埃的接面深度。
  10. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，所述輸入/輸出靜電放電元件進一步包括一源極自動對準金屬矽化物層，位於所述源極區域之上。
  11. 如申請專利範圍第1項所述之輸入/輸出靜電放電元件，所述輸入/輸出靜電放電元件進一步包括一汲極自動對準金屬矽化物層，位於所述汲極區域之上，且所述汲極自動對準金屬矽化物層和所述側壁間隔單元的邊緣有一偏移以防止洩漏。
  12. 一種級聯輸入/輸出靜電放電元件，包括：一第一MOS電晶體，具有一閘極電極、一源極架構和一汲極架構；以及一第二MOS電晶體，通過共用所述第一MOS電晶體的所述源極架構與所述第一MOS電晶體串聯；其中所述第一MOS電晶體的所述源極架構包括一第一輕摻雜汲極區域，所述第一MOS電晶體的所述汲極架構包括一第二輕摻雜汲極區域，且所述第二輕摻雜汲極區域的摻雜濃度大於所述第一輕摻雜汲極區域的摻雜濃度。
  13. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述第一輕摻雜汲極區域是由一輸入/輸出元件之一輕摻雜汲極植入製程所形成的一輸入/輸出輕摻雜汲極區域，所述第二輕摻雜汲極區域是由一核心元件之一輕摻雜汲極植入製程所形成的一核心輕摻雜汲極區域。
  14. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述第一輕摻雜汲極區域是由一輸入/輸出元件之一輕摻雜汲極植入製程所形成的一輸入/輸出輕摻雜汲極區域，所述第二輕摻雜汲極區域是一核心輕摻雜汲極區域加上一輸入/輸出輕摻雜汲極區域，其中所述核心輕摻雜汲極區域由一核心元件之一輕摻雜汲極植入製程所形成，以及所述輸入/輸出輕摻雜汲極區域由一輸入/輸出元件之一輕摻雜汲極植入製程所形成。
  15. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述源極架構進一步包括一源極區域，所述源極區域與所述第一輕摻雜汲極區域相鄰。
  16. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述汲極架構進一步包括一汲極區域，所述汲極區域與所述第二輕摻雜汲極區域相鄰。
  17. 如申請專利範圍第16項所述之級聯輸入/輸出靜電放電元件，其中所述汲極區域耦接於一輸入/輸出焊墊。
  18. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中位於所述閘極電極之下的一閘極介電層由一輸入/輸出元件之一閘極介電層所形成。
  19. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述第一MOS電晶體和所述第二MOS電晶體均為NMOS電晶體。
  20. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述汲極架構進一步包括一袋狀區域，位於所述第二輕摻雜汲極區域周圍。
  21. 如申請專利範圍第12項所述之級聯輸入/輸出靜電放電元件，其中所述源極架構也作為所述第二MOS電晶體的一汲極。
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