CN101997031A - 输入/输出静电放电元件与级联输入/输出静电放电元件 - Google Patents

输入/输出静电放电元件与级联输入/输出静电放电元件 Download PDF

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CN101997031A
CN101997031A CN2009101810058A CN200910181005A CN101997031A CN 101997031 A CN101997031 A CN 101997031A CN 2009101810058 A CN2009101810058 A CN 2009101810058A CN 200910181005 A CN200910181005 A CN 200910181005A CN 101997031 A CN101997031 A CN 101997031A
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lightly doped
doped drain
zone
electrostatic discharging
drain zone
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李东兴
林奕成
曹卫立
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MediaTek Inc
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Abstract

本发明提供输入/输出静电放电元件与级联输入/输出静电放电元件，其中输入/输出静电放电元件，包括栅极电极，位于衬底之上；栅极介质层，位于所述栅极电极和所述衬底之间；一对侧壁隔离单元，分别位于所述栅极电极的两个相对的侧壁；第一LDD区域，位于一个所述侧壁隔离单元之下；源极区域，与所述第一LDD区域相邻；第二LDD区域，位于另一个所述侧壁隔离单元之下；以及漏极区域，与所述第二LDD区域相邻；其中所述第二LDD区域的掺杂浓度大于所述第一LDD区域的掺杂浓度。利用本发明能够减少ESD元件的结击穿电压并获得更好的ESD性能。

Description

输入/输出静电放电元件与级联输入/输出静电放电元件
技术领域
本发明有关于集成电路(integrated circuits，以下简称为IC)，尤其有关于具有较低的结击穿电压(junction breakdown voltage)和较好的静电放电(electrostatic discharge，以下简称为ESD)防护性能的输入/输出(input/output，以下简称为I/O)ESD元件。
背景技术
IC芯片与芯片外(off-chip)的电子元件进行电通信以交换信息。IC芯片可利用与芯片外电子元件所用电压不同的电压。于是，IC芯片和芯片外电子元件之间的接口必须能够容纳电压差。此种接口包含混合电压I/O驱动器。
传统的ESD防护架构包括两个级联(casade)结构的N型金属氧化物半导体(Negative Metal Oxide Semiconductor，NMOS)晶体管，这两个NMOS晶体管合并为衬底(substrate)的相同有效区(active area)。例如，当在静电放电期间提供寄生横向NPN双极型晶体管(parasitic lateral NPN bipolartransistor)时，两个NMOS晶体管允许5V信号在正常运作期间降至3.3V。在ESD条件下，当底端NMOS晶体管的源极和顶端NMOS晶体管的漏极之间产生双极效应时，堆叠(stacked)晶体管运作于骤回(snapback)。
当此I/O驱动器已用于一些通用设计，如何平衡ESD防护性能和I/O性能则继续成为一种挑战。于是，期望提升级联MOS驱动器的性能和ESD元件的ESD防护性能。更具体地讲，需要从驱动器消除ESD的设计约束以达到最大的I/O性能。
发明内容
有鉴于此，本发明提供输入/输出静电放电元件与级联输入/输出静电放电元件。
依据本发明一个实施例提供一种输入/输出静电放电元件，包括：栅极电极，位于衬底之上；栅极介质层，位于所述栅极电极和所述衬底之间；对侧壁隔离单元，分别位于所述栅极电极的两个相对的侧壁；第一LDD区域，位于一个所述侧壁隔离单元之下；源极区域，与所述第一LDD区域相邻；第二LDD区域，位于另一个所述侧壁隔离单元之下；以及漏极区域，与所述第二LDD区域相邻；其中所述第二LDD区域的掺杂浓度大于所述第一LDD区域的掺杂浓度。
依据本发明另一个实施例提供一种级联输入/输出静电放电元件，包括：第一MOS晶体管，具有栅极电极、源极架构和漏极架构；以及第二MOS晶体管，通过共享所述第一MOS晶体管的所述源极架构与所述第一MOS晶体管串联；其中所述第一MOS晶体管的所述源极架构包括第一LDD区域，所述第一MOS晶体管的所述漏极架构包括第二LDD区域，且所述第二LDD区域的掺杂浓度大于所述第一LDD区域的掺杂浓度。
利用本发明能够减少ESD元件的结击穿电压并获得更好的ESD性能。
以下根据多个图式对本发明的较佳实施例进行详细描述，所属领域技术人员阅读后可明确了解本发明的目的。
附图说明
图1是根据本发明一个实施例的ESD元件的横断面示意图。
图2是根据本发明另一个实施例的级联I/O ESD元件的横断面示意图。
图3是根据本发明另一个实施例的ESD元件的横断面示意图。
图4是根据本发明另一个实施例的ESD元件的横断面示意图。
具体实施方式
在权利要求书及说明书当中使用了某些词汇来指称特定的元件。所属领域中的普通技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本发明的权利要求书及说明书并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及后续的请求项当中所提及的“包含”为开放式的用语，故应解释成“包含但不限定于”。以外，“耦接”一词在此包含任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接于该第二装置，或通过其他装置或连接手段间接地电气连接至该第二装置。
图1是根据本发明一个实施例的ESD元件1的横断面示意图。如图1所示，于I/O P阱(well)12形成ESD元件1，且I/O P阱12设置于半导体衬底10(如P型硅衬底)上。根据本实施例，ESD元件1是NMOS晶体管且于I/O元件区域中制造。当然，本发明也适用于P型金属氧化物半导体(Positive Metal OxideSemiconductor，PMOS)晶体管。ESD元件1包括I/O P阱12区域上设置的栅极电极20。栅极电极20可为堆叠架构，包括导体和绝缘体，导体例如多晶硅层(polysilicon layer)、金属或金属硅化物(metal silicide)；绝缘体例如用于封装导体的氮化硅(silicon nitride)。当然，栅极电极20可为通常用于I/O元件的任一适合的栅极架构。
可在栅极电极20和I/O P阱12之间设置栅极介质层22。栅极介质层22可由I/O元件的栅极介质层形成。栅极介质层22可与I/O元件同时形成且因此相较于核心(core)元件的厚度，栅极介质层22具有更厚的厚度。举例来说，基于65纳米(nm)技术节点，栅极介质层22有大约35～70埃(angstrom)的厚度，而核心元件(图中未示)具有10～25埃的厚度。侧壁隔离单元(sidewall spacer)24a和侧壁隔离单元24b可在栅极电极20的两个相对的侧壁上形成。侧壁隔离单元24a和24b可包括介电材料，例如氧化硅(silicon oxide)、氮化硅、氮氧化硅(siliconoxynitride)或其组合。在一个实施例中侧壁隔离单元24a和24b进一步包括衬垫(liner)，比如氧化衬垫。
在栅极电极20的左侧，于I/O P阱12中设置源极架构30。源极架构30可包括第一N型轻掺杂漏极(N-type lightly doped drain，NLDD)区域14、N+源极区域15以及自对准多晶硅化物层(salicide layer)15a。其中，第一NLDD区域14位于侧壁隔离单元24a下方，N+源极区域15与第一NLDD区域14相邻，自对准多晶硅化物层15a位于N+源极区域15之上。第一NLDD区域14可以是I/O元件的轻掺杂漏极(Lightly Doped Drain，LDD)植入工艺所形成的I/O NLDD区域。
举例来说，根据一个实施例，第一NLDD区域14可通过植入N型掺杂物(dopant)形成，其中N型掺杂物例如一定量的磷(phosphorus)和砷(arsenic)，比如2×1013～8×1013atoms/cm2，且第一NLDD区域14可有大约300～1,000埃的结深度。在一个实施例中，N+源极区域15可在侧壁隔离单元24a和24b形成之后形成。N+源极区域15可通过在I/O P阱12中植入N型掺杂物形成，N型掺杂物例如一定量(如1×1015～5×1015atoms/cm2)的砷。举例来说，根据本发明，N+源极区域15可有大约800～1,500埃的结深度。自对准多晶硅化物层15a可在与侧壁隔离单元24a的边缘相邻处形成且不超出第一NLDD区域14，其中自对准多晶硅化物层15a可以是钴(cobalt)自对准多晶硅化物或镍(nickel)自对准多晶硅化物。
在栅极电极20的右侧，于I/O P阱12设置漏极架构40，且漏极架构40与源极架构30相对。漏极架构40可包括第二NLDD区域16、P型袋状(pocket)区域17、N+漏极区域18和自对准多晶硅化物层18a。其中，第二NLDD区域16位于侧壁隔离单元24b下方，P型袋状区域17在第二NLDD区域16周围，N+漏极区域18与第二NLDD区域16相邻，自对准多晶硅化物层18a在N+漏极区域18之上。N+漏极区域18耦接I/O焊垫。第二NLDD区域16可以是核心元件的LDD植入工艺所形成的核心LDD区域。本实施例的一个特点就是ESD元件1具有非对称的LDD结构。第二NLDD区域16的掺杂浓度(doping concentration)大于第一NLDD区域14的掺杂浓度。为了具有非对称的LDD结构，本实施例中的ESD元件1在其漏极架构40不包括I/O NLDD或任何额外的ESD植入，而是将第二NLDD区域16与环型植入(halo implantation)合并，此处的环型植入例如P型袋状区域17。通过合并第二NLDD区域16和P型袋状区域17以及从漏极架构40中消除I/O NLDD，能够减少ESD元件1的结击穿电压并获得更好的ESD性能。
第二NLDD区域16可与核心元件的核心NLDD植入同时形成。根据一个实施例，第二NLDD区域16可通过植入N型掺杂物形成，其中N型掺杂物例如一定量(比如5×1014～3×1015atoms/cm2)的砷，且第二NLDD区域16可有大约200～900埃的结深度。P型袋状区域17可由核心元件工艺中执行的环型植入所形成。根据一个实施例，P型袋状区域17可通过植入P型掺杂物形成，其中P型掺杂物例如一定量(比如1×1013～9×1013atoms/cm2)的铟(In)、硼(B)或二氟化硼(BF2)，且P型袋状区域17可有大约200～900埃的结深度。例如，自对准多晶硅化物层18a可以是钴自对准多晶硅化物或镍自对准多晶硅化物，自对准多晶硅化物层18a和侧壁隔离单元24b的边缘偏移d以防止泄漏(leakage)。然而，在另一个实施例中，自对准多晶硅化物层18a和侧壁隔离单元24b之间没有偏移。当然，本发明也可适用于PMOS晶体管，比如将NLDD区域14和N+源极区域15等分别替换为PLDD区域和P+源极区域等。
图2是根据本发明另一个实施例的级联I/O ESD元件2的横断面示意图。如图2所示，级联I/O ESD元件2包括级联结构的两个NMOS晶体管100和200，其中NMOS晶体管100具有与图1所描述的ESD元件1相似的架构。NMOS晶体管100可包括于I/O P阱12之上设置的栅极电极20。在栅极电极20和I/O P阱12之间设置栅极介质层22。栅极介质层22可由I/O元件的栅极介质层形成。侧壁隔离单元24a和侧壁隔离单元24b在栅极电极20的两个相对的侧壁形成。侧壁隔离单元24a和侧壁隔离单元24b可包括介电材料，例如氧化硅、氮化硅、氮氧化硅或其组合。在栅极电极20的左侧，在I/O P阱12中设置源极架构。源极架构可包括第一NLDD区域14、N+源极区域15和自对准多晶硅化物层15a。其中，第一NLDD区域14位于侧壁隔离单元24a下方，N+源极区域15与第一NLDD区域14相邻。第一NLDD区域14是由I/O元件的LDD植入工艺所形成的I/O NLDD区域。例如，根据一个实施例，第一NLDD区域14可通过植入N型掺杂物形成，其中N型掺杂物例如一定量(比如2×1013～8×1013atoms/cm2)的磷和砷，且第一NLDD区域14可有大约300～1,000埃的结深度。在一个实施例中，N+源极区域15可在侧壁隔离单元24a和24b形成之后形成。N+源极区域15可通过在I/O P阱12中植入N型掺杂物形成，N型掺杂物例如一定量(如1×1015～5×1015atoms/cm2)的砷。举例来说，根据本发明，N+源极区域15可有大约800～1,500埃的结深度。自对准多晶硅化物层15a可在与侧壁隔离单元24a的边缘相邻处形成且不超出第一NLDD区域14，其中自对准多晶硅化物层15a可以是钴自对准多晶硅化物或镍自对准多晶硅化物。
在栅极电极20的右侧，I/O P阱12所设置的漏极架构耦接于I/O焊垫。漏极架构可包括第二NLDD区域16、P型袋状区域17、N+漏极区域18和自对准多晶硅化物层18a。其中，第二NLDD区域16位于侧壁隔离单元24b下方，P型袋状区域17在第二NLDD区域16周围，N+漏极区域18与第二NLDD区域16相邻。第二NLDD区域16可以是由核心元件的LDD植入工艺所形成的核心LDD区域。NMOS晶体管100在其漏极架构中不包括I/O NLDD或任何额外的ESD植入。NMOS晶体管100具有非对称的LDD结构。第二NLDD区域16的掺杂浓度大于第一NLDD区域14的掺杂浓度。通过合并第二NLDD区域16和P型袋状区域17以及从漏极架构中消除I/O NLDD，能够减少ESD元件的结击穿电压并获得更好的ESD性能。
第二NLDD区域16可与核心元件的核心NLDD植入同时形成。根据一个实施例，第二NLDD区域16可通过植入N型掺杂物形成，其中N型掺杂物例如一定量(比如5×1014～3×1015atoms/cm2)的砷，且第二NLDD区域16可有大约200～900埃的结深度。P型袋状区域17可由核心元件工艺中执行的环型植入所形成。根据一个实施例，P型袋状区域17可通过植入P型掺杂物形成，其中P型掺杂物例如一定量(比如1×1013～9×1013atoms/cm2)的铟、硼或二氟化硼，且P型袋状区域17可有大约200～900埃的结深度。例如，自对准多晶硅化物层18a可以是钴自对准多晶硅化物或镍自对准多晶硅化物，自对准多晶硅化物层18a和侧壁隔离单元24b的边缘偏移d以防止泄漏。
NMOS晶体管200通过共享N+源极区域15和NMOS晶体管100串联，其中N+源极区域15也作为NMOS晶体管200的漏极。NMOS晶体管100是非对称NMOS晶体管架构，其源极一侧具有I/O NLDD，漏极一侧具有核心NLDD/袋状，不同于NMOS晶体管100，NMOS晶体管200是对称NMOS晶体管架构，其源极和漏极均具有I/O NLDD。如图2所示，NMOS晶体管200包括I/O P阱12上设置的栅极电极50，且栅极电极50和栅极电极20相邻。可以在栅极电极50和I/O P阱12之间设置栅极介质层52。栅极介质层52可以由I/O元件的栅极介质层形成。侧壁隔离单元54a和侧壁隔离单元54b可在栅极电极50的两个相对的侧壁处形成。侧壁隔离单元54a和54b可包含介电材料，例如氧化硅、氮化硅、氮氧化硅或其组合。在栅极电极50的左侧，I/O P阱12设置的源极与VSS或地相连。I/O NLDD 44a位于侧壁隔离单元54a下方，I/O NLDD 44b位于侧壁隔离单元54b下方，以便NMOS晶体管200具有对称的LDD结构。N+源极区域45(与I/O NLDD 44a合并)与N+源极区域15和18同时形成，其中I/O NLDD 44a和侧壁隔离单元54a相邻。自对准多晶硅化物层45a位于N+源极区域45之上。N+源极区域45可在侧壁隔离单元44a和44b形成之后形成。N+源极区域45可通过在I/O P阱12中植入N型掺杂物形成，N型掺杂物例如一定量(如1×1015～5×1015atoms/cm2)的砷。举例来说，根据本发明，N+源极区域45可有大约800～1,500埃的结深度。
当然，本发明也可适用于PMOS晶体管，比如将NLDD区域14和N+源极区域45等分别替换为PLDD区域和P+源极区域等。
图3是根据本发明另一实施例的ESD元件1a的横断面示意图。可知根据本发明的另一个实施例，图2的NMOS晶体管100可由ESD元件1a所取代。如图3所示，ESD元件1a具有与图1所描述的ESD元件1相似的架构，然而，漏极架构40a是不同的。在栅极电极20的右侧，在I/O P阱12中设置漏极架构40a，且漏极架构40a与源极架构30相对。漏极架构40a可包括第二NLDD区域16、P型袋状区域17、N+漏极区域18、ESD植入区域68和自对准多晶硅化物层18a。其中，第二NLDD区域16位于侧壁隔离单元24b下方，P型袋状区域17在第二NLDD区域16周围，ESD植入区域68位于N+漏极区域18之下，自对准多晶硅化物层18a位于N+漏极区域18之上。ESD元件1a也具有非对称的LDD结构。第二NLDD区域16的掺杂浓度大于第一NLDD区域14的掺杂浓度。通过合并第二NLDD区域16和P型袋状区域17以及从漏极架构40a中消除I/O NLDD，能够减少ESD元件的结击穿电压并获得更好的ESD性能。图1中ESD元件1和图3中ESD元件1a的区别之处在于图3中ESD元件1a在其漏极架构40a中并入额外的ESD植入区域68。根据一个实施例，ESD植入区域68为P型掺杂区域。当然，本发明也可适用于PMOS晶体管，比如，ESD植入区域68可由N型掺杂区域所取代。
图4是根据本发明另一个实施例的ESD元件1b的横断面示意图。可知根据本发明另一个实施例，图2中的NMOS晶体管100可由ESD元件1b取代。如图4所示，ESD元件1b可具有与图1所描述的ESD元件1相似的架构，然而，漏极架构40b是不同的。在栅极电极20的右侧，在I/O P阱12中设置漏极架构40b，且漏极架构40b与源极架构30相对。漏极架构40b可包括I/O NLDD区域14b、核心NLDD区域16a、P型袋状区域17、N+漏极区域18和自对准多晶硅化物层18a。其中，核心NLDD区域16a位于侧壁隔离单元24b下方，P型袋状区域17在核心NLDD区域16a周围，自对准多晶硅化物层18a位于N+漏极区域18之上。I/O NLDD区域14a和14b同时形成且因此大致具有相同的掺杂浓度。I/ONLDD区域14b可大致包围核心NLDD区域16a。ESD元件1b具有非对称的LDD结构。因此，本实施例中的第二NLDD区域包括核心元件的LDD植入工艺所形成的核心NLDD区域16a与I/O元件的LDD植入工艺所形成的I/O NLDD区域14b。核心NLDD区域16a的掺杂浓度大于第一NLDD区域14a的掺杂浓度。通过将核心NLDD区域16a和P型袋状区域17合并进漏极架构40b，能够减少ESD元件1b的结击穿电压并获得更好的ESD性能。当然，本发明也可适用于PMOS晶体管，比如将NLDD区域14a和N+源极区域15等分别替换为PLDD区域和P+源极区域等。
虽然本发明已就较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作各种的变更和润饰。

Claims (22)

1.一种输入/输出静电放电元件，其特征在于，包括：
栅极电极，位于衬底之上；
栅极介质层，位于所述栅极电极和所述衬底之间；
一对侧壁隔离单元，分别位于所述栅极电极的两个相对的侧壁；
第一轻掺杂漏极区域，位于一个所述侧壁隔离单元之下；
源极区域，与所述第一轻掺杂漏极区域相邻；
第二轻掺杂漏极区域，位于另一个所述侧壁隔离单元之下；以及
漏极区域，与所述第二轻掺杂漏极区域相邻；
其中所述第二轻掺杂漏极区域的掺杂浓度大于所述第一轻掺杂漏极区域的掺杂浓度。
2.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述第一轻掺杂漏极区域是由输入/输出元件的轻掺杂漏极植入工艺所形成的输入/输出轻掺杂漏极区域，所述第二轻掺杂漏极区域是由核心元件的轻掺杂漏极植入工艺所形成的核心轻掺杂漏极区域。
3.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述第一轻掺杂漏极区域是由输入/输出元件的轻掺杂漏极植入工艺所形成的输入/输出轻掺杂漏极区域，以及所述第二轻掺杂漏极区域是核心轻掺杂漏极区域加上输入/输出轻掺杂漏极区域，其中所述核心轻掺杂漏极区域是由核心元件的轻掺杂漏极植入工艺所形成，以及所述输入/输出轻掺杂漏极区域是由输入/输出元件的轻掺杂漏极植入工艺所形成。
4.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述漏极区域耦接于输入/输出焊垫。
5.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述栅极介质层由输入/输出元件的栅极介质层所形成。
6.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述输入/输出静电放电元件进一步包括袋状区域，位于所述第二轻掺杂漏极区域周围。
7.如权利要求6所述的输入/输出静电放电元件，其特征在于，所述袋状区域是由核心元件工艺中执行的环型植入所形成。
8.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述第一轻掺杂漏极区域是输入/输出N型轻掺杂漏极区域，且所述第一轻掺杂漏极区域具有300～1,000埃的结深度。
9.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述第二轻掺杂漏极区域是核心N型轻掺杂漏极区域，且所述第二轻掺杂漏极区域具有200～900埃的结深度。
10.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述输入/输出静电放电元件进一步包括源极自对准多晶硅化物层，位于所述源极区域之上。
11.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述输入/输出静电放电元件进一步包括漏极自对准多晶硅化物层，位于所述漏极区域之上，且所述漏极自对准多晶硅化物层和所述侧壁隔离单元的边缘有偏移以防止泄漏。
12.如权利要求1所述的输入/输出静电放电元件，其特征在于，所述第一轻掺杂漏极区域、所述第二轻掺杂漏极区域、所述源极区域和所述漏极区域均位于输入/输出P阱中。
13.一种级联输入/输出静电放电元件，其特征在于，包括：
第一MOS晶体管，具有栅极电极、源极架构和漏极架构；以及
第二MOS晶体管，通过共享所述第一MOS晶体管的所述源极架构与所述第一MOS晶体管串联；
其中所述第一MOS晶体管的所述源极架构包括第一轻掺杂漏极区域，所述第一MOS晶体管的所述漏极架构包括第二轻掺杂漏极区域，且所述第二轻掺杂漏极区域的掺杂浓度大于所述第一轻掺杂漏极区域的掺杂浓度。
14.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述第一轻掺杂漏极区域是由输入/输出元件的轻掺杂漏极植入工艺所形成的输入/输出轻掺杂漏极区域，所述第二轻掺杂漏极区域是由核心元件的轻掺杂漏极植入工艺所形成的核心轻掺杂漏极区域。
15.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述第一轻掺杂漏极区域是由输入/输出元件的轻掺杂漏极植入工艺所形成的输入/输出轻掺杂漏极区域，所述第二轻掺杂漏极区域是核心轻掺杂漏极区域加上输入/输出轻掺杂漏极区域，其中所述核心轻掺杂漏极区域由核心元件的轻掺杂漏极植入工艺所形成，以及所述输入/输出轻掺杂漏极区域由输入/输出元件的轻掺杂漏极植入工艺所形成。
16.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述源极架构进一步包括源极区域，所述源极区域与所述第一轻掺杂漏极区域相邻。
17.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述漏极架构进一步包括漏极区域，所述漏极区域与所述第二轻掺杂漏极区域相邻。
18.如权利要求17所述的级联输入/输出静电放电元件，其特征在于，所述漏极区域耦接于输入/输出焊垫。
19.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，位于所述栅极电极之下的栅极介质层由输入/输出元件的栅极介质层所形成。
20.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述第一MOS晶体管和所述第二MOS晶体管均为NMOS晶体管。
21.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述漏极架构进一步包括袋状区域，位于所述第二轻掺杂漏极区域周围。
22.如权利要求13所述的级联输入/输出静电放电元件，其特征在于，所述源极架构也作为所述第二MOS晶体管的漏极。
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