TWI407369B - 具功率感知之指令引退裝置、方法及系統 - Google Patents

具功率感知之指令引退裝置、方法及系統 Download PDF

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Publication number
TWI407369B
TWI407369B TW098120442A TW98120442A TWI407369B TW I407369 B TWI407369 B TW I407369B TW 098120442 A TW098120442 A TW 098120442A TW 98120442 A TW98120442 A TW 98120442A TW I407369 B TWI407369 B TW I407369B
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TW
Taiwan
Prior art keywords
instruction
logic
signal
buffer
retirement
Prior art date
Application number
TW098120442A
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English (en)
Chinese (zh)
Other versions
TW201015435A (en
Inventor
Zeev Sperber
Rafi Marom
Ofer Levy
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201015435A publication Critical patent/TW201015435A/zh
Application granted granted Critical
Publication of TWI407369B publication Critical patent/TWI407369B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Power Sources (AREA)
TW098120442A 2008-06-27 2009-06-18 具功率感知之指令引退裝置、方法及系統 TWI407369B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/215,526 US7921280B2 (en) 2008-06-27 2008-06-27 Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array

Publications (2)

Publication Number Publication Date
TW201015435A TW201015435A (en) 2010-04-16
TWI407369B true TWI407369B (zh) 2013-09-01

Family

ID=41360915

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098120442A TWI407369B (zh) 2008-06-27 2009-06-18 具功率感知之指令引退裝置、方法及系統

Country Status (8)

Country Link
US (1) US7921280B2 (ja)
JP (1) JP5474926B2 (ja)
CN (1) CN101615115B (ja)
DE (1) DE102009029852A1 (ja)
GB (1) GB2473345B (ja)
RU (1) RU2427883C2 (ja)
TW (1) TWI407369B (ja)
WO (1) WO2009158247A2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130080141A1 (en) * 2011-09-23 2013-03-28 National Tsing Hua University Power aware simulation system with embedded multi-core dsp

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TW200604944A (en) * 2004-06-17 2006-02-01 Intel Corp Reducing false error detection in a microprocessor by tracking instructions neutral to errors
US7096345B1 (en) * 2003-09-26 2006-08-22 Marvell International Ltd. Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof

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US7096345B1 (en) * 2003-09-26 2006-08-22 Marvell International Ltd. Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof
TW200604944A (en) * 2004-06-17 2006-02-01 Intel Corp Reducing false error detection in a microprocessor by tracking instructions neutral to errors

Also Published As

Publication number Publication date
TW201015435A (en) 2010-04-16
GB201015011D0 (en) 2010-10-20
RU2009124521A (ru) 2011-01-10
DE102009029852A1 (de) 2009-12-31
JP5474926B2 (ja) 2014-04-16
GB2473345A (en) 2011-03-09
JP2011514607A (ja) 2011-05-06
WO2009158247A2 (en) 2009-12-30
WO2009158247A3 (en) 2010-03-04
US20090327663A1 (en) 2009-12-31
US7921280B2 (en) 2011-04-05
CN101615115A (zh) 2009-12-30
GB2473345B (en) 2012-12-05
RU2427883C2 (ru) 2011-08-27
CN101615115B (zh) 2013-12-25

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