TWI406483B - Control circuit of charge pump circuit - Google Patents

Abstract

A control circuit of a charge pump circuit is provided. The control circuit includes a ring oscillator and a load state detecting unit. The ring oscillator generates a clock signal and adjusts the frequency of the clock signal according to a first control signal, and stops generating the clock signal according to an adjusting signal. The load state detecting unit generates the first control signal and decides when to enable the first control signal according to the variety of the voltage of the output of the charge pump circuit and the adjusting signal, wherein the pulse width of the adjusting signal narrows with the decline of the value of the output voltage decreasing.

Description

Control circuit of charge pump circuit

The present invention relates to a control circuit for a charge pump circuit, and more particularly to a control circuit that can simultaneously take into account the efficiency and drive capability of a charge pump circuit.

In electronic devices, source voltages of various levels are often required, so charge pump circuits are often configured to utilize existing supply voltages to generate supply voltages of various levels.

1 is a block diagram of a conventional charge pump circuit and its control circuit. The control circuit 100 includes a voltage level detector 102 and a ring oscillator 104. The voltage level detector 102 is configured to detect the voltage level of the output voltage Vout of the charge pump circuit 106. When the output voltage Vout is less than a fixed preset voltage level, the voltage level detector 102 outputs a trigger signal. S1 to ring oscillator 104. The ring oscillator 104 determines whether to output the clock signal P1 according to the trigger signal S1, so that the charge pump circuit 106 pulls the output voltage Vout back to the normal voltage level according to the clock signal P1. Generally, when the frequency of the clock signal P1 outputted by the ring oscillator 104 is high, the driving ability of the charge pump circuit 106 is better, and the efficiency is poor. Conversely, when the clock signal P1 output by the ring oscillator 104 is high, When the frequency is low, the driving power of the charge pump circuit 106 is poor, and the efficiency is good. Since the output frequency of the ring oscillator of the conventional charge pump circuit is fixed, it is often necessary to make a trade-off between the driving ability and the efficiency of the charge pump circuit according to the actual situation when designing the circuit, and it is impossible to simultaneously consider both.

U.S. Patent Application No. 20060197583 discloses a method for increasing the efficiency of a charge pump circuit which determines the input frequency of the charge pump based on the magnitude of the load driven by the charge pump to increase the efficiency of the charge pump circuit. However, this method also uses a fixed voltage level to determine the frequency conversion of the ring oscillator, and still cannot balance the efficiency and driving capability of the charge pump. Therefore, when the output voltage drifts back and forth between the upper and lower limits of the preset voltage level, It will cause the ring oscillator to continuously switch the frequency, and reduce the efficiency of the charge pump circuit. Even the ring oscillator can not generate the clock signal required by the charge pump circuit to increase the output voltage during the frequency conversion process, resulting in the output voltage. decline.

The invention provides a control circuit of a charge pump circuit, which can simultaneously consider the efficiency and driving capability of the charge pump circuit according to the change of the load state.

The invention provides a control circuit for a charge pump circuit, comprising a ring oscillator and a load state detecting unit. The ring oscillator is coupled to the charge pump circuit and the load state detecting unit. The ring oscillator is used to generate a clock signal, adjust the frequency of the clock signal according to the first control signal, and stop generating the clock signal according to an adjustment signal. The load state detecting unit is configured to generate a first control signal, and determine a time point at which the first control signal is enabled according to a voltage drop change and an adjustment signal of the output voltage of the charge pump circuit, wherein the pulse width of the signal is adjusted according to the output voltage The voltage value decreases and becomes narrower.

In an embodiment of the present invention, when the output voltage reaches the target voltage level, the ring oscillator stops generating the clock signal according to the adjustment signal, and when the voltage value of the output voltage decreases, the load state detection unit adjusts according to the adjustment. The signal indicates the point in time at which the first control signal is enabled early.

In an embodiment of the present invention, the control circuit of the charge pump circuit further includes a voltage level detector coupled to the output of the ring oscillator and the charge pump circuit to detect the voltage drop of the output voltage. To generate an adjustment signal.

In an embodiment of the invention, the load state detecting unit includes a bias voltage generating unit and a delay unit. The bias voltage generating unit is coupled to the voltage level detector and the output of the charge pump circuit, and generates a bias voltage according to the output voltage. The delay unit is coupled to the bias voltage generating unit and delays the time point at which the first control signal is enabled according to the bias voltage.

Based on the above, the present invention adjusts the enabling time point of the first control signal by adjusting the pulse width variation of the signal and the voltage drop of the output voltage, so that the voltage pump circuit can change its operating frequency according to the state of the load, so as to balance the voltage. The efficiency and drive capability of the pump circuit.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a block diagram of a charge pump circuit and a control circuit thereof according to an embodiment of the invention. Referring to FIG. 2, the control circuit 200 includes a voltage level detector 202, a load state detecting unit 204, and a ring oscillator 206. The voltage level detector 202 is coupled to the load state detecting unit 204, the ring oscillator 206, and the output of the charge pump circuit 208. The ring oscillator 206 is coupled to the load state detecting unit 204 and the charge pump circuit 208.

The voltage level detector 202 is configured to detect a voltage drop change of the output voltage Vout at the output of the charge pump circuit 208, and output an adjustment signal LMT according to the voltage drop of the output voltage Vout. The load state detecting unit 204 is configured to generate the first control signal CON1, and determine a time point at which the first control signal CON1 is enabled according to the output voltage Vout and the adjustment signal LMT. The ring oscillator 206 adjusts the frequency of the clock signal P2 generated by the ring oscillator 206 according to the first control signal CON1. In addition, the charge pump circuit 208 doubles the basic voltage according to the clock signal P2 and generates an output voltage Vout at its output terminal.

For example, when the output voltage Vout drops due to the light load current, and the first control signal CON1 is not enabled, the clock signal P2 output by the ring oscillator 206 has a lower frequency, thus causing the charge pump circuit. 208 operates at a lower operating frequency, at which time the charge pump circuit 208 has a higher efficiency, but when the voltage level of the output voltage Vout is suddenly pulled low (ie, when the load current becomes large), the load state detecting unit 204 adjusts the time point at which the first control signal CON1 is enabled according to the magnitude of the voltage value drop of the output voltage Vout and the adjustment signal LMT. When the magnitude of the voltage value of the output voltage Vout decreases, the load state detecting unit 204 enables the first control signal CON1 earlier. When the first control signal CON1 is enabled, the ring oscillator 206 increases the frequency of the clock signal P2 according to the first control signal CON1, so that the charge pump circuit 208 operates at a higher operating frequency. The sub-circuit 208 has a strong driving capability to quickly pull the output voltage Vout of the charge pump circuit 208 back to the normal voltage level.

The control circuit 200 of the present embodiment can adjust the operating frequency of the charge pump circuit 208 according to the magnitude of the voltage value drop of the output voltage Vout and the adjustment signal LMT, while taking into account the efficiency and driving capability of the charge pump circuit 208, avoiding It is known to use a fixed voltage level to determine the frequency conversion of the ring oscillator 206, while not being able to simultaneously account for the efficiency and drive capability of the charge pump circuit 208. Even when the load current continues to occur and Vout falls to the vicinity of the frequency conversion point, it can be avoided that the charge pump circuit 208 cannot obtain the clock signal P2 required to increase the output voltage due to the continuous switching of the clock signal P2, so that the output voltage Vout decline.

3 is a block diagram of a charge pump circuit and a control circuit thereof according to another embodiment of the present invention. Referring to FIG. 3, in the embodiment, the load state detecting unit 204 of the embodiment of FIG. 2 may include a bias voltage generating unit 302 and a delay unit 304, wherein the bias voltage generating unit 302 is coupled to the voltage level detector. 202, delay unit 304 and the output of charge pump circuit 208. The bias voltage generating unit 302 is configured to detect a voltage drop of the output voltage Vout of the charge pump circuit 208, and output a bias voltage Vb according to the voltage drop of the output voltage Vout, and the delay unit 304 generates the first control signal CON1, and The time point at which the first control signal CON1 is enabled is delayed according to the adjustment signal LMT and the bias voltage Vb. When the magnitude of the voltage value drop of the output voltage Vout is larger, the bias voltage Vb output by the bias voltage generating unit 302 is larger, and the delay time of the delay unit 304 delaying the enable of the first control signal CON1 is also shorter. That is to say, when the magnitude of the voltage value of the output voltage Vout decreases, the first control signal CON1 is enabled to increase the frequency of the clock signal P2, thereby pulling back the output voltage Vout of the charge pump circuit 208. Normal voltage level.

In detail, the load state detecting unit 204 and the ring oscillator 206 in FIG. 3 can be as shown in FIG. 4. 4 is a circuit diagram of a load state detector and a ring oscillator according to an embodiment of the invention. Referring to FIG. 4, the bias voltage generating unit 302 includes transistors Q1 to Q5 and resistors R1 and R2. The first source/drain of the transistor Q1 is coupled to the output voltage Vout, the gate of the transistor Q1 is coupled to the adjustment signal LMT, and the resistors R1 and R2 are connected in series to the second source/drain of the transistor Q1 and the ground GND. between. The gate of the transistor Q2 is coupled to the first source/drain, respectively, to the adjustment signal LMT and the power supply voltage VDD, and the second source/drain of the transistor Q2 is coupled to the first source/drain of the transistors Q3 and Q4. The gate of the transistor Q3 is coupled to the common junction of the resistors R1 and R2, the first source/drain of the transistor Q4 is coupled to the second source/drain of the transistor Q2, and the gate of the transistor Q4 is coupled. A second source/drain of transistor Q4, and a second source/drain of transistor Q4 is coupled to a second source/drain of transistor Q3. The transistor Q5 is coupled between the second source/drain of the transistor Q4 and the ground GND, and the gate of the transistor Q5 is coupled to the first source/drain of the transistor Q5 and the delay unit 304.

The delay unit 304 includes a plurality of buffers A1 connected in series, a plurality of buffer capacitors C1, and a plurality of transistors Q6. The input ends of the plurality of buffers A1 connected in series (that is, the input ends of the buffer strings formed by the plurality of buffers A1) are coupled to the adjustment signal LMT, and the outputs of the plurality of buffers A1 connected in series ( That is, the output of the buffer string formed by the plurality of buffers A1 is coupled to the ring oscillator 206. The plurality of snubber capacitors C1 are respectively coupled between the output end of the corresponding buffer A1 and the ground GND. In addition, the transistor Q6 is coupled between the corresponding buffer A1 and the ground GND, wherein the gate of the transistor Q6 is coupled to the bias voltage generating unit 302.

In addition, the ring oscillator 206 includes a plurality of buffers A2 and a plurality of current sources Is. The input ends of the plurality of buffers A2 connected in series (that is, the input ends of the buffer strings formed by the plurality of buffers A2) are coupled to their own outputs (ie, a plurality of buffers A2 are formed). The current source Is is coupled between the corresponding buffer A2 and the ground GND, and the current magnitude of each current source Is is controlled by the first control signal CON1 and the second control signal CON2 . In this embodiment, each current source Is may include a transistor Q9~Q12, wherein the transistor Q11 and the transistor Q12 are connected in series between the buffer A2 and the ground GND, and the transistor Q9 and the transistor Q10 are also connected in series. The gates of the transistors Q11 and Q9 are coupled to the adjustment signal LMT, and the gates of the transistors Q12 and Q10 are respectively coupled to the first control signal CON1 and the second control signal CON2. Before the first control signal CON1 is enabled, the second control signal CON2 controls the clock signal P2 generated by the ring oscillator 206 to be maintained at a basic frequency, which is smaller than the time after the first control signal CON1 is enabled. The frequency of the signal P2.

5A-5C are schematic diagrams showing waveforms of an adjustment signal, a control signal, and a clock signal according to an embodiment of the invention. 5A is a waveform diagram when the charge pump circuit has a large load current, FIG. 5B is a waveform diagram when the charge pump circuit has a small load current, and FIG. 5C is a diagram when the charge pump circuit has a micro load current. The waveform diagram, that is, the falling amplitude of the output voltage of the charge pump circuit corresponding to FIGS. 5A to 5C is sequentially large to small.

Referring to FIG. 3, FIG. 4 and FIG. 5A, when the output voltage Vout of the charge pump circuit 208 is decreased by a voltage value, the reference voltage Vc at the common contact of the resistors R1 and R2 in the bias voltage generating unit 302 is also caused. That is, the gate voltage of the transistor Q3 is lowered, so that the current of the transistor Q3 becomes large, and the bias current Ib flowing to the transistor Q5 becomes large (and the bias voltage Vb of the gate of the transistor Q5 also rises). Under the influence of the rise of the bias voltage Vb of the gate of the transistor Q5, the current flowing through the transistor Q6 in the delay unit 304 will also become larger, and the charging and discharging rate of the snubber capacitor C1 is increased, so that the first control signal CON1 is at the output voltage Vout. The drop is enabled after a period of time T1. The transistor Q12 in the ring oscillator 206 turns on its channel as the first control signal CON1 is enabled, and the current of the current source Is is thus increased to the current I1 flowing through the transistor Q12 plus the current I2 flowing through the transistor Q10. . The current of the current source Is is the current I2 flowing through the transistor Q10 during the time T1, and the current value is controlled by the voltage level of the second control signal CON2. The increase in current of the current source Is will increase the frequency of the clock signal P2 output by the ring oscillator 206, thereby providing a larger drive current to quickly pull the output voltage Vout of the charge pump circuit 208 back to the normal voltage level. .

Referring to FIG. 3, FIG. 4 and FIG. 5B, since the charge pump circuit 208 of the embodiment has a smaller load current than the embodiment of FIG. 5A, the reference voltage Vc decreases at the common contact of the resistors R1 and R2. The voltage value will be smaller than the reference voltage Vc of the embodiment of FIG. 5A, and the bias current Ib is also smaller than the bias current Ib of the embodiment of FIG. 5A (ie, the voltage value of the bias voltage Vb is increased by a small amount), The charge and discharge rate of the snubber capacitor C1 is slower than the charge and discharge rate when the charge pump circuit 208 has a large load current. In this way, the time point when the first control signal CON1 is enabled will be later than the time point of the embodiment of FIG. 5A (that is, the time T2 will be greater than the time T1), and the ring oscillator 206 raises the time point of the clock signal P2. Late.

In addition, referring to FIG. 3, FIG. 4 and FIG. 5C, this embodiment assumes that the charge pump circuit 208 has only a small load current. Since the pulse width of the adjustment signal LMT becomes narrower as the voltage value of the output voltage Vout becomes smaller, when the pulse width of the adjustment signal LMT is too narrow, the adjustment signal LMT is filtered by the delay unit 304, thereby making the embodiment The first control signal CON1 will not be enabled. At this time, the current of the current source Is is the current I2 controlled by the second control signal CON2, and the ring oscillator 206 generates the clock signal P2 of the fundamental frequency according to the current I2, so that the output voltage Vout of the charge pump circuit 208 returns to the normal state. Voltage level. When the output voltage Vout of the charge pump circuit 208 reaches the target voltage level (ie, returns to the normal voltage level), the adjustment signal LMT will be changed from the high voltage level to the low voltage level, and the transistors Q11 and Q9 will be The channel is turned off, thereby causing the ring oscillator 206 to stop outputting the clock signal P2 to maintain the output voltage Vout at the target voltage level.

As described above, the activation time point of the first control signal CON1 is adjusted by adjusting the pulse width variation of the signal LMT and the voltage drop of the output voltage Vout. When the load current is large, the first control signal CON1 is enabled early. When the load current is small, the first control signal CON1 is delayed, so that the time point of changing the operating frequency of the voltage pump circuit 208 can be adjusted according to the state of the load, so as to balance the efficiency and driving capability of the voltage pump circuit 208. .

FIG. 6 is a schematic diagram of waveforms of output voltage, load current, adjustment signal, and control signal according to an embodiment of the invention. It can be seen from FIG. 6 that, compared with the prior art, when the output voltage Vout is lower than the normal voltage level, the control signal CON1 does not continuously switch its voltage due to the change of the load current I-load. The timing signal, therefore, the clock signal P2 output by the ring oscillator 206 does not continuously switch the frequency as in the prior art to reduce the efficiency of the voltage pump circuit. When the output voltage Vout returns to the normal voltage level, the voltage level of the adjustment signal LMT and the first control signal CON1 and the second control signal CON2 is changed from the high voltage level to the low voltage level. When the output voltage Vout drops slightly from the normal voltage level by a voltage value, the adjustment signal LMT and the second control signal CON2 will be converted to a high voltage level to pull the output voltage Vout back to the normal voltage level.

It should be noted that the buffers A1 and A2 in the embodiment of FIG. 4 may also be an inverter or a transistor. For example, FIG. 7 is a circuit diagram of a load state detector and a ring oscillator according to another embodiment of the present invention. As shown in Figure 7, buffers A1 and A2 can be implemented with transistors Q7 and Q8, respectively. Wherein, the gate of the transistor Q7 is the input end of the buffer A1, the second source/drain of the transistor Q7 is the output end of the buffer A1, and the first source/drain of the transistor Q7 is coupled. To the power supply voltage VDD. In addition, the gate of the transistor Q8 is at the input end of the buffer A2, the second source of the transistor Q8 is the output terminal of the buffer A2, and the first source/drain of the transistor Q8 is coupled to the power supply voltage VDD. . The operation of the load state detector and the ring oscillator of this embodiment is similar to the load state detector of FIG. 4 and the ring oscillator, and therefore will not be described herein.

FIG. 8 is a circuit diagram of a load state detector and a ring oscillator according to another embodiment of the present invention. This embodiment differs from the embodiment of FIG. 4 in that the current source Is can be increased by a string formed by the transistors Q13, Q14. The transistors Q13 and Q14 are connected in series between the buffer A2 and the ground GND, the gate of the transistor Q13 is coupled to the adjustment signal LMT, and the gate of the transistor Q14 is coupled to the output of one of the plurality of buffers A1. (eg the output of the first buffer A1 in the buffer string). Since the transistors Q12 and Q14 are coupled to the output terminals of the different buffers A1, the channels of the transistors Q12 and Q14 are opened for different times, so that the clock signal P2 generated by the ring oscillator 206 can be various. Different frequency variations allow the charge pump circuit 208 to have better efficiency and drive capability depending on the load current. The operation of the circuit of this embodiment is similar to the circuit of the embodiment of FIG. 4, and therefore will not be described herein.

In summary, the present invention adjusts the enabling time point of the first control signal CON1 by adjusting the pulse width variation of the signal and the voltage drop of the output voltage. When the load current is large, the first control signal CON1 is enabled early, and when the load current is small, the first control signal CON1 is delayed, so that the voltage pump circuit 208 can control the first control signal according to the state of the load. The time point is enabled to change its operating frequency to account for the efficiency and drive capability of the voltage pump circuit 208.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ control circuit

102, 202‧‧‧Voltage level detector

104, 206‧‧‧ ring oscillator

106, 208‧‧‧ Charge pump circuit

204‧‧‧Load state detection unit

302‧‧‧Bias voltage generating unit

304‧‧‧Delay unit

Is‧‧‧current source

C1‧‧‧ snubber capacitor

Vc‧‧‧reference voltage

Ib‧‧‧ bias current

I-load‧‧‧ load current

Q1~Q14‧‧‧O crystal

VDD‧‧‧Power supply voltage

GND‧‧‧ Grounding

R1, R2‧‧‧ resistance

A1, A2‧‧‧ buffer

Vb‧‧‧ bias voltage

S1‧‧‧ trigger signal

LMT‧‧‧ adjustment signal

CON1‧‧‧ first control signal

CON2‧‧‧second control signal

Vout‧‧‧ output voltage

P1, P2‧‧‧ clock signal

T1, T2‧‧‧ time

1 is a block diagram of a conventional charge pump circuit and its control circuit.

2 is a block diagram of a charge pump circuit and a control circuit thereof according to an embodiment of the invention.

3 is a block diagram of a charge pump circuit and a control circuit thereof according to another embodiment of the present invention.

4 is a circuit diagram of a load state detector and a ring oscillator according to an embodiment of the invention.

5A-5C are schematic diagrams showing waveforms of an adjustment signal, a control signal, and a clock signal according to an embodiment of the invention.

FIG. 6 is a schematic diagram showing waveforms of output voltage, load current, adjustment signal, and control signal according to an embodiment of the invention.

FIG. 7 is a circuit diagram of a load state detector and a ring oscillator according to another embodiment of the present invention.

FIG. 8 is a circuit diagram of a load state detector and a ring oscillator according to another embodiment of the present invention.

200. . . Control circuit

202. . . Voltage level detector

204. . . Load status detection unit

206. . . Ring oscillator

208. . . Charge pump circuit

LMT. . . Adjustment signal

CON1. . . First control signal

Vout. . . The output voltage

P2. . . Clock signal

Claims (10)

A control circuit for a charge pump circuit includes: a ring oscillator coupled to the charge pump circuit to generate a clock signal, adjusting a frequency of the clock signal according to a first control signal, and stopping generation according to an adjustment signal The clock signal is coupled to the ring oscillator, and directly receives an output voltage of the charge pump circuit and the adjustment signal to generate the first control signal, and according to the received charge The voltage drop of the output voltage of the circuit and the adjustment signal determine a time point at which the first control signal is enabled, wherein a pulse width of the adjustment signal becomes smaller as the voltage value of the output voltage decreases. The control circuit of claim 1, wherein when the output voltage reaches a target voltage level, the ring oscillator stops generating the clock signal according to the adjustment signal, and when the voltage value of the output voltage decreases When the size is increased, the load state detecting unit preliminarily enables the time point of the first control signal according to the adjustment signal. The control circuit of claim 2, further comprising: a voltage level detector coupled to the load state detecting unit, the ring oscillator and the output of the charge pump circuit, detecting the The voltage drop of the output voltage is used to generate the adjustment signal. The control circuit of claim 3, wherein the load state detecting unit comprises: a bias voltage generating unit coupled to the voltage level detector and an output of the charge pump circuit, according to the Output voltage produces a bias voltage And a delay unit coupled to the bias voltage generating unit to generate the first control signal and delay a time point at which the first control signal is enabled according to the bias voltage. The control circuit of claim 4, wherein the bias voltage generating unit comprises: a first transistor, a first source/drain is coupled to the output voltage, and a gate is coupled to the adjustment signal; a first resistor: a second resistor connected in series with the second source/drain of the first transistor and a ground: a second transistor, the first source/drain coupling Connected to a power supply voltage, the gate of the second transistor is coupled to the adjustment signal; a third transistor, the first source/drain is coupled to the second source/drain of the second transistor, the third a gate of the transistor is coupled to the common junction of the first resistor and the second resistor; a fourth transistor having a first source/drain coupled to the second source/drain of the second transistor, The second source/drain of the fourth transistor is coupled to the gate of the fourth transistor and the second source/drain of the third transistor; a fifth transistor coupled to the fourth transistor The second source/drain is coupled to the ground, and the gate of the fifth transistor is coupled to the first source/drain of the fifth transistor and the delay unit. The control circuit of claim 4, wherein the delay unit comprises: a plurality of first buffers connected in series, the input ends of the first buffers connected in series are coupled to the adjustment signal, and the output ends of the first buffers connected in series are coupled to the ring oscillator; The capacitors are respectively coupled between the output end of the corresponding first buffer and the ground; and a plurality of sixth transistors are respectively coupled between the corresponding first buffer and the ground, and the sixth electric The gate of the crystal is coupled to the bias voltage generating unit. The control circuit of claim 6, wherein each of the first buffers is a seventh transistor, and the input end and the output end of each of the first buffers are respectively a gate of the seventh transistor The second source/drain, the first source/drain of the seventh transistor is coupled to a power supply voltage. The control circuit of claim 1, wherein the ring oscillator comprises: a plurality of second buffers connected in series, and the input ends of the second buffers connected in series are coupled to the series connected An output of the second buffer; and a plurality of current sources respectively coupled between the corresponding second buffer and a ground, wherein the current of each of the current sources is controlled by the first control signal and a second control Signal. The control circuit of claim 8, wherein each of the second buffers is an eighth transistor, and the input end and the output end of each of the second buffers are respectively a gate of the eighth transistor The second source/drain, the first source/drain of the eighth transistor is coupled to a power supply voltage. Such as the control circuit described in claim 8 of the patent scope, wherein each The current source includes: a ninth transistor having a gate coupled to the adjustment signal; a tenth transistor coupled in series with the ninth transistor between the corresponding second buffer and the ground, the tenth a gate of the transistor is coupled to the second control signal; an eleventh transistor having a gate coupled to the adjustment signal; and a twelfth transistor connected in series with the eleventh transistor The gate of the twelfth transistor is coupled to the first control signal between the second buffer and the ground.