CN105120561B - A kind of adjusting control circuit and its method - Google Patents
A kind of adjusting control circuit and its method Download PDFInfo
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- CN105120561B CN105120561B CN201510542840.5A CN201510542840A CN105120561B CN 105120561 B CN105120561 B CN 105120561B CN 201510542840 A CN201510542840 A CN 201510542840A CN 105120561 B CN105120561 B CN 105120561B
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Abstract
The present invention relates to a kind of adjusting control circuit and its method, a kind of adjusting control circuit, the circuit includes：Late release module (002), after delay scheduled time, the clamper module (003) is thoroughly closed；Clamper module (003), for by the node voltage clamper in the main amplifier module (001) in predetermined magnitude of voltage；Main amplifier module (001), for being charged to the work loop module (006)；Loop module (004) is maintained, for maintaining the normal work of the main amplifier module (001)；Circuit module (005) is closed, for completing LED output currents from normally to the process of closing；Work loop module (006), for completing LED output currents from zero to normal process.The present invention can ensure that the rising of LED output currents, fall time are all smaller, improve whole PWM dimming resolutions, and ensure that LED output currents do not have larger overshoot, improve the service life of LED lamp bead.
Description
Technical field
The present invention relates to LED backlight drive circuit design field, more particularly to a kind of adjusting control circuit and its method
Background technology
LED backlight, refer to the illumination for LCD Panel, because it has low in energy consumption, adjust than high, response is rapid
It hurry up, the features such as long lifespan, gradually substituting traditional CCFL (cold-cathode tube) backlight.LED drive circuit can exactly ensure
LED constant current exports, and the control circuit of high light modulation ratio etc..The domestic market of such product is substantially shared by external product at present
Neck, therefore the drive control circuit is studied and designed to realizing the production domesticization of such product, promoting the development of industry has reality
Meaning.
With the development of electronic product, it is desirable to which the dimming scope of electronic display screen is more and more wider, light modulation mentioned here
Refer to PWM (numeral) light modulations, as shown in Figure 1 is PWM dimming sequence figures, the square-wave signal that PWM is an externally input, LED output currents
Waveform.In PWM brightness adjustment controls, time quantum TR then represents output current as the time needed for 0 converting into target electric current, time quantum
TF represents output current and time needed for 0 is converted back from target current.At most of conditions, light modulating frequency is lower, contrast
Degree is just higher, because these fixed delays can only take least a portion of dimming cycle.But light modulating frequency is too low and meeting can
Audio-frequency noise can be caused, influence the application of electronic product, so general light modulating frequency can be more than 20KHz in normal use, that
High light modulation ratio is carried, TR, TF time can only be reduced as far as possible.The requirement of minimum contrast is then depended on as the upper limit, it is right
The inverse for being expressed as minimum ON time more general than degree.
Traditional PWM dimming driving circuits are illustrated in figure 2, depict two kinds of traditional PWM brightness adjustment controls modes in fig. 2.
Example 1, pwm signal directly controls amplifier AMP working condition, when PWM is " height ", AMP normal works, by amplifier to adjustment
Pipe N1 gate charges so that whole loop is set up, and when AMP " just " " negative " input voltage is equal, adjustment pipe N1 reaches just
Normal setting electric current, and LED strip and the N1 series connection of adjustment pipe, so LED also reaches the electric current of requirement；When PWM is " low ", AMP
Do not work, AMP outputs pull down to " " current potential, so as to close adjustment pipe N1.Because AMP driving force is limited, so output
TR the and TF times of electric current are all longer.And example 2, discharge and recharge is carried out to exchange homogeneous tube grid by controlling switch S1, S2, it is this
Form TR, the TF time can accomplish very little, but AMP has been detached outside whole acceleration loop, can cause LED output currents
There is larger overshoot, easily cause LED damage.So the backlight drive class product of the in the market country is dimmed than all smaller.
The content of the invention
The purpose of the present invention is to be directed to deficiencies of the prior art, there is provided a kind of adjusting control circuit and its side
Method.The present invention needs to design PWM (numeral) light modulations with quick response, can allow LED output currents from zero to normal, and
There is the faster response time from normal current to zero, and can make PWM that there is larger light modulation ratio, and LED can be ensured
Output current overshoot electric current is smaller.
To achieve these goals, first aspect present invention provides a kind of adjusting control circuit, and the circuit includes：Delay is closed
Mold closing block 002, after delay scheduled time, the clamper module 003 is thoroughly closed；Clamper module 003, for by described in
Node voltage clamper in main amplifier module 001 is on predetermined magnitude of voltage；Main amplifier module 001, for the building ring
Road module 006 charges；Loop module 004 is maintained, for maintaining the normal work of the main amplifier module 001；Close circuit mould
Block 005, for completing LED output currents from normally to the process of closing；Work loop module 006, for completing that LED is defeated
Go out electric current from zero to normal process.
Preferably, the main amplifier module 001 respectively with the work loop module 006 and the maintenance loop module
004 respectively constitutes feedback control loop.
Preferably, the maintenance loop module 004 includes the second N-type metal-oxide-semiconductor N2,3rd resistor R3 and the first control is opened
Close S1；Wherein, the second N-type metal-oxide-semiconductor N2 drain electrode connection external input voltage source VN1, its grid connect the main amplifier module
001 output end, its source electrode connection 3rd resistor R3 one end and the first controlling switch S1 one end；3rd resistor R3's is another
One end is grounded GND；The first controlling switch S1 other ends are connected with the negative input end of main amplifier module 001.
Preferably, the closing circuit module 005 includes the 3rd controlling switch S3, the 4th controlling switch S4 and the 4th electricity
Hinder R4；Wherein, the 4th controlling switch S4 one end is connected with the output end of main amplifier module 001, and the other end is opened with the 3rd control
The one end for closing S3 is connected；The 3rd controlling switch S3 other end is connected with the 4th resistance R4 one end；4th resistance R4's is another
End ground connection GND.
Preferably, the work loop module 006 includes the first N-type metal-oxide-semiconductor N1, second resistance R2 and the second control is opened
Close S2；Wherein, the first N-type metal-oxide-semiconductor N1 drain electrode is connected with LED strip, realizes the first N-type metal-oxide-semiconductor N1 and LED series connection, its grid
Pole is connected with closing the 3rd controlling switch S3 and the 4th controlling switch S4 tie points in circuit module 005, its source electrode and second
Resistance R2 one end and the second controlling switch S2 one end are connected；The second controlling switch S2 other end and main amplifier module
001 negative input end is connected；Second resistance R2 other end ground connection GND.
Preferably, the main amplifier module 001, main amplifier are two foldings cascade amplifier, its frequency compensation form
To be miller-compensated, the grid of the input pipe of its second level amplifier connects the output end of the clamper module 003.
Preferably, the late release module 002 include the first phase inverter 021, the second phase inverter 022, NAND gate 023,
First d type flip flop 024 and the second d type flip flop 025；Wherein, PWM input signals are connected with the input of the first phase inverter 021,
The output end of first phase inverter 021 is connected with the input of the second phase inverter 022；The output end of second phase inverter 022 and the first D
The data input D ends of trigger 024 and one end of NAND gate 023 are connected；Clock input CLK and the first d type flip flop 024 and
The CLK ends of second d type flip flop 025 are connected；EN is the other end of the enabled input connection NAND gate 023 of chip, and NAND gate 023 exports
End is connected with the reset RSET ends of the first d type flip flop 024 and the second d type flip flop 025；The Q ends of first d type flip flop 024 and the
The input D ends of 2-D trigger 025 are connected, and the Q ends output of the second d type flip flop 025 is the output of late release module 002.
Preferably, the clamper module 003 includes the second p-type metal-oxide-semiconductor P2, the 3rd p-type metal-oxide-semiconductor P3 and the 4th p-type MOS
Pipe P4；Wherein, the second p-type metal-oxide-semiconductor P2 source electrode meets input power VDD, and its grid connects the output end of late release module 002,
Defined herein line name SHUT, it, which drains, connects the 3rd p-type metal-oxide-semiconductor P3 source electrode；3rd p-type metal-oxide-semiconductor P3 grid leak connects the 4th p-type
Metal-oxide-semiconductor P4 source electrode；4th p-type metal-oxide-semiconductor P4 grid leaks short circuit together as clamper module output end, defined herein as VPD；Should
The p-type metal-oxide-semiconductor P8 of second level input pipe the 8th of the VPD connections main amplifier module 001 grid.
Second aspect of the present invention provides a kind of method of adjusting control circuit, applied to main amplifier module, late release
Module, clamper module, maintain in the adjusting control circuit that loop module, closing circuit module and work loop module form,
It is characterised in that it includes following steps：The node voltage clamper in the main amplifier modules A MP1 is existed according to input pwm signal
On predetermined magnitude of voltage；According to the node voltage after the clamping action, the main amplifier modules A MP1 gives the work loop
Module charges；After work loop module charging, complete LED output currents from zero to normal process；The LED outputs
When electric current is normal, after predetermined time delay, the clamping action is thoroughly closed；According to input pwm signal, the master is maintained
Amplifier modules A MP1 normal work；While the main amplifier modules A MP1 normal works, complete LED output currents from just
Often accelerate the process closed.
Preferably, according to input pwm signal by the node voltage clamper in the main amplifier modules A MP1 in predetermined electricity
Step includes in pressure value：When input pwm signal is " height ", allow in the main amplifier modules A MP1 of boost phase the second input pipe grid source
Voltage constant, do not influenceed by changes such as input power VDD.
Preferably, the work loop is given according to the node voltage after the clamping action, the main amplifier modules A MP1
Module charge step includes：The second level input pipe gate source voltage of the main amplifier modules A MP1 is dimmed in PWM in transfer process
Grid VPD node voltages control after by clamper.
Preferably, after the work loop charging, ensure that main amplifier positive-negative input end voltage is equal；The LED outputs electricity
When flowing normal, weaken the clamping action to second level input pipe P8 gate node voltages, clamping action is thoroughly closed after delay.
Preferably, according to input pwm signal, maintaining the normal operation Step of the main amplifier modules A MP1 includes：Work as PWM
When LED output currents are closed in light modulation, the normal work of the main amplifier modules A MP1 can be kept, avoids it from deviateing too many work
Make state.
The present invention can ensure LED output currents from zero to it is normal rise and from normally to zero fall time all compared with
It is small, improve whole PWM dimming resolutions；Accelerating circuit is fused in main amplifier control, ensure that LED output currents will not
There is larger overshoot, improve the service life of LED lamp bead.
Brief description of the drawings
In order to become apparent from illustrate the embodiment of the present invention technical scheme, embodiment will be described below needed for use it is attached
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this area
For those of ordinary skill, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is PWM dimming sequence schematic diagrames；
Fig. 2 is the PWM light modulation schematic diagrames of prior art；
Fig. 3 is a kind of adjusting control circuit schematic diagram that the embodiment of the present invention one provides；
Fig. 4 is a kind of adjusting control circuit schematic diagram that the embodiment of the present invention two provides；
Fig. 5 is the main amplifier AMP1 schematic diagrames that the embodiment of the present invention two provides；
Fig. 6 is a kind of switching sequence schematic diagram for adjusting control circuit that the embodiment of the present invention two provides；
Fig. 7 is the late release module diagram that the embodiment of the present invention two provides；
Fig. 8 is the clamper module diagram that the embodiment of the present invention two provides；
Fig. 9 is the PWM late release module time diagrams that the embodiment of the present invention two provides；
Figure 10 is the PWM light modulation workflow schematic diagrams that the embodiment of the present invention two provides；
Figure 11 is a kind of method schematic diagram for adjusting control circuit that the embodiment of the present invention three provides.
Embodiment
Below by drawings and examples, technical scheme is described in further detail.
The present invention can ensure LED output currents from zero to it is normal rise and from normally to zero fall time all compared with
It is small, improve whole PWM dimming resolutions；Accelerating circuit is fused in main amplifier control, ensure that LED output currents will not
There is larger overshoot, improve the service life of LED lamp bead.
Fig. 3 is a kind of adjusting control circuit schematic diagram that the embodiment of the present invention one provides.A kind of brightness adjustment control as shown in Figure 3
Circuit, the circuit include：Main amplifier module 001, late release module 002, clamper module 003, maintenance loop module 004, pass
Closed circuit module 005 and work loop module 006；Wherein, late release module 002, after delay scheduled time, by institute
Clamper module 003 is stated thoroughly to close；Clamper module 003, for by the node voltage clamper in the main amplifier module 001 pre-
On fixed magnitude of voltage；Main amplifier module 001, for being charged to the work loop module 006；Loop module 004 is maintained, is used for
Maintain the normal work of the main amplifier module 001；Close circuit module 005, for complete by LED output currents from normally to
The process of closing；Work loop module 006, for completing LED output currents from zero to normal process.
The present embodiment can ensure LED output currents from zero to it is normal rise and from normally to zero fall time all
It is smaller, improve whole PWM dimming resolutions；Accelerating circuit is fused in main amplifier control, ensure that LED output currents not
Larger overshoot is had, improves the service life of LED lamp bead.
Fig. 4 is a kind of adjusting control circuit schematic diagram that the embodiment of the present invention two provides.As shown in figure 4, the circuit includes
Main amplifier module 001, late release module 002, clamper module 003, loop module 004 is maintained, close circuit module 005, work
Make loop module 006.
Specifically, the preferred scheme as the present embodiment, it is described maintenance loop module 004 include the second N-type metal-oxide-semiconductor N2,
3rd resistor R3 and the first controlling switch S1；Wherein, the second N-type metal-oxide-semiconductor N2 drain electrode connection external input voltage source VN1,
Its grid connects the output end of the main amplifier module 001, and its source electrode connection 3rd resistor R3 one end and the first control are opened
Close S1 one end；3rd resistor R3 other end ground connection GND；The first controlling switch S1 other ends are negative with main amplifier module 001
Input is connected.
Specifically, the preferred scheme as the present embodiment, it is described closing circuit module 005 include the 3rd controlling switch S3,
4th controlling switch S4 and the 4th resistance R4；Wherein, the 4th controlling switch S4 one end and the output end of main amplifier module 001
It is connected, the other end is connected with the 3rd controlling switch S3 one end；The 3rd controlling switch S3 other end and the one of the 4th resistance R4
End is connected；4th resistance R4 other end ground connection GND.
Specifically, the preferred scheme as the present embodiment, the work loop module 006 include the first N-type metal-oxide-semiconductor N1,
Second resistance R2 and the second controlling switch S2；Wherein, the first N-type metal-oxide-semiconductor N1 drain electrode is connected with LED strip, realizes the first N-type
Metal-oxide-semiconductor N1 and LED series connection, its grid is with closing the 3rd controlling switch S3 and the 4th controlling switch S4 in circuit module 005
Tie point is connected, and its source electrode is connected with second resistance R2 one end and the second controlling switch S2 one end；Second controlling switch
The S2 other end is connected with the negative input end of main amplifier module 001；Second resistance R2 other end ground connection GND.
The PWM light modulation course of work：PWM is an externally input the square-wave signal to drive circuit, and PWM is dimmed in accelerating module
Controlling switch S1, S2, S3, S4, switching sequence Fig. 6 visible with PWM relations (a kind of adjusting control circuit switching sequence signal
Figure).When pwm signal is by " low " change " height ", S2, S4 conductings are switched, switch S1, S3 disconnect.The now work loop
Module 006 forms feedback control loop with the main amplifier module 001, at this moment because LED output currents are " zero ", main amplifier module
AMP1 negative terminal input voltage is close to zero, then main amplifier can pull to second level input pipe P8 grid VPD node voltages
" " current potential, but due to the effect of clamper module 003, VPD will not decline too " low ", but meeting clamper is in opposed power
(BIASP1-BIASN2-BIASN1-BIASP2) voltage, such voltage can cause input pipe P8 pipes in the second level to be in resistance
Area, homogeneous tube N1 gate capacitance is exchanged by second level input pipe P8 pipes and charged, due to designed second level input pipe P8 pipes
At resistance area, its equivalent resistance is smaller, adjustment pipe N1 grid voltage can be filled height in the short period of time, when adjustment is managed
N1 gate charges to a certain extent after, adjustment pipe N1 is turned on and electric current is occurred, with adjustment pipe N1 electric currents increase, on resistance R2
There is voltage, main amplifier AMP1 initially enters the work of amplifier area.Because second level input pipe P8 gate source voltages are initially to be clamped
(BIASP1-BIASN2-BIASN1-BIASP2) voltage is arrived in position, and second level input pipe P8 is remote into its gate source voltage of saturation region
Less than the magnitude of voltage, so gradually to weaken clamper module defeated to the second level with the normal work of the main amplifier module 001
Enter the clamping action of pipe P8 gate source voltages so that second level input pipe P8 automatically disengages resistance area, weakens charging pull-up effect, keeps away
It is too high to exempt to exchange homogeneous tube N1 gate charges, causes the larger overshoot of LED output currents.The late release module 002, is pair
Pwm signal rising edge carries out the delay of the scheduled time, and the late release module 002 is by the clamper mould after the scheduled time
Block 003 is thoroughly closed, and avoids the clamper module 003 from causing offset influence to system, so far completes electric current from zero to normal
Accelerator.
When pwm signal is low, controlling switch S2, S4 disconnects, controlling switch S1, S3 closure.By the maintenance loop mould
The loop that block 004 is formed with the main amplifier module 001, maintain the normal work of the main amplifier modules A MP1 so that under
When one pwm signal comes, the main amplifier modules A MP1 being capable of quick response work.The closing of LED output currents, then by
Circuit module 005 is closed to complete.In closing circuit module 005 after controlling switch S3 closures, exchange homogeneous tube N1's by resistance R4
Gate capacitance is discharged, and so as to close adjustment pipe N1, completes LED current from normally to the process of closing.
The course of work of late release module 002：When EN or pwm signal are " low ", the output of NAND gate 023 is " height ", and D is touched
Hair device 024, d type flip flop 025 are in reset state, and the output of Q ends is all " low "；Chip starts normal work after EN is " height ",
After pwm signal is by " low " change " height ", it is " height " that can export the Q ends of d type flip flop 025 by 1 to 2 CLK clock, by the pincers
Position module path blockade, so being capable of 1 to 2 CLK clock cycle of normal work equivalent to the clamper module.Its timing variations
It can be seen that Fig. 9 (PWM late release modules time diagram).
Fig. 5 is the main amplifier AMP1 schematic diagrames that the embodiment of the present invention two provides.As shown in figure 5, the main amplifier module 001,
For traditional two foldings cascade amplifier, its frequency compensation form is miller-compensated, and it is mainly characterized by second level amplifier
Input pipe P8 grid connect the output of the clamper module 003, the input pipe P8 of second level amplifier gate line name definition
For VPD.
Fig. 7 is the late release module diagram that the embodiment of the present invention two provides.As shown in fig. 7, the late release module
002 includes the first phase inverter 021, the second phase inverter 022, NAND gate 023, the first d type flip flop 024 and the second d type flip flop
025。
Specifically, the preferred scheme as the present embodiment, the late release module 002 include the first phase inverter 021, the
Two phase inverters 022, NAND gate 023, the first d type flip flop 024 and the second d type flip flop 025；Wherein, PWM input signals and first
The input of phase inverter 021 is connected, and the output end of the first phase inverter 021 is connected with the input of the second phase inverter 022；Second is anti-
The output end of phase device 022 is connected with the data input D ends of the first d type flip flop 024 and one end of NAND gate 023；Clock inputs
CLK is connected with the CLK ends of the first d type flip flop 024 and the second d type flip flop 025；EN is the enabled input connection NAND gate of chip
023 other end, the output end of NAND gate 023 and the reset RSET ends phase of the first d type flip flop 024 and the second d type flip flop 025
Even；The Q ends of first d type flip flop 024 are connected with the input D ends of the second d type flip flop 025, and the Q ends output of the second d type flip flop 025 is
The output of late release module 002.
Fig. 8 is the clamper module diagram that the embodiment of the present invention two provides.The as shown in Figure 8 clamper module 003 includes the
Two p-type metal-oxide-semiconductor P2, the 3rd p-type metal-oxide-semiconductor P3, the 4th p-type metal-oxide-semiconductor P4.
Specifically, the preferred scheme as the present embodiment, the second p-type metal-oxide-semiconductor P2 source electrode meet input power VDD, its grid
Pole connects the output end of late release module 002, and defined herein line name SHUT, it, which drains, connects the 3rd p-type metal-oxide-semiconductor P3 source electrode；The
Three p-type metal-oxide-semiconductor P3 grid leak connects the 4th p-type metal-oxide-semiconductor P4 source electrode；4th p-type metal-oxide-semiconductor P4 grid leak short circuits are together as clamper
The output end of module, defined herein as VPD；The p-type MOS of second level input pipe the 8th of the VPD connections main amplifier module 001
Pipe P8 grid.
Figure 10 is the PWM light modulation workflow schematic diagrams that the embodiment of the present invention two provides.The tool of PWM light modulations as described in Figure 10
Body comprises the following steps：
Step S101, when pwm signal is by " low " change " height ", switch S2, S4 conducting, switch S1, S3 disconnect；Now work
Make loop module 006 and main amplifier module 001 and form feedback control loop, at this moment because LED output currents are " zero ", main amplifier AMP1
Negative terminal input voltage close to zero, then main amplifier can pull to the input pipe P8 of second level amplifier grid VPD node voltages
" " current potential；
Step S102, due to the effect of clamper module 003, VPD will not decline too " low ", but meeting clamper is in opposed power
(BIASP1-BIASN2-BIASN1-BIASP2) voltage, such voltage can cause at the input pipe P8 pipes of second level amplifier
In resistance area, homogeneous tube N1 gate capacitance is exchanged by the input pipe P8 pipes of second level amplifier and charged；
Step S103, because the input pipe P8 pipes of designed second level amplifier are at resistance area, its equivalent resistance compared with
It is small, adjustment pipe N1 grid voltage can be filled height in the short period of time, after pipe N1 gate charges are adjusted to a certain extent,
Adjustment pipe N1 is turned on and electric current is occurred, with adjustment pipe N1 electric currents increase, voltage occurs on resistance R2, main amplifier AMP1 starts
Worked into amplifier area；
Step S104, because the input pipe P8 grid voltages of second level amplifier are initially clamped to (BIASP1-BIASN2-
BIASN1-BIASP2) voltage, and after the input pipe P8 of second level amplifier enters saturation region, its grid voltage is much smaller than the voltage
Value, so as the normal work of main amplifier module 001 can gradually weaken input pipe P8 grid of the clamper module to second level amplifier
The clamping action of pole tension so that the input pipe P8 of second level amplifier automatically disengages resistance area, weakens charging pull-up effect, avoids
It is too high to exchange homogeneous tube N1 gate charges, causes the larger overshoot of LED output currents；
Step S105, late release module, be to pwm signal rising edge carry out certain time delay, by setting when
Between after late release module 002 clamper module 003 is thoroughly closed, avoid clamper module 003 from causing offset influence to system, extremely
This completes electric current from zero to normal accelerator；
Specifically, when EN or pwm signal are " low ", the output of NAND gate 023 is " height ", d type flip flop 024, d type flip flop
025 is in reset state, and the output of Q ends is all " low ", and chip starts normal work after EN is " height ", and pwm signal is become by " low "
After " height ", it is " height " that can export the Q ends of d type flip flop 025 by 1 to 2 CLK clock, by clamper module path blockade, so
Being capable of 1 to 2 CLK clock cycle of normal work equivalent to clamper module；
Specifically, it is uncertain in " height " or " low " when pwm signal input delay closing unit, works as pwm signal
When being input to late release and being in " height ", it is " height " that can export the Q ends of d type flip flop 025 by 1 to 2 CLK clock, also
It is that the SHUT defined is in " height " position, by clamper module path blockade, the PWM that such as Fig. 9 embodiment of the present invention two provides postpones to close
Shown in mold closing block time diagram；
Step S106, after pwm signal is by " height " change " low ", controlling switch S2, S4 disconnects, S1, S3 closure；
Step S107, the loop being made up of maintenance loop module 004 and main amplifier module 001, maintains main amplifier AMP1
Normal work so that when next pwm signal comes, AMP1 can quick response work.The closing of LED output currents,
Then completed by closing circuit module 005；
Step S108, close in circuit module 005 after controlling switch S3 closures, homogeneous tube N1 grid electricity is exchanged by resistance R4
Appearance is discharged；
Step S109, resistance R4 one section of ground connection, the time by resistance R4 electric discharge is shorter, so as to close adjustment pipe
N1, LED current is completed from normally to the process of closing.
Therefore, the present embodiment can ensure LED output currents from zero to it is normal rise and from normally to zero decline
Time is all smaller, improves whole PWM dimming resolutions；Accelerating circuit is fused in main amplifier control, ensure that LED is exported
Electric current does not have larger overshoot, improves the service life of LED lamp bead.
Figure 11 is a kind of method schematic diagram for adjusting control circuit that the embodiment of the present invention three provides.As shown in figure 11, adjust
The method of light control circuit includes step S111-S116：
In step S111, the node voltage clamper in the main amplifier modules A MP1 is being made a reservation for according to input pwm signal
Magnitude of voltage on；
In step S112, according to the node voltage after the clamping action, the main amplifier modules A MP1 gives the work
Loop module charges；
In step S113, after the work loop module charging, complete LED output currents from zero to normal process；
It is after predetermined time delay, the clamping action is thorough when the LED output currents are normal in step S114
Close；
In step S115, according to pwm signal is inputted, the normal work of the main amplifier modules A MP1 is maintained；
While step S116, the main amplifier modules A MP1 normal works, complete to add LED output currents from normal
The process that speed is closed.
Preferably as a kind of possible implementation of this example, it is described according to input pwm signal by the main amplifier mould
Node voltage clamper in the block AMP1 step on predetermined magnitude of voltage includes：When input pwm signal is " height ", allows and accelerating rank
The main amplifier modules A MP1 of section the second input pipe gate source voltage is constant, is not influenceed by changes such as input power VDD.
Preferably as a kind of possible implementation of this example, the node voltage according to after the clamping action,
The main amplifier modules A MP1 includes to the work loop module charge step：The second level of the main amplifier modules A MP1 is defeated
Enter grid VPD node voltage control of the pipe gate source voltage in PWM dims transfer process after by clamper.
Preferably as a kind of possible implementation of this example, after the work loop charging, ensure that main amplifier is positive and negative
Input terminal voltage is equal；When the LED output currents are normal, weaken the clamper work to second level input pipe P8 gate node voltages
With thorough closing clamping action after delay.
It is described according to input pwm signal preferably as a kind of possible implementation of this example, maintain the main fortune
Amplification module AMP1 normal operation Step includes：When PWM, which is dimmed, closes LED output currents, the main amplifier mould can be kept
Block AMP1 normal work, it is avoided to deviate too many working condition.
Therefore, the present embodiment can ensure LED output currents from zero to it is normal rise and from normally to zero decline
Time is all smaller, improves whole PWM dimming resolutions；Accelerating circuit is fused in main amplifier control, ensure that LED is exported
Electric current does not have larger overshoot, improves the service life of LED lamp bead.
Above-described embodiment, the purpose of the present invention, technical scheme and beneficial outcomes are carried out further
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., all should include
Within protection scope of the present invention.
Claims (9)
1. a kind of adjusting control circuit, it is characterised in that the circuit includes:Main amplifier module (001), late release module
(002), clamper module (003), maintenance loop module (004), closing circuit module (005) and work loop module (006)；
Wherein,
Late release module (002), after delay scheduled time, the clamper module (003) is thoroughly closed；Wherein,
The late release module (002) includes：First phase inverter (021), the second phase inverter (022), NAND gate (023),
One d type flip flop (024) and the second d type flip flop (025)；Wherein, PWM input signals and the input of the first phase inverter (021)
It is connected, the output end of the first phase inverter (021) is connected with the input of the second phase inverter (022)；Second phase inverter (022) it is defeated
Go out end with the data input D ends of the first d type flip flop (024) and one end of NAND gate (023) to be connected；Clock inputs CLK and the
The CLK ends of one d type flip flop (024) and the second d type flip flop (025) are connected；EN is the enabled input connection NAND gate (023) of chip
The other end, the reset RSET ends of NAND gate (023) output end and the first d type flip flop (024) and the second d type flip flop (025)
It is connected；The Q ends of first d type flip flop (024) are connected with the input D ends of the second d type flip flop (025), the Q of the second d type flip flop (025)
End output is the output of late release module (002)；
Clamper module (003), for by the node voltage clamper in the main amplifier module (001) in predetermined magnitude of voltage；
Wherein,
The clamper module (003) includes the second p-type metal-oxide-semiconductor (P2), the 3rd p-type metal-oxide-semiconductor (P3) and the 4th p-type metal-oxide-semiconductor
(P4)；Wherein, the source electrode of the second p-type metal-oxide-semiconductor (P2) connects input power (VDD), and its grid connects the defeated of late release module (002)
Go out end, defined herein line name SHUT, it, which drains, connects the source electrode of the 3rd p-type metal-oxide-semiconductor (P3)；The grid leak of 3rd p-type metal-oxide-semiconductor (P3) connects
Connect the source electrode of the 4th p-type metal-oxide-semiconductor (P4)；4th p-type metal-oxide-semiconductor (P4) grid leak short circuit together as clamper module output end, this
Place is defined as VPD；The grid of the p-type metal-oxide-semiconductor (P8) of second level input pipe the 8th of the VPD connections main amplifier module (001)
Pole, wherein, the 8th p-type metal-oxide-semiconductor (P8) is built in the main amplifier module (001)；
Main amplifier module (001), for being charged to the work loop module (006)；
Loop module (004) is maintained, for maintaining the normal work of the main amplifier module (001)；
Circuit module (005) is closed, for completing LED output currents from normally to the process of closing；
Work loop module (006), for completing LED output currents from zero to normal process.
2. circuit according to claim 1, it is characterised in that the main amplifier module (001) respectively with the building ring
Road module (006) and the maintenance loop module (004) respectively constitute feedback control loop.
3. circuit according to claim 1 or claim 2, it is characterised in that:
The maintenance loop module (004) includes the second N-type metal-oxide-semiconductor (N2), 3rd resistor (R3) and the first controlling switch
(S1)；Wherein,
Drain electrode connection external input voltage source (VN1) of second N-type metal-oxide-semiconductor (N2), its grid connect the main amplifier module
(001) output end, one end of its source electrode connection 3rd resistor (R3) and one end of the first controlling switch (S1)；3rd resistor
(R3) other end ground connection (GND)；First controlling switch (S1) other end is connected with the negative input end of main amplifier module (001)；
The closing circuit module (005) includes the 3rd controlling switch (S3), the 4th controlling switch (S4) and the 4th resistance
(R4)；Wherein,
One end of 4th controlling switch (S4) is connected with the output end of main amplifier module (001), the other end and the 3rd controlling switch
(S3) one end is connected；The other end of 3rd controlling switch (S3) is connected with one end of the 4th resistance (R4)；4th resistance (R4)
The other end ground connection (GND)；
The work loop module (006) includes the first N-type metal-oxide-semiconductor (N1), second resistance (R2) and the second controlling switch
(S2)；Wherein,
The drain electrode of first N-type metal-oxide-semiconductor (N1) is connected with LED strip, realizes the first N-type metal-oxide-semiconductor (N1) and LED series connection, its grid
Be connected with closing the 3rd controlling switch (S3) and the 4th controlling switch (S4) tie point in circuit module (005), its source electrode with
One end of second resistance (R2) and one end of the second controlling switch (S2) are connected；The other end of second controlling switch (S2) and master
The negative input end of amplifier module (001) is connected；The other end ground connection (GND) of second resistance (R2).
4. circuit according to claim 1 or 2, it is characterised in that：
The main amplifier module (001), main amplifier are two foldings cascade amplifier, and its frequency compensation form is mended for Miller
Repay, the grid of the input pipe of its second level amplifier connects the output end of the clamper module (003).
A kind of 5. method of adjusting control circuit, applied to main amplifier module, late release module, clamper module, maintenance loop
Module, close in the adjusting control circuit of circuit module and the loop module composition that works, it is characterised in that including following step
Suddenly：
According to input pwm signal by the node voltage clamper in the main amplifier module (AMP1) on predetermined magnitude of voltage；
According to the node voltage after the clamping action, the main amplifier module (AMP1) is charged to the work loop module；
After work loop module charging, complete LED output currents from zero to normal process；
When the LED output currents are normal, after predetermined time delay, the clamping action is thoroughly closed；
According to input pwm signal, the normal work of the maintenance main amplifier module (AMP1)；
While main amplifier module (AMP1) normal work, the process for closing LED output currents from normal acceleration is completed；
Wherein, the late release module includes：First phase inverter, the second phase inverter, NAND gate, the first d type flip flop and
2-D trigger；Wherein, PWM input signals are connected with the input of the first phase inverter, the output end of the first phase inverter and second anti-
The input of phase device is connected；The output end of second phase inverter and the data input D ends of the first d type flip flop and one end of NAND gate
It is connected；Clock input CLK is connected with the CLK ends of the first d type flip flop and the second d type flip flop；EN is the enabled input connection of chip
The other end of NAND gate, NAND gate output end are connected with the reset RSET ends of the first d type flip flop and the second d type flip flop；First D
The Q ends of trigger are connected with the input D ends of the second d type flip flop, and the Q ends output of the second d type flip flop is the defeated of late release module
Go out；
The clamper module, for by the node voltage clamper in the main amplifier module in predetermined magnitude of voltage；
Wherein, the clamper module includes the second p-type metal-oxide-semiconductor, the 3rd p-type metal-oxide-semiconductor and the 4th p-type metal-oxide-semiconductor；Wherein, the 2nd P
The source electrode of type metal-oxide-semiconductor (P2) connects input power, and its grid connects the output end of late release module, defined herein line name SHUT, its
Drain electrode connects the source electrode of the 3rd p-type metal-oxide-semiconductor；The grid leak of 3rd p-type metal-oxide-semiconductor connects the source electrode of the 4th p-type metal-oxide-semiconductor；4th p-type MOS
Pipe grid leak short circuit together as clamper module output end, defined herein as VPD, the VPD connections main amplifier module
(001) grid of the p-type metal-oxide-semiconductor (P8) of second level input pipe the 8th, wherein, the 8th p-type metal-oxide-semiconductor (P8) is built in described
Main amplifier module (001).
6. according to the method for claim 5, it is characterised in that according to input pwm signal by the main amplifier module
(AMP1) node voltage clamper in the step on predetermined magnitude of voltage includes：
When input pwm signal is " height ", make the second input pipe gate source voltage in the main amplifier module (AMP1) of boost phase constant,
Do not influenceed by changes such as input powers (VDD).
7. according to the method for claim 5, it is characterised in that according to the node voltage after the clamping action, the master
Amplifier module (AMP1) includes to the work loop module charge step：
Grid of the second level input pipe gate source voltage of the main amplifier module (AMP1) in PWM dims transfer process after by clamper
Pole (VPD) node voltage controls.
8. according to the method for claim 5, it is characterised in that after the work loop charging, ensure that main amplifier is positive and negative defeated
It is equal to enter terminal voltage；When the LED output currents are normal, weaken the clamper work to second level input pipe (P8) gate node voltage
With thorough closing clamping action after delay.
9. according to the method for claim 5, it is characterised in that according to input pwm signal, maintain the main amplifier module
(AMP1) normal operation Step includes：
When PWM, which is dimmed, closes LED output currents, the normal work of the main amplifier module (AMP1) can be kept, avoids it
Deviate too many working condition.
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|---|---|---|---|---|
| CN101340755A (en) * | 2008-08-12 | 2009-01-07 | 深圳市联德合微电子有限公司 | High-speed driving circuit of LED capable of overshooting prevention |
| EP2230579A1 (en) * | 2009-03-20 | 2010-09-22 | STMicroelectronics S.r.l. | Fast switching, overshoot-free, current source and method |
| CN102196621A (en) * | 2010-03-19 | 2011-09-21 | 上海贝岭股份有限公司 | LED dimming circuit |
| CN204948436U (en) * | 2015-08-31 | 2016-01-06 | 英特格灵芯片(天津)有限公司 | A kind of adjusting control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103327694B (en) * | 2013-06-26 | 2015-07-22 | 上海晶丰明源半导体有限公司 | Silicon controlled dimming LED drive circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101340755A (en) * | 2008-08-12 | 2009-01-07 | 深圳市联德合微电子有限公司 | High-speed driving circuit of LED capable of overshooting prevention |
| EP2230579A1 (en) * | 2009-03-20 | 2010-09-22 | STMicroelectronics S.r.l. | Fast switching, overshoot-free, current source and method |
| CN102196621A (en) * | 2010-03-19 | 2011-09-21 | 上海贝岭股份有限公司 | LED dimming circuit |
| CN204948436U (en) * | 2015-08-31 | 2016-01-06 | 英特格灵芯片(天津)有限公司 | A kind of adjusting control circuit |
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