TWI401002B - Print circuit board and layout thereof - Google Patents
Print circuit board and layout thereof Download PDFInfo
- Publication number
- TWI401002B TWI401002B TW97114160A TW97114160A TWI401002B TW I401002 B TWI401002 B TW I401002B TW 97114160 A TW97114160 A TW 97114160A TW 97114160 A TW97114160 A TW 97114160A TW I401002 B TWI401002 B TW I401002B
- Authority
- TW
- Taiwan
- Prior art keywords
- vias
- power
- circuit board
- printed circuit
- layers
- Prior art date
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
本發明係關於一種印刷電路板及其佈線方法。The present invention relates to a printed circuit board and a wiring method therefor.
印刷電路板作為一種元件連接平台於電子工業中佔據了絕對統治之地位。隨著電子產品之功能需求不斷提高,印刷電路板亦日益高密度化、高集成化及多層化。多層印刷電路板通常具有多個電源層及地層,流過每個過孔電流係所有與之連接之電源層提供之電流之和。As a component connection platform, printed circuit boards occupy an absolute dominance in the electronics industry. As the functional requirements of electronic products continue to increase, printed circuit boards are becoming increasingly dense, highly integrated, and multi-layered. Multilayer printed circuit boards typically have multiple power and ground layers that flow through the sum of the currents supplied by all of the via current lines connected to the power plane.
由於多層印刷電路板生產工藝之不足,各電源層上之電流往往分佈不均,使得同一電源層對各過孔之電流資獻不均衡。目前,多層印刷電路板大多將每個過孔與所有電源層連接,導致各過孔之電流大小不一,分佈極不均衡。對於多層印刷電路板而言,單個過孔之電流有最高上限值,當電流超過此上限值時,過孔之銅壁將被熔毀,不能正常工作。Due to the insufficiency of the production process of the multilayer printed circuit board, the currents on the power supply layers are often unevenly distributed, so that the current power layer has an unbalanced current contribution to each via. At present, multi-layer printed circuit boards mostly connect each via with all power layers, resulting in different currents and uneven distribution of the vias. For a multilayer printed circuit board, the current of a single via has the highest upper limit. When the current exceeds the upper limit, the copper wall of the via will be melted and will not work properly.
鑒於以上內容,有必要提供一種過孔電流相對均勻之印刷電路板。In view of the above, it is necessary to provide a printed circuit board having a relatively uniform via current.
一種印刷電路板之佈線方法,包括步驟:根據電流小之過孔連接較多電源層及電流大之過孔連接較少電源層之原則,使印刷電路板所有過孔之電流相對均勻,以確定每個過孔連接電源層之數量;根據上述所確定之每個過孔連接之電源層之數量,隔離無需電性連接之過孔與電源層。本發明還涉及一種使用該佈線方法設計得到之印刷電路板,其包括複 數過孔,該等過孔所電性連接之電源層數不同。A wiring method for a printed circuit board, comprising the steps of: connecting a plurality of power supply layers with a small current via and a current supply with a large current via, and making the current of all the vias of the printed circuit board relatively uniform to determine The number of power layers connected to each of the vias; the vias and power planes that do not require electrical connections are isolated according to the number of power planes for each via connection determined above. The present invention also relates to a printed circuit board designed using the wiring method, including The number of vias is different, and the number of power layers electrically connected to the vias is different.
使用該印刷電路板之佈線方法能使印刷電路板所有過孔電流相對均勻分佈,避免流經某些過孔之電流過大,致使印刷電路板局部溫度過高,而導致印刷電路板過孔銅壁被燒壞,從而提高了印刷電路板之穩定性。The wiring method of the printed circuit board can make all the via currents of the printed circuit board relatively evenly distributed, avoiding excessive current flowing through some via holes, causing the local temperature of the printed circuit board to be too high, and causing the printed circuit board to pass through the copper wall. It is burnt out, which improves the stability of the printed circuit board.
請參閱圖1,本發明印刷電路板在對過孔電流進行調整時,首先於仿真軟體中構建印刷電路板100之模型,該印刷電路板100包括16個過孔P1-P16,6個電源層L1-L6。該16個過孔P1-P16均與6個電源層L1-L6相連。Referring to FIG. 1, the printed circuit board of the present invention firstly constructs a model of the printed circuit board 100 in the simulation software when the via current is adjusted. The printed circuit board 100 includes 16 vias P1-P16 and 6 power layers. L1-L6. The 16 via holes P1-P16 are connected to the six power supply layers L1-L6.
然後於仿真軟體中將訊號輸入到該印刷電路板100中,仿真得到流過每個過孔P1-P16之電流值,並將流過每個過孔之電流列表,如圖2,可見該16個過孔P1-P16之電流分佈極不均勻。流過該等過孔P9、P13、P14、P15、P16之電流較大,流過過孔P3、P4、P7之電流較小,其中流過過孔P13之電流最大,為7.942安培,流過過孔P7之電流最小,為0.895安培。Then, the signal is input into the printed circuit board 100 in the simulation software, and the current value flowing through each of the via holes P1 - P16 is simulated, and the current flow through each of the via holes is displayed, as shown in FIG. The current distribution of the vias P1-P16 is extremely uneven. The current flowing through the via holes P9, P13, P14, P15, and P16 is large, and the current flowing through the via holes P3, P4, and P7 is small, and the current flowing through the via hole P13 is the largest, which is 7.942 amps, flowing through The current in via P7 is the smallest, 0.895 amps.
再根據電流小之過孔連接較多電源層及電流大之過孔連接較少電源層之原則,於仿真軟體中不斷調整該16個過孔P1-P16與6個電源層L1-L6之連接關係。當觀察到該16個過孔P1-P16之電流如圖3所示時,該16個過孔P1-P16之電流分佈相對均勻,得到該16個過孔P1-P16與電源層L1-L6之較佳連接數。According to the principle that a small current is connected to a large number of power supply layers and a large current via is connected to a small power supply layer, the connection of the 16 vias P1-P16 and the six power supply layers L1-L6 is continuously adjusted in the simulation software. relationship. When the currents of the 16 vias P1-P16 are observed as shown in FIG. 3, the current distribution of the 16 vias P1-P16 is relatively uniform, and the 16 vias P1-P16 and the power layers L1-L6 are obtained. The number of connections is preferred.
調整後,流過過孔之最大電流由7.942安培下降為3.416安培,最小電流由0.895安培上升為1.227安培。相應地, 該最大電流與最小電流之間之差值由7.047安培降低到2.139安培。由此可見,透過變更過孔與電源層之連結關係,該16個過孔P1-P16之電流能達到一個相對均勻之狀態。需要指出的是,儘管於調整前後過孔P4與6個電源層L1-L6之連接關係沒有改變,但流過該過孔P4之電流由1.040安培上升到1.882安培。這是因為,任何一個過孔與某一電源層之連接關係變化都會改變該電源層之電流分佈狀況,從而改變流過其他過孔之電流值。After adjustment, the maximum current flowing through the via decreased from 7.942 amps to 3.416 amps, and the minimum current increased from 0.895 amps to 1.227 amps. Correspondingly, The difference between the maximum current and the minimum current is reduced from 7.047 amps to 2.139 amps. It can be seen that the current of the 16 vias P1-P16 can reach a relatively uniform state by changing the connection relationship between the via and the power layer. It should be noted that although the connection relationship between the via hole P4 and the six power supply layers L1 - L6 is not changed before and after the adjustment, the current flowing through the via hole P4 is increased from 1.040 amps to 1.882 amps. This is because any change in the connection relationship between any via and a power plane changes the current distribution of the power plane, thereby changing the current flowing through the other vias.
根據仿真軟體得到該16個過孔P1-P16與電源層之較佳連接數後,在印刷電路板實際佈線時,該16個過孔P1-P16與各電源層之連接需要相應之調節。以該過孔P1為例,其與電源層之連接數由6個降為3個,利用反焊盤隔離該過孔P1與該6個電源層L1-L6中之3個電源層之連接。調整後之印刷電路板示意圖如圖5。After the preferred connection number of the 16 vias P1-P16 and the power supply layer is obtained according to the simulation software, when the printed circuit board is actually wired, the connection of the 16 via holes P1-P16 and the power supply layers needs to be adjusted accordingly. Taking the via hole P1 as an example, the number of connections to the power supply layer is reduced from six to three, and the connection between the via hole P1 and the three power supply layers of the six power supply layers L1 - L6 is isolated by the anti-pad. The adjusted printed circuit board is shown in Figure 5.
請參閱圖4,於實驗過程中發現,根據電流小之過孔連接較多電源層及電流大之過孔連接較少電源層之原則,該16個過孔P1-P16之電流相對均勻分佈時,該16個過孔P1-P16與電源層之連接方式不唯一,但每種連接方式均能相對勻化該16個過孔P1-P16之電流分佈。本方法旨在對印刷電路板過孔電流之調節給出一種定性之指導。Referring to FIG. 4, during the experiment, it is found that the current of the 16 vias P1-P16 is relatively evenly distributed according to the principle that a small current is connected to a plurality of power layers and a large current is connected to a small power supply layer. The connection manner of the 16 via holes P1-P16 and the power supply layer is not unique, but each connection mode can relatively homogenize the current distribution of the 16 via holes P1-P16. This method is intended to give a qualitative guide to the regulation of the printed circuit board via current.
綜上可知,透過印刷電路板過孔電流調整方法,能使流過所有過孔之電流相對均勻,避免流經某些過孔之電流過大,使印刷電路板局部溫度過高,導致印刷電路板過孔銅壁被燒壞,提高印刷電路板之穩定性。In summary, the through-hole current adjustment method of the printed circuit board can make the current flowing through all the vias relatively uniform, avoiding excessive current flowing through some via holes, and causing the local temperature of the printed circuit board to be too high, resulting in a printed circuit board. The via copper wall is burned out to improve the stability of the printed circuit board.
綜上所述,本發明符合發明專利要件,爰依法提出專利 申請。惟,以上所述者僅為本發明之較佳實施方式,舉凡熟悉本案技藝之人士,於爰依本發明精神所作之等效修飾或變化,皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent, and patents are filed according to law. Application. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.
印刷電路板‧‧‧100Printed circuit board ‧‧100
過孔‧‧‧P1-P16Via ‧‧‧P1-P16
電源層‧‧‧L1-L6Power layer ‧‧‧L1-L6
圖1係一印刷電路板示意圖。Figure 1 is a schematic diagram of a printed circuit board.
圖2係圖1所示印刷電路板中之過孔電流之分佈表。Figure 2 is a table showing the distribution of via currents in the printed circuit board shown in Figure 1.
圖3係調整後之過孔與電源層連接數及過孔電流分佈表。Figure 3 shows the adjusted number of vias and power plane connections and the via current distribution table.
圖4係另一調整後之過孔與電源層連接數及過孔電流之分佈表。Fig. 4 is a table showing the distribution of the number of vias connected to the power supply layer and the distribution of via currents.
圖5係本發明較佳實施方式之印刷電路板之示意圖。Figure 5 is a schematic illustration of a printed circuit board in accordance with a preferred embodiment of the present invention.
印刷電路板‧‧‧100Printed circuit board ‧‧100
過孔‧‧‧P1-P16Via ‧‧‧P1-P16
電源層‧‧‧L1-L6Power layer ‧‧‧L1-L6
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW97114160A TWI401002B (en) | 2008-04-18 | 2008-04-18 | Print circuit board and layout thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW97114160A TWI401002B (en) | 2008-04-18 | 2008-04-18 | Print circuit board and layout thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200945971A TW200945971A (en) | 2009-11-01 |
TWI401002B true TWI401002B (en) | 2013-07-01 |
Family
ID=44869911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW97114160A TWI401002B (en) | 2008-04-18 | 2008-04-18 | Print circuit board and layout thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI401002B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6137064A (en) * | 1999-06-11 | 2000-10-24 | Teradyne, Inc. | Split via surface mount connector and related techniques |
US20090199149A1 (en) * | 2008-02-06 | 2009-08-06 | David Kwong | Methods and apparatus for layout of multi-layer circuit substrates |
-
2008
- 2008-04-18 TW TW97114160A patent/TWI401002B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6137064A (en) * | 1999-06-11 | 2000-10-24 | Teradyne, Inc. | Split via surface mount connector and related techniques |
US20090199149A1 (en) * | 2008-02-06 | 2009-08-06 | David Kwong | Methods and apparatus for layout of multi-layer circuit substrates |
Also Published As
Publication number | Publication date |
---|---|
TW200945971A (en) | 2009-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI657729B (en) | Via in a printed circuit board | |
CN105304390B (en) | LED panels and preparation method thereof, backlight module and keyboard using it | |
ATE548483T1 (en) | METHOD FOR PRODUCING MULTI-LAYER CIRCUIT BOARDS WITH HOLES REQUIRING SURFACE COATING WITH COPPER | |
US7925999B2 (en) | Method of modifying vias connection of printed circuit boards | |
WO2016058225A1 (en) | Multilayer printed circuit board | |
CN104812174A (en) | Prepreg blind hole and slot forming method | |
Lau et al. | A numerical technique to evaluate warpage behavior of double sided rigid-flex board assemblies during reflow soldering process | |
TWI401002B (en) | Print circuit board and layout thereof | |
US10356906B2 (en) | Method of manufacturing a PCB including a thick-wall via | |
CN104270903B (en) | A kind of method and apparatus for realizing tin on PCB | |
TWI678954B (en) | High-current transmitting method utilizing printed circuit board | |
CN103501577A (en) | Arranging method of PCB (Printed Circuit Board) power supply via holes | |
CN104936378B (en) | A kind of pcb board and its draw craft | |
US8383955B2 (en) | Printed circuit board | |
JP2003298238A (en) | Inverted micro via | |
US8451615B2 (en) | Printed circuit board | |
JP2014212215A (en) | Wiring board unit manufacturing method, insertion seat manufacturing method, wiring board unit and insertion seat | |
CN105916315A (en) | Manufacturing method of HDI printed circuit board | |
CN105578769B (en) | A kind of production method for the PCB for preventing drilling from pulling copper | |
TWI402007B (en) | Printed circuit board | |
CN203194010U (en) | Thick copper printed circuit board | |
Chien et al. | Taguchi DoE for solder voids reduction | |
US20100110650A1 (en) | Soldering Strategies for Printed Circuit Board Assemblies | |
Design | Assembly | |
JP2010219463A (en) | Multilayer wiring board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |