TW200945971A - Print circuit board and layout thereof - Google Patents

Print circuit board and layout thereof Download PDF

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Publication number
TW200945971A
TW200945971A TW97114160A TW97114160A TW200945971A TW 200945971 A TW200945971 A TW 200945971A TW 97114160 A TW97114160 A TW 97114160A TW 97114160 A TW97114160 A TW 97114160A TW 200945971 A TW200945971 A TW 200945971A
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TW
Taiwan
Prior art keywords
vias
circuit board
power supply
printed circuit
power
Prior art date
Application number
TW97114160A
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Chinese (zh)
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TWI401002B (en
Inventor
Ying-Tso Lai
Chien-Hung Liu
Shou-Kuo Hsu
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Hon Hai Prec Ind Co Ltd
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Priority to TW97114160A priority Critical patent/TWI401002B/en
Publication of TW200945971A publication Critical patent/TW200945971A/en
Application granted granted Critical
Publication of TWI401002B publication Critical patent/TWI401002B/en

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Abstract

A layout method of a print circuit board (PCB) includes the following steps: according to the through via with more current connecting less power layers and the through via with less current connecting more power layers, adjusting the number of the power layers connected to each through via to average the current of the through via and get the number of the power layers connected to each through via; and insulating the power layers unnecessarily connected to the through via. The layout method enhances the stability of PCB.

Description

200945971 九、發明說明: 【發明所屬之技術領域】 • 本發明係關於一種印刷電路板及其佈線方法。 【先前技術】 印刷電路板作為一種元件連接平台於電子工業中佔據 了絕對統治之地位。隨著電子產品之功能需求不斷提高, 印刷電路板亦曰益高密度化、高集成化及多層化。多層印 刷電路板通常具有多個電源層及地層,流過每個過孔電流 ©係所有與之連接之電源層提供之電流之和。 由於多層印刷電路板生產工藝之不足,各電源層上之電 流往往分佈不均,使得同一電源層對各過孔之電流貢獻不 均衡。目前,多層印刷電路板大多將每個過孔與所有電源 層連接,導致各過孔之電流大小不一,分佈極不均衡。對 於多層印刷電路板而言,單個過孔之電流有最高上限值, 當電流超過此上限值時,過孔之銅壁將被熔毁,不能正 工作。 ®【發明内容】 鑒於以上内容’有必要提供一種過孔電流相對均勻之 刷電路板。 一種印刷電路板之佈線方法,包括步驟:根據電流小之 過孔連接較多電源層及電流大之過孔連接較少電源層之原 則,使印刷電路板所有過孔之電流相對均句,以確定每個過 孔連接電源層之數量;根據上述所確定之每個過孔連接之電 源層之數量,隔離無需電性連接之過孔與電源層。本發明還 涉及-種使㈣佈㈣法設計得狀印刷t路板其包括複 6 200945971 數過孔,該等過孔所電性連接之電源層數不同。 ' 使用該印刷電路板之佈線方法能使印刷電路板所有過孔 - 電流相對均勻分佈,避免流經某些過孔之電流過大,致使印 刷電路板局部溫度過高,而導致印刷電路板過孔銅壁被燒 壞5從而提局了印刷電路板之穩定性。 【實施方式】 請參閱圖1,本發明印刷電路板在對過孔電流進行調整 時,首先於仿真軟體中構建印刷電路板100之模型,該印 ❹刷電路板100包括16個過孔PI - P16,6個電源層L1 -L6。該16個過孑L PI - P16均與6個電源層LI - L6相連。 然後於仿真軟體中將訊號輸入到該印刷電路板100 中,仿真得到流過每個過孔PI - P16之電流值,並將流過 每個過孔之電流列表,如圖2,可見該16個過孔PI - P16 之電流分佈極不均勻。流過該等過孔P9、P13、P14、P15、 P16之電流較大,流過過孔P3、P4、P7之電流較小,其中 流過過孔P13之電流最大,為7.942安培,流過過孔P7 ❹之電流最小,為0.895安培。 再根據電流小之過孔連接較多電源層及電流大之過孔 連接較少電源層之原則,於仿真軟體中不斷調整該16個過 孔PI - P16與6個電源層LI - L6之連接關係。當觀察到 該16個過孔PI - P16之電流如圖3所示時,該16個過孔 PI - P16之電流分佈相對均勻,得到該16個過孔PI - P16 與電源層LI - L6之較佳連接數。 調整後,流過過孔之最大電流由7.942安培下降為3.416 安培,最小電流由0.895安培上升為1.227安培。相應地, 200945971 該最大電流與最小電流之間之差值由7 047安培降低到 * 2.139安培。由此可見,透過變更過孔與電源層:連結關 '係,該16個過孔pl_ P16之電流能達到一個相對均勻之 狀態。需要指出的是,儘管於調整前後過孔P4與6個電 源層LI - L6之連接關係沒有改變,但流過該過孔P4之電 流由1.040安培上升到1.882安培。這是因為,任何一個 過孔與某一電源層之連接關係變化都會改變該電源層之電 流分佈狀況,從而改變流過其他過孔之電流值。 ❹ 根據仿真軟體得到該16個過孔PI - P16與電源層之較 佳連接數後,在印刷電路板實際佈線時,該16個過孔θ ρι二 P16與各電源層之連接需要相應之調節。以該過孔pi為 例’其與電源層之連接數由6個降為3個’利用反焊盤隔 離該過孔P1與該6個電源層L1_ L6中之3個電源層之連 接。調整後之印刷電路板示意圖如圖5。 請參閱圖4,於實驗過程中發現,根據電流小之過孔連 接較多電源層及電流大之過孔連接較少電源層之原則,該 ❹16個過孔P1_P16之電流相對均句分佈時,該16個過^ P1—P16與電源層之連接方式不唯一,但每種連接方式均 能相對勻化該16個過孔P1_P16之電流分佈。本方法旨 在對印刷電路板過孔電流之調節給出一種定性之指導。 综上可知,透過印刷電路板過孔電流調整方法,能使流 過所有過孔之電流相對均勻,避免流經某些過孔之電流過 大使印刷電路板局部溫度過高,導致印刷電路板過孔銅 壁被燒壞,提高印刷電路板之穩定性。 綜上所述,本發明符合發明專利要件,爰依法提出專利 8 200945971 申請。惟,以上所述者僅為本發明之較佳實施方式,舉凡 熟悉本案技藝之人士,於爰依本發明精神所作之等效修飾 或變化,皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係一印刷電路板示意圖。 圖2係圖1所示印刷電路板中之過孔電流之分佈表。 圖3係調整後之過孔與電源層連接數及過孔電流分钸 表。 圖4係另一調整後之過孔與電源層連接數及過孔電流之 分佈表。 圖5係本發明較佳實施方式之印刷電路板之示意圖。 【主要元件符號說明】 印刷電路板100 過孔 P1-P16 電源層 L1-L6200945971 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a printed circuit board and a wiring method therefor. [Prior Art] Printed circuit boards occupy an absolute dominant position in the electronics industry as a component connection platform. As the functional requirements of electronic products continue to increase, printed circuit boards also benefit from high density, high integration and multi-layering. Multilayer printed circuit boards typically have multiple power planes and ground planes through which each via current flows through the sum of the currents supplied by all of the power planes connected to it. Due to the insufficiency of the production process of the multilayer printed circuit board, the currents on the power supply layers are often unevenly distributed, so that the same power supply layer contributes unevenly to the current of each via. At present, multi-layer printed circuit boards mostly connect each via to all power layers, resulting in different currents and uneven distribution of the vias. For multilayer printed circuit boards, the current of a single via has the highest upper limit. When the current exceeds this upper limit, the copper walls of the via will be melted and will not work properly. ® [Invention] In view of the above, it is necessary to provide a brush circuit board with a relatively uniform via current. A wiring method for a printed circuit board, comprising the steps of: connecting a plurality of power supply layers and a current having a large current to connect a plurality of power supply layers according to a current having a small current to make the current of all the via holes of the printed circuit board relatively uniform; Determine the number of power connections for each via connection; isolate the vias and power planes that do not require electrical connections, based on the number of power planes connected to each via as defined above. The invention also relates to a method for designing a printed circuit board comprising a plurality of (2009) printed circuit boards, wherein the number of power supply layers electrically connected to the via holes is different. 'The wiring method of the printed circuit board enables all the vias of the printed circuit board - the current to be relatively evenly distributed, to avoid excessive current flowing through some vias, resulting in excessive local temperature of the printed circuit board, resulting in printed circuit board vias. The copper wall is burned out 5 to improve the stability of the printed circuit board. [Embodiment] Referring to FIG. 1, the printed circuit board of the present invention firstly constructs a model of the printed circuit board 100 in the simulation software when the via current is adjusted. The printer circuit board 100 includes 16 vias PI - P16, 6 power layers L1 - L6. The 16 孑 L PI - P16 are connected to 6 power layers LI - L6. Then, the signal is input into the printed circuit board 100 in the simulation software, and the current value flowing through each of the vias PI - P16 is simulated, and the current flow through each via is displayed, as shown in FIG. The current distribution of the vias PI - P16 is extremely uneven. The current flowing through the vias P9, P13, P14, P15, and P16 is large, and the current flowing through the via holes P3, P4, and P7 is small, and the current flowing through the via hole P13 is the largest, which is 7.942 amps, flowing through The current in via P7 is the smallest, 0.895 amps. According to the principle that a small current is connected to a large number of power supply layers and a large current via is connected to a small power supply layer, the connection of the 16 vias PI-P16 and the six power supply layers LI-L6 is continuously adjusted in the simulation software. relationship. When the current of the 16 vias PI - P16 is observed as shown in FIG. 3, the current distribution of the 16 vias PI - P16 is relatively uniform, and the 16 vias PI - P16 and the power layer LI - L6 are obtained. The number of connections is preferred. After adjustment, the maximum current flowing through the via decreased from 7.942 amps to 3.416 amps, and the minimum current increased from 0.895 amps to 1.227 amps. Accordingly, the difference between the maximum current and the minimum current of 200945971 is reduced from 7 047 amps to * 2.139 amps. It can be seen that the current of the 16 vias pl_P16 can reach a relatively uniform state by changing the via and the power supply layer. It should be noted that although the connection relationship between the via hole P4 and the six power source layers LI - L6 is not changed before and after the adjustment, the current flowing through the via hole P4 rises from 1.040 amps to 1.882 amps. This is because any change in the connection relationship between a via and a power plane changes the current distribution of the power plane and changes the current flowing through the other vias. ❹ According to the simulation software, the number of connections between the 16 vias PI-P16 and the power layer is obtained. When the printed circuit board is actually wired, the connection of the 16 vias θ ρι P16 to the power layers needs to be adjusted accordingly. . Taking the via pi as an example, the number of connections to the power supply layer is reduced from six to three. The via pad P1 is used to isolate the via hole P1 from the three power supply layers of the six power supply layers L1_L6. The adjusted printed circuit board is shown in Figure 5. Referring to FIG. 4, during the experiment, it is found that the current of the 16 vias P1_P16 is relatively uniform when the current is connected to the power supply layer and the current is larger than the power supply layer. The connection between the 16 P1 and P16 and the power supply layer is not unique, but each connection mode can relatively homogenize the current distribution of the 16 vias P1_P16. This method is intended to give a qualitative guide to the regulation of the via current of a printed circuit board. In summary, through the printed circuit board through-hole current adjustment method, the current flowing through all the via holes can be relatively uniform, and the current flowing through some of the via holes is too large, so that the local temperature of the printed circuit board is too high, resulting in the printed circuit board passing. The copper wall of the hole is burned out to improve the stability of the printed circuit board. In summary, the present invention complies with the requirements of the invention patent, and patents are filed according to law 8 200945971. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. [Simple description of the drawing] Fig. 1 is a schematic diagram of a printed circuit board. Figure 2 is a table showing the distribution of via currents in the printed circuit board shown in Figure 1. Figure 3 shows the adjusted number of vias and power plane connections and the via current distribution table. Fig. 4 is a table showing the distribution of the number of vias connected to the power supply layer and the via current. Figure 5 is a schematic illustration of a printed circuit board in accordance with a preferred embodiment of the present invention. [Main component symbol description] Printed circuit board 100 via P1-P16 power supply layer L1-L6

Claims (1)

200945971 k申請專利範圍 1 種印刷電路板之佈線方法,包括步驟: 根據電流小之過孔連接較多電源層及電流大之過孔連接較 少電源層之原則’使印刷電路板所有過孔之電流相對均 勻,以確定每個過孔連接電源層之數量; 根據上述所確定之每個過孔連接之電源層之數量,隔離無 需電性連接之過孔與電源層。 ❹ 2.如申請專利範圍第i項所述之印刷電路板之佈線方 法,其中每個過孔連接電源層之數量,是通過於仿真軟體 _對印刷電路板模型’根據電流小之過孔連接較多電源層 =流大之過孔連純少電源層之㈣,使印刷電路板模 i中所有過孔之電流相對均勻而確定。 、 3電:刷:路板,包括複數過孔與電源層,該等過孔所 =電源層數不完全相同,而使流經所有過孔之電 ❹ 荆^申明專利範圍第3項所述之印刷電路板,其中該印 刷電路板包括16個過孔及6個電 八以 層之過孔有!個,連接2個電連接1個電源 個電源層之過孔有3個,連接^電^有4個,連接3 連接5個電源層之過孔有3個::過孔有4個, 1個。 接6個電源層之過孔有 5.如申請專利範圍第3項所述之 I電路板包括16_孔及6個電 ^^其中該印 層之過孔有1個,連接2個電 :中連接1個電源 個電源層之過孔有5個,連接 二:有2個,連接3 電/原層之過孔有4個, 200945971 連接5個電源層之過孔有3個,連接6個電源層之過孔有 * 1個。200945971 k Patent application scope 1 wiring method of printed circuit board, including the steps: According to the principle of connecting a small number of power supply layers with a small current via and a large current via, connecting the less power supply layer to make all the vias of the printed circuit board The current is relatively uniform to determine the number of power connections to each via; to isolate the vias and power planes that do not require electrical connections, as determined by the number of power planes connected to each via. ❹ 2. The wiring method of the printed circuit board according to the invention of claim i, wherein the number of power layers connected to each of the via holes is through the simulation software _ to the printed circuit board model 'via small current via connection More power supply layer = large flow vias with less power supply layer (4), so that the current of all vias in the printed circuit board mode i is relatively uniform and determined. 3 electricity: brush: the road board, including the plurality of vias and the power supply layer, the number of the power supply layers is not exactly the same, and the electricity flowing through all the via holes is described in the third paragraph of the patent scope. A printed circuit board in which the printed circuit board includes 16 vias and 6 electrical vias with vias! There are 3 vias for connecting 2 power connections to one power supply layer, 4 for connection ^^, 3 for vias for connecting 5 power layers: 4 for vias, 1 One. The via hole of the six power supply layers is 5. The I circuit board of the third aspect of the patent application includes 16_holes and 6 electric circuits, wherein one of the via holes of the printed layer has two electric connections: There are 5 vias for connecting one power supply and one power supply layer. There are two connections: two, and four vias for connecting 3 electric/original layers. 200945971 There are 3 vias connecting 5 power supply layers, and 6 connections. There are *1 vias for each power plane. 1111
TW97114160A 2008-04-18 2008-04-18 Print circuit board and layout thereof TWI401002B (en)

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Publication number Priority date Publication date Assignee Title
US6137064A (en) * 1999-06-11 2000-10-24 Teradyne, Inc. Split via surface mount connector and related techniques
US7996806B2 (en) * 2008-02-06 2011-08-09 Electronics For Imaging, Inc. Methods and apparatus for layout of multi-layer circuit substrates

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