CN103501577A - Arranging method of PCB (Printed Circuit Board) power supply via holes - Google Patents
Arranging method of PCB (Printed Circuit Board) power supply via holes Download PDFInfo
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- CN103501577A CN103501577A CN201310492370.7A CN201310492370A CN103501577A CN 103501577 A CN103501577 A CN 103501577A CN 201310492370 A CN201310492370 A CN 201310492370A CN 103501577 A CN103501577 A CN 103501577A
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Abstract
The invention discloses an arranging method of PCB (Printed Circuit Board) power supply via holes, belonging to the field of a PCB. The method comprises the steps as follows: firstly, setting the number of via holes according to bearing current, ranging from 0.5A-3A, of each via hole, then forming the via holes in a PCB by two parallel rows, wherein the distance between the two adjacent via holes in each row is the same, the two rows of via holes are formed in a staggered manner, and holes of one row of via holes are dead against the copper paving parts of the other row of via holes, and a copper-plated via hole wall and a bonding pad are sequentially arranged at the outer periphery of the holes from inside to outside. Compared with the prior art, the arranging method of PCB power supply via holes has the characteristics of being reasonable in design, easy to process and the like, not only can the power supply completeness be favorable, but also the signal quality can also be greatly improved, and the signal completeness can be facilitated.
Description
Technical field
The present invention relates to the PCB field of circuit boards, specifically a kind of arrangement method of PCB power vias.
Background technology
Via hole (Via) is one of important component part of PCB, be covered with thickly dotted via hole on whole pcb board, wherein some via hole has been used for the connection of each layer signal line, what have is used for connecting Power Plane, some is used for connecting GND, also some is used for doing heat radiation use etc., and this makes via hole become the important component part of PCB, and the expense of boring has also accounted for 30% left and right of whole pcb board.
From design angle, a via hole mainly contains pad, anti-pad, boring and the hole wall of electroplating form, but the effect of via hole just completes the connection of different layers signal or Power etc., for the layer that there is no holding wire and need to connect, the existence of via hole can make the PCB circuit board leave a cavity on the contrary, will produce non-continuous event to the plane of reference of signal like this, make the Plane of bus plane or bottom be full of cavity, destroy Power Integrity.In addition, if via hole put misarrangement, the electric current that can make the part via hole pass through is large, the part via hole may have loaded current hardly, the via hole temperature of bearing great current can be very high, there is the very large danger of breaking in this via hole.Not only affect the use function of mainboard after via hole breaks, but also may the outward appearance of PCB be exerted an influence, have a strong impact on designing quality.
At present, in the PCB design process, whether the number of only focusing on via hole meets designing requirement, and putting and arranging of via hole do not done to some standards settings, caused arbitrarily putting of via hole, possible everyone each time the via hole of Layout put differently, for PCB, design brings very large risk for this.
summary of the invention
Technical assignment of the present invention is to provide a kind of arrangement method of PCB power vias.
Technical assignment of the present invention is realized in the following manner, the method step is as follows: but first by each via hole loaded current, in the scope of 0.5A-3A, set the number of via hole, then via hole being divided into to two parallel rows is arranged on the PCB circuit board, distance between adjacent two via holes of every row is identical, be crisscross arranged between two row's via holes, make the paving copper part of the hole of row's via hole over against another row's via hole; The periphery of hole is that hole wall and pad are crossed in copper facing from inside to outside successively.
Between the center of circle of adjacent two via holes of described every row, apart from a, be: the diameter of two holes adds 6mil.
Between the center of circle of described two row's via holes, horizontal range b is: the diameter of a pad.
The arrangement method of a kind of PCB power vias of the present invention compared to the prior art, have reasonable in design, be easy to the characteristics such as processing, not only be conducive to Power Integrity but also improved greatly the quality of signal, be easy to signal integrity.
The accompanying drawing explanation
The structural representation that accompanying drawing 1 is put for a kind of PCB power vias;
In figure: 1, PCB circuit board, 2, hole, 3, copper facing crosses hole wall, 4, pad.
Embodiment
Embodiment 1:
Via hole comprises that hole 2, copper facing crosses hole wall 3 and pad 4, and hole 2 has the identical center of circle with pad 4, and the periphery of hole 2 is that hole wall 3 and pad 4 are crossed in copper facing from inside to outside successively.
But the number of setting via hole in the scope of 0.5A-3A by each via hole loaded current is 20, every 10 via holes are a row, via hole is divided into to two parallel rows and is arranged on PCB circuit board 1, between the center of circle of adjacent two via holes of every row apart from a be: the diameter of two holes 2 adds 6mil; (the center of circle of a hole 2 in row's via hole is crisscross arranged between two row's via holes, the intermediate point of distance between corresponding another two hole 2 centers of circle of row of level), make the paving copper part of the hole 2 of row's via hole over against another row's via hole, between the center of circle of two row's via holes, horizontal range b is: the diameter of a pad 4.
Embodiment 2:
Via hole comprises that hole 2, copper facing crosses hole wall 3 and pad 4, and hole 2 has the identical center of circle with pad 4, and the periphery of hole 2 is that hole wall 3 and pad 4 are crossed in copper facing from inside to outside successively.
But the number of setting via hole in the scope of 0.5A-3A by each via hole loaded current is 16, every 8 via holes are a row, via hole is divided into to two parallel rows and is arranged on PCB circuit board 1, between the center of circle of adjacent two via holes of every row apart from a be: the diameter of two holes 2 adds 6mil; (the center of circle of a hole 2 in row's via hole is crisscross arranged between two row's via holes, the intermediate point of distance between corresponding another two hole 2 centers of circle of row of level), make the paving copper part of the hole 2 of row's via hole over against another row's via hole, between the center of circle of two row's via holes, horizontal range b is: the diameter of a pad 4.
Embodiment 3:
Via hole comprises that hole 2, copper facing crosses hole wall 3 and pad 4, and hole 2 has the identical center of circle with pad 4, and the periphery of hole 2 is that hole wall 3 and pad 4 are crossed in copper facing from inside to outside successively.
But the number of setting via hole in the scope of 0.5A-3A by each via hole loaded current is 28, every 14 via holes are a row, via hole is divided into to two parallel rows and is arranged on PCB circuit board 1, between the center of circle of adjacent two via holes of every row apart from a be: the diameter of two holes 2 adds 6mil; (the center of circle of a hole 2 in row's via hole is crisscross arranged between two row's via holes, the intermediate point of distance between corresponding another two hole 2 centers of circle of row of level), make the paving copper part of the hole 2 of row's via hole over against another row's via hole, between the center of circle of two row's via holes, horizontal range b is: the diameter of a pad 4.
The via hole that above-mentioned three embodiment arrange, make via hole electric current relatively uniform pulling load current well.The maximum current passed through in all via holes is 2.87A, the minimum current of passing through is 0.9A, both differ 1.97A, difference between via hole has reduced 1.53A than initial designs (random via hole setting) like this, the distribution of via hole electric current is relatively more even, effectively reduces the difference between the via hole electric current.
Claims (3)
1. the arrangement method of a PCB power vias, it is characterized in that, the method step is as follows: but first by each via hole loaded current, in the scope of 0.5A-3A, set the number of via hole, then via hole being divided into to two parallel rows is arranged on the PCB circuit board, distance between adjacent two via holes of every row is identical, be crisscross arranged between two row's via holes, make the paving copper part of the hole of row's via hole over against another row's via hole; The periphery of hole is that hole wall and pad are crossed in copper facing from inside to outside successively.
2. the arrangement method of PCB power vias according to claim 1, is characterized in that, between the center of circle of adjacent two via holes of described every row, apart from a, is: the diameter of two holes adds 6mil.
3. the arrangement method of PCB power vias according to claim 1, is characterized in that, between the center of circle of described two row's via holes, horizontal range b is: the diameter of a pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310492370.7A CN103501577A (en) | 2013-10-21 | 2013-10-21 | Arranging method of PCB (Printed Circuit Board) power supply via holes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310492370.7A CN103501577A (en) | 2013-10-21 | 2013-10-21 | Arranging method of PCB (Printed Circuit Board) power supply via holes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103501577A true CN103501577A (en) | 2014-01-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310492370.7A Pending CN103501577A (en) | 2013-10-21 | 2013-10-21 | Arranging method of PCB (Printed Circuit Board) power supply via holes |
Country Status (1)
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| CN (1) | CN103501577A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016095283A1 (en) * | 2014-12-18 | 2016-06-23 | 深圳市华星光电技术有限公司 | Inductor, circuit board and realization method of inductor |
| CN105955437A (en) * | 2016-04-21 | 2016-09-21 | 浪潮电子信息产业股份有限公司 | Position placing method of power via hole and PCB |
| CN105956341A (en) * | 2016-06-22 | 2016-09-21 | 浪潮集团有限公司 | Skill realization method for automatically calculating actual width of power supply poured copper |
| US9615459B2 (en) | 2014-12-18 | 2017-04-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Inductor, circuit board, and implementing method of the inductor |
| WO2021120278A1 (en) * | 2019-12-18 | 2021-06-24 | Tcl华星光电技术有限公司 | Array substrate and display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010047880A1 (en) * | 1999-03-01 | 2001-12-06 | Abbott Donald C. | Double sided flexible circuit for integrated circuit packages and method of manufacture |
| US20030165051A1 (en) * | 2000-03-13 | 2003-09-04 | Kledzik Kenneth J. | Modular integrated circuit chip carrier |
| CN102116817A (en) * | 2009-12-31 | 2011-07-06 | 德律科技股份有限公司 | Electrical connection defect detection device |
-
2013
- 2013-10-21 CN CN201310492370.7A patent/CN103501577A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010047880A1 (en) * | 1999-03-01 | 2001-12-06 | Abbott Donald C. | Double sided flexible circuit for integrated circuit packages and method of manufacture |
| US20030165051A1 (en) * | 2000-03-13 | 2003-09-04 | Kledzik Kenneth J. | Modular integrated circuit chip carrier |
| CN102116817A (en) * | 2009-12-31 | 2011-07-06 | 德律科技股份有限公司 | Electrical connection defect detection device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016095283A1 (en) * | 2014-12-18 | 2016-06-23 | 深圳市华星光电技术有限公司 | Inductor, circuit board and realization method of inductor |
| US9615459B2 (en) | 2014-12-18 | 2017-04-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Inductor, circuit board, and implementing method of the inductor |
| CN105955437A (en) * | 2016-04-21 | 2016-09-21 | 浪潮电子信息产业股份有限公司 | Position placing method of power via hole and PCB |
| CN105956341A (en) * | 2016-06-22 | 2016-09-21 | 浪潮集团有限公司 | Skill realization method for automatically calculating actual width of power supply poured copper |
| WO2021120278A1 (en) * | 2019-12-18 | 2021-06-24 | Tcl华星光电技术有限公司 | Array substrate and display panel |
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| C06 | Publication | ||
| PB01 | Publication | ||
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| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140108 |