TWI399828B - Method of fabricating transient voltage suppressor (tvs) with changeable avalanche voltage - Google Patents

Method of fabricating transient voltage suppressor (tvs) with changeable avalanche voltage Download PDF

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TWI399828B
TWI399828B TW98102079A TW98102079A TWI399828B TW I399828 B TWI399828 B TW I399828B TW 98102079 A TW98102079 A TW 98102079A TW 98102079 A TW98102079 A TW 98102079A TW I399828 B TWI399828 B TW I399828B
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transient voltage
substrate
voltage suppressor
manufacturing
deep doped
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TW98102079A
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TW201029113A (en
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Chung Yu Kuo
Tzu Chiang Wang
Tsang Sheng Chang
Chih Huan Shen
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Anova Technology Co Ltd
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可改變耐壓之瞬態電壓抑制器製造方法Transient voltage suppressor manufacturing method capable of changing withstand voltage

本發明係為一種可改變耐壓之瞬態電壓抑制器製造方法,特別為一種應用於瞬態電壓抑制器之可改變耐壓之瞬態電壓抑制器製造方法。The invention relates to a method for manufacturing a transient voltage suppressor capable of changing withstand voltage, in particular to a method for manufacturing a transient voltage suppressor capable of changing withstand voltage applied to a transient voltage suppressor.

在電.子裝置中,常因突波而破壞了電子裝置之控制電路,並導致控制電路喪失功能,嚴重時更有可能引起觸電以及電器短路而失火,進而危害到使用者之人身安全,因此電子裝置中多會設置可抑制突波之元件,以保護控制電路不受到影響。In an electric sub-device, the control circuit of the electronic device is often destroyed by the glitch, and the control circuit loses its function. In severe cases, it is more likely to cause electric shock and short circuit of the electric appliance, thereby jeopardizing the personal safety of the user. In the electronic device, an element that suppresses the surge is provided to protect the control circuit from being affected.

而瞬態電壓抑制器(Transient Voltage Suppressor,TVS)即為一種具有抑制突波功能之元件,其係為二極體結構,因此可利用二極體非線性歐姆特性,使得當穩定電壓輸入控制電路時,瞬態電壓抑制器對控制電路呈現高阻抗狀態。然而當輸入之電壓瞬間升高而出現突波時,由於電壓急速增加,因此使得瞬態電壓抑制器之阻抗值迅速下降,並形成一短路狀態,進而提供一低阻抗路徑,藉此突波電壓之電流可被導離而不影響控制電路,並達到保護控制電路之功效。The Transient Voltage Suppressor (TVS) is a component with a function of suppressing the surge, which is a diode structure, so the nonlinear ohmic characteristics of the diode can be utilized, so that the stable voltage input control circuit The transient voltage suppressor presents a high impedance state to the control circuit. However, when the input voltage rises instantaneously and a surge occurs, the voltage value of the transient voltage suppressor rapidly drops due to the rapid increase of the voltage, and a short circuit state is formed, thereby providing a low impedance path, thereby using the surge voltage. The current can be conducted away without affecting the control circuit and achieving the effectiveness of the protection control circuit.

第1圖係為曾納二極體之電壓-電流特性曲線圖。Figure 1 is a graph of the voltage-current characteristics of a Zener diode.

由於瞬態電壓抑制器之工作原理與曾納二極體類似,因此舉例來說瞬態電壓抑制器之特性曲線圖可如第1圖所示,其中輸入電壓小於5伏特為場發射區域,而輸入電壓介於5伏特至7.5伏特之間屬於過渡區域,又輸入電壓8伏特時,則為瞬態電壓抑制器之崩潰電壓。Since the transient voltage suppressor works similarly to the Zener diode, for example, the characteristic curve of the transient voltage suppressor can be as shown in Fig. 1, where the input voltage is less than 5 volts for the field emission region, and The input voltage is between 5 volts and 7.5 volts, which is the transition region. When the input voltage is 8 volts, it is the breakdown voltage of the transient voltage suppressor.

而由此特性曲線圖可知,當瞬態電壓抑制器之輸入電壓大於8伏特時,可以穩定產生大量輸出電流,然而當瞬態電壓抑制器之輸入電壓小於8伏特時,由於場發射效應之影響,而使得瞬態電壓抑制器之阻抗值變化不穩定產生了漏電流。From this characteristic graph, when the input voltage of the transient voltage suppressor is greater than 8 volts, a large amount of output current can be stably generated. However, when the input voltage of the transient voltage suppressor is less than 8 volts, the effect of the field emission effect is affected. The instability of the impedance value of the transient voltage suppressor causes leakage current.

又根據市面上瞬態電壓抑制器規格書中所載,瞬態電壓抑制器分別應用於過渡區域與崩潰電壓時,其間之漏電流數值有高達到200至500倍的差異,如此使得瞬態電壓抑制器應用於低電壓之過渡區域時產生信賴性不佳及額定消耗功率過高之缺點,進而導致瞬態電壓抑制器不適合應用於低電壓之電子裝置。According to the specification of the transient voltage suppressor on the market, when the transient voltage suppressor is applied to the transition region and the breakdown voltage respectively, the leakage current value between them is 200 to 500 times higher, so that the transient voltage is made. When the suppressor is applied to the transition region of low voltage, it has the disadvantages of poor reliability and high rated power consumption, which in turn makes the transient voltage suppressor unsuitable for low voltage electronic devices.

本發明係為一種可改變耐壓之瞬態電壓抑制器製造方法,其係於基板中形成深度摻雜層,以降低線性阻抗,並達到提升瞬態電壓抑制器功率之功效。The invention is a method for manufacturing a transient voltage suppressor capable of changing withstand voltage, which forms a deep doped layer in a substrate to reduce linear impedance and achieve the effect of improving the power of the transient voltage suppressor.

本發明係為一種可改變耐壓之瞬態電壓抑制器製造方法,其係於清洗基板之過程中增加蝕刻溶液、混合酸及王水之清洗步驟,以完全清除基板表面之氧化層。The invention relates to a method for manufacturing a transient voltage suppressor capable of changing withstand voltage, which is a step of cleaning the etching solution, the mixed acid and the aqua regia during the process of cleaning the substrate to completely remove the oxide layer on the surface of the substrate.

本發明係為一種可改變耐壓之瞬態電壓抑制器製造方法,其係於熱處理基板過程中,以改變熱處理溫度之方式而形成不同厚度之氧化層,藉以達到改變耐壓之功效,進而應用於降低過渡區域及場發射區域之漏電流。The invention is a method for manufacturing a transient voltage suppressor capable of changing withstand voltage, which is formed by forming an oxide layer of different thickness by changing the heat treatment temperature during the process of heat-treating the substrate, thereby achieving the effect of changing the withstand voltage, and then applying To reduce the leakage current in the transition region and the field emission region.

本發明係為一種可改變耐壓之瞬態電壓抑制器製造方法,其係於熱處理基板過程中加入含氯氣體,因此可形成具有穩定電荷功效之含氯氧化絕緣層。The present invention is a method for manufacturing a transient voltage suppressor capable of changing withstand voltage, which is added to a chlorine-containing gas during heat treatment of a substrate, thereby forming a chlorine-containing oxide insulating layer having a stable charge effect.

為達上述功效,本發明提供一種可改變耐壓之瞬態電壓抑制器製造方法,其包括下列步驟:提供一基板,其具有:一對深度摻雜層,其係以驅入擴散方式形成於基板之兩側,且深度摻雜層係由一第一型深度摻雜層及一第二型深度摻雜層所組成,又於深度摻雜層間形成一第一型原始基板層;圖案化基板,其係蝕刻第二型深度摻雜層及第一型原始基板層,以穿透第二型深度摻雜層並形成至少一溝槽於第一型原始基板層上;清洗基板,其包括下列步驟:浸泡基板於一蝕刻溶液中,且蝕刻溶液係由氫氟酸與去離子水以一第一溶液體積比例組成;使用一混合酸溶液清洗基板,且混合酸溶液係由硝酸、氫氟酸與醋酸溶液以一第二溶液體積比例組成;以及浸泡基板於一王水溶液中,且王水溶液係由硝酸、鹽酸與去離子水以一第三溶液體積比例組成;熱處理基板,以於溝槽表面生成一氧化絕緣層,其包括下列步驟:在一氮氣環境下以一第一溫度熱處理3分鐘;在混合氮氣、一含氯氣體及一氧氣之環境下以一第二溫度熱處理17分鐘;在混合氮氣、含氯氣體及氧氣之環境下以一第三溫度熱處理90分鐘;在混合氮氣及氧氣之環境下以一第四溫度熱處理2分鐘;以及在氮氣環境下以一第五溫度熱處理10秒鐘;以及形成一對金屬電極,其係分別覆蓋於深度摻雜層之表面,且使氧化絕緣層係裸露於金屬電極之外。In order to achieve the above effects, the present invention provides a method for fabricating a transient voltage suppressor capable of changing withstand voltage, comprising the steps of: providing a substrate having: a pair of deeply doped layers formed by diffusion diffusion The two sides of the substrate, and the deep doped layer is composed of a first type deep doped layer and a second type deep doped layer, and a first type original substrate layer is formed between the deep doped layers; the patterned substrate Etching the second type deep doped layer and the first type original substrate layer to penetrate the second type deep doped layer and form at least one trench on the first type original substrate layer; cleaning the substrate, including the following Step: soaking the substrate in an etching solution, and the etching solution is composed of hydrofluoric acid and deionized water in a first solution volume ratio; cleaning the substrate with a mixed acid solution, and mixing the acid solution with nitric acid, hydrofluoric acid And the acetic acid solution is composed of a second solution volume ratio; and the substrate is immersed in an aqueous solution of the king, and the aqueous solution of the king is composed of nitric acid, hydrochloric acid and deionized water in a volume ratio of the third solution; Forming an oxidized insulating layer on the surface of the trench, comprising the steps of: heat-treating at a first temperature for 3 minutes in a nitrogen atmosphere; heat-treating at a second temperature in a mixed nitrogen, a chlorine-containing gas, and an oxygen atmosphere; Minute; heat treatment at a third temperature for 90 minutes in a mixed nitrogen, chlorine gas, and oxygen atmosphere; heat treatment at a fourth temperature for 2 minutes in a mixed nitrogen and oxygen atmosphere; and a fifth temperature in a nitrogen atmosphere Heat treatment for 10 seconds; and forming a pair of metal electrodes respectively covering the surface of the deep doped layer and exposing the oxidized insulating layer to the outside of the metal electrode.

藉由本發明的實施,至少可達到下列進步功效:With the implementation of the present invention, at least the following advancements can be achieved:

一、利用調整熱處理之溫度,以改變瞬態電壓抑制器之耐壓,進而降低瞬態電壓抑制器應用於低電壓之漏電流。First, the temperature of the heat treatment is adjusted to change the withstand voltage of the transient voltage suppressor, thereby reducing the leakage current of the transient voltage suppressor applied to the low voltage.

二、由於瞬態電壓抑制器應用於低電壓時漏電流獲得改善,所以可達到增加瞬態電壓抑制器於低電壓應用時之信賴性及降低額定消耗功率之功效。Second, since the transient voltage suppressor is improved when the low voltage is applied, the reliability of the transient voltage suppressor in low voltage applications and the reduction of the rated power consumption can be achieved.

為了使任何熟習相關技藝者了解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點,因此將在實施方式中詳細敘述本發明之詳細特徵以及優點。In order to make those skilled in the art understand the technical content of the present invention and implement it, and according to the disclosure, the patent scope and the drawings, the related objects and advantages of the present invention can be easily understood by those skilled in the art. The detailed features and advantages of the present invention will be described in detail in the embodiments.

第2圖係為本發明之一種可改變耐壓之瞬態電壓抑制器製造方法S100之流程實施例圖。第3圖係為本發明之一種基板10之剖視實施例圖。第4圖係為本發明之一種具有溝槽14之基板10之剖視實施例圖。第5圖係為本發明之一種清洗基板步驟S30之流程實施例圖。第6圖係為本發明之一種熱處理基板步驟S40之流程實施例圖。第7圖係為本發明之一種具有氧化絕緣層15之基板10之剖視實施例圖。第8圖係為本發明之一種瞬態電壓抑制器之剖視實施例圖。Fig. 2 is a flow chart showing an embodiment of a method for manufacturing a transient voltage suppressor S100 capable of changing withstand voltage. Fig. 3 is a cross-sectional view showing a substrate 10 of the present invention. Figure 4 is a cross-sectional view of a substrate 10 having a trench 14 of the present invention. Fig. 5 is a flow chart showing an embodiment of a step S30 of cleaning a substrate of the present invention. Fig. 6 is a view showing a flow chart of a step S40 of heat-treating the substrate of the present invention. Figure 7 is a cross-sectional view showing a substrate 10 having an oxidized insulating layer 15 of the present invention. Figure 8 is a cross-sectional view of a transient voltage suppressor of the present invention.

如第2圖所示,本實施例係為一種可改變耐壓之瞬態電壓抑制器製造方法S100,其包括下列步驟:提供一基板S10;圖案化基板S20;清洗基板S30;熱處理基板S40;以及形成一對金屬電極S50。As shown in FIG. 2, this embodiment is a transient voltage suppressor manufacturing method S100 capable of changing withstand voltage, comprising the steps of: providing a substrate S10; patterning the substrate S20; cleaning the substrate S30; heat treating the substrate S40; And forming a pair of metal electrodes S50.

提供一基板S10:如第3圖所示,基板10係可以為一矽基板,且分別於基板10之兩側以驅入擴散(drive-in diffusion)方式形成一對深度摻雜層11、12。而使用具有深度摻雜層11、12之基板10製作之瞬態電壓抑制器可具有較低之線性阻抗,因此可達到降低額定消耗功率之功效。又基板10之深度摻雜層11、12包括一第一型深度摻雜層11及一第二型深度摻雜層12,且第一型深度摻雜層11及第二型深度摻雜層12間又形成一第一型原始基板層13。A substrate S10 is provided. As shown in FIG. 3, the substrate 10 can be a germanium substrate, and a pair of deep doped layers 11 and 12 are formed on both sides of the substrate 10 by drive-in diffusion. . The transient voltage suppressor fabricated using the substrate 10 having the deep doped layers 11, 12 can have a lower linear impedance, thereby achieving the effect of reducing the rated power consumption. Further, the deep doped layers 11 and 12 of the substrate 10 include a first type deep doped layer 11 and a second type deep doped layer 12, and the first type deep doped layer 11 and the second type deep doped layer 12 A first type of original substrate layer 13 is formed again.

舉例來說,當瞬態電壓抑制器應用於抑制負突波時,第一型深度摻雜層11可以為一N型深度摻雜層,而第二型深度摻雜層12則可以為一P型深度摻雜層,並且第一型原始基板層13便為一N型原始基板層。相反地,當第一型深度摻雜層11為一P型深度摻雜層時,瞬態電壓抑制器可應用於抑制正突波,此時第二型深度摻雜層12則可以為一N型深度摻雜層,而第一型原始基板層13為一P型原始基板層。For example, when the transient voltage suppressor is applied to suppress negative surges, the first type deep doped layer 11 may be an N type deep doped layer, and the second type deep doped layer 12 may be a P. The deep doped layer is formed, and the first type original substrate layer 13 is an N-type original substrate layer. Conversely, when the first type deep doped layer 11 is a P type deep doped layer, the transient voltage suppressor can be applied to suppress the positive glitch, and the second type deep doped layer 12 can be a N. The deep-doped layer is formed, and the first-type original substrate layer 13 is a P-type original substrate layer.

圖案化基板S20:其係可使用現行之微影曝光技術於基板10之第二型深度摻雜層12表面形成圖案後,再透過蝕刻技術蝕刻第二型深度摻雜層12表面之圖案,而蝕刻之深度係如第4圖所示,其係穿透第二型深度摻雜層12,並且形成至少一溝槽14於第一型原始基板層13上。The patterned substrate S20 is formed by patterning the surface of the second type deep doping layer 12 of the substrate 10 by using the current lithography exposure technique, and then etching the pattern of the surface of the second type deep doping layer 12 by etching. The depth of the etch is as shown in FIG. 4, which penetrates the second type deep doped layer 12 and forms at least one trench 14 on the first type original substrate layer 13.

清洗基板S30:如第5圖所示,清洗基板步驟S30又可細分為下列步驟:浸泡基板於一蝕刻溶液中S31;使用一混合酸溶液清洗基板S32;以及浸泡基板於一王水溶液中S33。Cleaning the substrate S30: As shown in FIG. 5, the cleaning substrate step S30 can be further subdivided into the following steps: soaking the substrate in an etching solution S31; cleaning the substrate S32 with a mixed acid solution; and soaking the substrate in an aqueous solution of S33.

浸泡基板於一蝕刻溶液中S31:由於基板10暴露於空氣中時,基板10的表面易生成有多餘之氧化層,而蝕刻溶液則可用以移除基板10表面多餘之氧化層,並且蝕刻溶液係由氫氟酸與去離子水以一第一溶液體積比例組成,又第一溶液體積比例係可以為1:4。Soaking the substrate in an etching solution S31: Since the substrate 10 is exposed to the air, the surface of the substrate 10 is likely to have an excess oxide layer, and the etching solution can be used to remove excess oxide layer on the surface of the substrate 10, and the etching solution is The hydrofluoric acid and deionized water are combined in a first solution volume ratio, and the first solution volume ratio may be 1:4.

使用一混合酸溶液清洗基板S32:由於以蝕刻溶液移除氧化層後之基板10表面為粗糙不平整之表面,因此可使用混合酸溶液清洗基板10表面,並使基板10表面光滑平整,而混合酸溶液係由硝酸、氫氟酸與醋酸溶液以一第二溶液體積比例組成,又第二溶液體積比例可以為12:1:6。The substrate S32 is cleaned by using a mixed acid solution: since the surface of the substrate 10 after removing the oxide layer by the etching solution is a rough uneven surface, the surface of the substrate 10 can be cleaned using a mixed acid solution, and the surface of the substrate 10 can be smoothed and mixed. The acid solution is composed of nitric acid, hydrofluoric acid and acetic acid solution in a second solution volume ratio, and the second solution volume ratio may be 12:1:6.

浸泡基板於一王水溶液中S33:為了確保基板10表面氧化層已完全清除,並避免影響後續製程之品質,因此可使用王水溶液再次清除基板10表面之氧化層,使得基板10表面之氧化層可完全被移除,而王水溶液係由硝酸、鹽酸與去離子水以一第三溶液體積比例組成,又第三溶液體積比例可以為7:6:30。Soaking the substrate in a king aqueous solution S33: In order to ensure that the surface oxide layer of the substrate 10 has been completely removed, and to avoid affecting the quality of the subsequent process, the oxide layer on the surface of the substrate 10 can be removed again by using the aqueous solution of the king, so that the oxide layer on the surface of the substrate 10 can be It is completely removed, and the aqueous solution of the king is composed of nitric acid, hydrochloric acid and deionized water in a third solution volume ratio, and the third solution volume ratio can be 7:6:30.

熱處理基板S40:如第6圖及第7圖所示,對基板10進行熱處理,以於基板10之溝槽14表面生成一氧化絕緣層15,而熱處理基板步驟S40亦可細分為下列步驟:在一氮氣環境下以一第一溫度熱處理3分鐘S41;在混合氮氣、一含氯氣體及一氧氣之環境下以一第二溫度熱處理17分鐘S42;在混合氮氣、含氯氣體及氧氣之環境下以一第三溫度熱處理90分鐘S43;在混合氮氣及氧氣之環境下以一第四溫度熱處理2分鐘S44;以及在氮氣環境下以一第五溫度熱處理10秒鐘S45。Heat-treating the substrate S40: as shown in FIGS. 6 and 7, heat-treating the substrate 10 to form an oxidized insulating layer 15 on the surface of the trench 14 of the substrate 10, and the heat-treating substrate step S40 may also be subdivided into the following steps: Heat treatment at a first temperature for 3 minutes in a nitrogen atmosphere; heat treatment at a second temperature for 17 minutes in a mixed nitrogen, a chlorine-containing gas, and an oxygen atmosphere; in a mixed nitrogen, chlorine-containing gas, and oxygen atmosphere Heat treatment at a third temperature for 90 minutes S43; heat treatment at a fourth temperature for 2 minutes S44 in a mixed nitrogen and oxygen atmosphere; and heat treatment at a fifth temperature for 10 seconds S45 under a nitrogen atmosphere.

如第7圖所示,於熱處理基板S40之過程中,連續且依序地操作上述之每一步驟,使得基板10之溝槽14表面經過熱處理以形成氧化絕緣層15,而熱處理基板10之過程中第一溫度係可以為800℃、第二溫度係可以為950℃、第三溫度與第四溫度則可以介於1000℃-1200℃之間,以及第五溫度係可以為800℃。As shown in FIG. 7, in the process of heat-treating the substrate S40, each of the above steps is continuously and sequentially operated, so that the surface of the trench 14 of the substrate 10 is subjected to heat treatment to form the oxidized insulating layer 15, and the process of heat-treating the substrate 10 is performed. The first temperature system may be 800 ° C, the second temperature system may be 950 ° C, the third temperature and the fourth temperature may be between 1000 ° C and 1200 ° C, and the fifth temperature system may be 800 ° C.

如第6圖所示,當基板10經由在混合氮氣、含氯氣體及氧氣之環境下以第三溫度熱處理90分鐘步驟S43以及在混合氮氣及氧氣之環境下以第四溫度熱處理2分鐘步驟S44時,可藉由改變第三溫度及第四溫度,使基板10上氧化絕緣層15之厚度隨著熱處理之溫度上升而增厚,並且使得瞬態電壓抑制器具有高耐壓之特性,也就是使得瞬態電壓抑制器具有較高之崩潰電壓。相反地,當選用較低之熱處理溫度時,便可形成具有較低耐壓及崩潰電壓之瞬態電壓抑制器。As shown in FIG. 6, when the substrate 10 is heat-treated at a third temperature for 90 minutes in a mixed nitrogen gas, a chlorine-containing gas, and oxygen, the step S43 is performed, and the fourth temperature is heat-treated for 2 minutes in an atmosphere of mixing nitrogen and oxygen. By changing the third temperature and the fourth temperature, the thickness of the oxidized insulating layer 15 on the substrate 10 is increased as the temperature of the heat treatment rises, and the transient voltage suppressor has a high withstand voltage characteristic, that is, This allows the transient voltage suppressor to have a higher breakdown voltage. Conversely, when a lower heat treatment temperature is selected, a transient voltage suppressor having a lower withstand voltage and a breakdown voltage can be formed.

由於可以透過調整氧化絕緣層15厚度以改變瞬態電壓抑制器之崩潰電壓,因此當瞬態電壓抑制器應用於低電壓裝置時,例如:3伏特至6伏特,便可以降低瞬態電壓抑制器之崩潰電壓,並且由於當輸入電壓為崩潰電壓時具有低漏電流之特性,所以可大幅改善瞬態電壓抑制器於過渡區域之漏電流現象,並增加瞬態電壓抑制器應用於低電壓之信賴性。Since the breakdown voltage of the transient voltage suppressor can be changed by adjusting the thickness of the oxide insulating layer 15, the transient voltage suppressor can be reduced when the transient voltage suppressor is applied to a low voltage device, for example, 3 volts to 6 volts. The breakdown voltage, and because of the low leakage current when the input voltage is a breakdown voltage, can greatly improve the leakage current phenomenon of the transient voltage suppressor in the transition region, and increase the reliability of the transient voltage suppressor applied to the low voltage. Sex.

又在熱處理基板步驟S40之過程中,可藉由加入氮氣而提高氧氣之流動性,以提升熱處理過程中氧氣之置換速率,並可更均勻且快速地於基板10之溝槽14表面形成氧化絕緣層15(如第7圖所示)。Further, during the heat treatment of the substrate step S40, the fluidity of the oxygen can be increased by adding nitrogen gas to increase the oxygen exchange rate during the heat treatment, and the oxide insulation can be more uniformly and rapidly formed on the surface of the trench 14 of the substrate 10. Layer 15 (as shown in Figure 7).

而熱處理過程中所使用之含氯氣體係可以為二氯乙烯氣體、二氯甲烷氣體或鹽酸氣體,由於含氯氣體中的氯分子具有穩定電荷及提升穩定性之功效,因此可作為穩定劑之用,並可提升瞬態電壓抑制器製造方法S100中氧化絕緣層15之製程成功率。The chlorine-containing gas system used in the heat treatment process may be dichloroethylene gas, methylene chloride gas or hydrochloric acid gas, and the chlorine molecule in the chlorine-containing gas has the functions of stabilizing charge and improving stability, so it can be used as a stabilizer. And the process success rate of the oxidized insulating layer 15 in the transient voltage suppressor manufacturing method S100 can be improved.

此外,由於熱處理基板S40過程中加入了含氯氣體,因此生成之氧化絕緣層15亦含有氯分子,所以氧化絕緣層15可具有穩定電荷之功效,並且可提升氧化絕緣層15之絕緣效能。Further, since the chlorine-containing gas is added during the heat treatment of the substrate S40, the generated oxidized insulating layer 15 also contains chlorine molecules, so that the oxidized insulating layer 15 can have a function of stabilizing charges and can improve the insulating performance of the oxidized insulating layer 15.

形成一對金屬電極S50:如第8圖所示,其係對基板10進行金屬化處理,以使得一對金屬電極16分別形成於基板10之第一型深度摻雜層11及第二型深度摻雜層12的表面,並使得氧化絕緣層15裸露於金屬電極16之外,以形成瞬態電壓抑制器之電極,又金屬電極16之材質係可以為具有高導電係數之金屬,例如:金、鎳…等。Forming a pair of metal electrodes S50: as shown in FIG. 8, the substrate 10 is metallized so that a pair of metal electrodes 16 are respectively formed on the first type deep doped layer 11 of the substrate 10 and the second type depth The surface of the layer 12 is doped, and the oxidized insulating layer 15 is exposed outside the metal electrode 16 to form an electrode of the transient voltage suppressor, and the material of the metal electrode 16 may be a metal having a high conductivity, such as gold. , nickel...etc.

惟上述各實施例係用以說明本發明之特點,其目的在使熟習該技術者能瞭解本發明之內容並據以實施,而非限定本發明之專利範圍,故凡其他未脫離本發明所揭示之精神而完成之等效修飾或修改,仍應包含在以下所述之申請專利範圍中。The embodiments are described to illustrate the features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the present invention and to implement the present invention without limiting the scope of the present invention. Equivalent modifications or modifications made by the spirit of the disclosure should still be included in the scope of the claims described below.

10...基板10. . . Substrate

11...第一型深度摻雜層11. . . First type deep doped layer

12...第二型深度摻雜層12. . . Second type deep doped layer

13...第一型原始基板層13. . . First type original substrate layer

14...溝槽14. . . Trench

15...氧化絕緣層15. . . Oxidized insulating layer

16...金屬電極16. . . Metal electrode

第1圖係為曾納二極體之電壓-電流特性曲線圖。Figure 1 is a graph of the voltage-current characteristics of a Zener diode.

第2圖係為本發明之一種可改變耐壓之瞬態電壓抑制器製造方法之流程實施例圖。Fig. 2 is a flow chart showing an embodiment of a method for manufacturing a transient voltage suppressor capable of changing withstand voltage according to the present invention.

第3圖係為本發明之一種基板之剖視實施例圖。Figure 3 is a cross-sectional view showing a substrate of the present invention.

第4圖係為本發明之一種具有溝槽之基板之剖視實施例圖。Figure 4 is a cross-sectional view of a substrate having a trench of the present invention.

第5圖係為本發明之一種清洗基板步驟之流程實施例圖。Figure 5 is a flow chart showing an embodiment of a step of cleaning a substrate of the present invention.

第6圖係為本發明之一種熱處理基板步驟之流程實施例圖。Figure 6 is a flow chart showing a process of the step of heat-treating the substrate of the present invention.

第7圖係為本發明之一種具有氧化絕緣層之基板之剖視實施例圖。Figure 7 is a cross-sectional view showing a substrate having an oxidized insulating layer of the present invention.

第8圖係為本發明之一種瞬態電壓抑制器之剖視實施例圖。Figure 8 is a cross-sectional view of a transient voltage suppressor of the present invention.

S10...提供一基板S10. . . Providing a substrate

S20...圖案化基板S20. . . Patterned substrate

S30...清洗基板S30. . . Cleaning substrate

S40...熱處理基板S40. . . Heat treated substrate

S50...形成一對金屬電極S50. . . Forming a pair of metal electrodes

Claims (16)

一種可改變耐壓之瞬態電壓抑制器製造方法,其包括下列步驟:提供一基板,其具有:一對深度摻雜層,其係以驅入擴散方式形成於該基板之兩側,且該對深度摻雜層係由一第一型深度摻雜層及二第二型深度摻雜層所組成,又於該對深度摻雜層間形成一第一型原始基板層;圖案化該基板,其係蝕刻該第二型深度摻雜層及該第一型原始基板層,以穿透該第二型深度摻雜層並形成至少一溝槽於該第一型原始基板層上;清洗該基板,其包括下列步驟:浸泡該基板於一蝕刻溶液中,且該蝕刻溶液係由氫氟酸與去離子水以一第一溶液體積比例組成;使用一混合酸溶液清洗該基板,且該混合酸溶液係由硝酸、氫氟酸與醋酸溶液以一第二溶液體積比例組成;以及浸泡該基板於一王水溶液中,且該王水溶液係由硝酸、鹽酸與去離子水以一第三溶液體積比例組成;熱處理該基板,以於該溝槽表面生成一氧化絕緣層,其包括下列步驟:在一氮氣環境下以一第一溫度熱處理3分鐘;在混合該氮氣、一含氯氣體及一氧氣之環境下以一第二溫度熱處理17分鐘;在混合該氮氣、該含氯氣體及該氧氣之環境下以一第三溫度熱處理90分鐘;在混合該氮氣及該氧氣之環境下以一第四溫度熱處理2分鐘;以及在該氮氣環境下以一第五溫度熱處理10秒鐘;以及形成一對金屬電極,其係分別覆蓋於該對深度摻雜層之表面,且使該氧化絕緣層係裸露於該對金屬電極之外。A method for manufacturing a transient voltage suppressor capable of changing withstand voltage, comprising the steps of: providing a substrate having: a pair of deeply doped layers formed on both sides of the substrate by diffusion diffusion, and The deep doped layer is composed of a first type deep doped layer and two second type deep doped layers, and a first type original substrate layer is formed between the pair of deep doped layers; the substrate is patterned. Etching the second type deep doped layer and the first type original substrate layer to penetrate the second type deep doped layer and form at least one trench on the first type original substrate layer; cleaning the substrate, The method comprises the steps of: immersing the substrate in an etching solution, and the etching solution is composed of hydrofluoric acid and deionized water in a first solution volume ratio; cleaning the substrate with a mixed acid solution, and the mixed acid solution Is composed of nitric acid, hydrofluoric acid and acetic acid solution in a second solution volume ratio; and soaking the substrate in an aqueous solution of a king, and the aqueous solution of the king is composed of nitric acid, hydrochloric acid and deionized water in a third solution volume ratio ;heat The substrate is formed to form an oxidized insulating layer on the surface of the trench, comprising the steps of: heat treating at a first temperature for 3 minutes in a nitrogen atmosphere; and mixing the nitrogen gas, a chlorine gas and an oxygen gas And heat-treating at a second temperature for 17 minutes; heat-treating at a third temperature for 90 minutes in an environment where the nitrogen gas, the chlorine-containing gas and the oxygen are mixed; and heat-treating at a fourth temperature in an environment where the nitrogen gas and the oxygen are mixed; And a heat treatment at a fifth temperature for 10 seconds in the nitrogen atmosphere; and forming a pair of metal electrodes respectively covering the surfaces of the pair of deep doped layers, and exposing the oxidized insulating layer to the pair Outside the metal electrode. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第一型深度摻雜層係為一N型深度摻雜層,以及該第二型深度摻雜層係為一P型深度摻雜層,且該第一型原始基板層係為一N型原始基板層。The method for manufacturing a transient voltage suppressor according to claim 1, wherein the first type deep doped layer is an N type deep doped layer, and the second type deep doped layer is a P A deep doped layer, and the first type of original substrate layer is an N-type original substrate layer. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第一型深度摻雜層係為一P型深度摻雜層,以及該第二型深度摻雜層係為一N型深度摻雜層,且該第一型原始基板層係為一P型原始基板層。The method of fabricating a transient voltage suppressor according to claim 1, wherein the first type deep doped layer is a P type deep doped layer, and the second type deep doped layer is a N A deep doped layer, and the first type of original substrate layer is a P-type original substrate layer. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第一溶液體積比例係為1:4。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the first solution volume ratio is 1:4. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第二溶液體積比例係為12:1:6。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the second solution volume ratio is 12:1:6. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第三溶液體積比例係為2:6:16。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the third solution volume ratio is 2:6:16. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第一溫度係為800℃。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the first temperature system is 800 °C. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第二溫度係為950℃。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the second temperature system is 950 °C. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第三溫度係為1000℃-1200℃。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the third temperature system is from 1000 ° C to 1200 ° C. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第四溫度係為1000℃-1200℃。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the fourth temperature system is from 1000 ° C to 1200 ° C. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該第五溫度係為800℃。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the fifth temperature system is 800 °C. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該含氯氣體係為二氯乙烯氣體。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the chlorine-containing gas system is a dichloroethylene gas. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該含氯氣體係為二氯甲烷氣體。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the chlorine-containing gas system is dichloromethane gas. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該含氯氣體係為鹽酸氣體。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the chlorine-containing gas system is hydrochloric acid gas. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該對金屬電極之材質係為金。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the material of the pair of metal electrodes is gold. 如申請專利範圍第1項所述之瞬態電壓抑制器製造方法,其中該對金屬電極之材質係為鎳。The method of manufacturing a transient voltage suppressor according to claim 1, wherein the material of the pair of metal electrodes is nickel.
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Publication number Priority date Publication date Assignee Title
US20020163021A1 (en) * 2001-05-04 2002-11-07 Semiconductor Components Industries Llc Low voltage transient voltage suppressor and method of making
US20020195689A1 (en) * 2001-06-21 2002-12-26 Lee Chun-Yuan Transient voltage suppressor structure
TW200416789A (en) * 2002-10-18 2004-09-01 Gen Semiconductor Inc Transient voltage suppressor having an epitaxial layer for higher avalanche voltage operation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020163021A1 (en) * 2001-05-04 2002-11-07 Semiconductor Components Industries Llc Low voltage transient voltage suppressor and method of making
US20030205762A1 (en) * 2001-05-04 2003-11-06 Robb Francine Y. Low voltage transient voltage suppressor and method of making
US20020195689A1 (en) * 2001-06-21 2002-12-26 Lee Chun-Yuan Transient voltage suppressor structure
TW200416789A (en) * 2002-10-18 2004-09-01 Gen Semiconductor Inc Transient voltage suppressor having an epitaxial layer for higher avalanche voltage operation

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