TWI398023B - A light-emitting device having a patterned surface - Google Patents

A light-emitting device having a patterned surface Download PDF

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TWI398023B
TWI398023B TW97150633A TW97150633A TWI398023B TW I398023 B TWI398023 B TW I398023B TW 97150633 A TW97150633 A TW 97150633A TW 97150633 A TW97150633 A TW 97150633A TW I398023 B TWI398023 B TW I398023B
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Taiwan
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light
unit patterns
layer
emitting element
semiconductor layer
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TW97150633A
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Chinese (zh)
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TW201025659A (en
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Chen Ou
Chiu Lin Yao
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Epistar Corp
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Priority to TW97150633A priority Critical patent/TWI398023B/en
Priority to US12/646,553 priority patent/US8633501B2/en
Publication of TW201025659A publication Critical patent/TW201025659A/en
Application granted granted Critical
Publication of TWI398023B publication Critical patent/TWI398023B/en
Priority to US14/132,819 priority patent/US9257604B2/en
Priority to US14/997,258 priority patent/US9608162B2/en
Priority to US15/428,395 priority patent/US9847451B2/en
Priority to US15/821,147 priority patent/US10181549B2/en
Priority to US16/214,667 priority patent/US10522715B2/en

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Description

一種具有圖形化表面之發光元件Light-emitting element with patterned surface

本發明係關於一具有圖形化表面之發光元件。The present invention relates to a light-emitting element having a patterned surface.

近幾年來發光二極體元件致力於亮度提昇,期能最終應用於照明領域,以發揮節能省碳之功效。亮度之提昇主要分兩部份,一為內部量子效率(Internal Quantum Efficiency; IQE)之提昇,主要透過磊晶品質的改善以增進電子電洞的結合效率;另一方面為光摘出效率(Light Extraction Efficiency; LEE)之提昇,主要著重在使發光層發出之光線能有效穿透至元件外部,降低光線被發光二極體內部結構所吸收。In recent years, the light-emitting diode components have been dedicated to the improvement of brightness, and the final application can be applied to the field of lighting to achieve energy-saving and carbon-saving effects. The improvement of brightness is mainly divided into two parts. One is the improvement of Internal Quantum Efficiency (IQE), which is mainly to improve the bonding efficiency of electron holes through the improvement of epitaxial quality; on the other hand, the light extraction efficiency (Light Extraction) Efficiency; LEE) is mainly focused on making the light emitted by the illuminating layer penetrate effectively to the outside of the component, reducing the absorption of light by the internal structure of the illuminating diode.

表面粗化技術被視為有效提昇亮度之方法之一。第7圖揭示一習知之具有表面圖案基板之發光二極體700,包含一成長基板701、一磊晶疊層、一第一電極707、以及一第二電極708。成長基板701之表面701a具有複數個梯形凹陷圖案,以增進出光取出效率。磊晶疊層包含一緩衝層702成長於成長基板701上、一非摻雜半導體層703成長於緩衝層702上、一第一摻雜型態之第一半導體層704成長於非摻雜半導體層703上、一活性層705成長於第一半導體層704上、一第二摻雜型態之第二半導體層706成長於活性層705上。第一電極707係形成於裸露之第一半導體層704上;第二電極708係形成於第二半導體層706上。由於一般基板表面701a之圖案設計其圖案寬度與圖 案間之間隔之比例約為1,故仍有大部份之表面區域平行於活性層之表面705a,自活性層705發射至該區域之光線,容易經全反射返回磊晶疊層,並被吸收轉換為熱,造成光取出效率不佳及散熱問題。除此,為了彌補平行區域所造成之光損失,通常會加深圖案深度,以改善圖案化基板之光摘出效率,但因此形成具有高深寬比(aspect ratio)之圖案化表面,造成後續磊晶成長困難,而影響元件之磊晶品質。Surface roughening technology is considered one of the ways to effectively increase brightness. FIG. 7 illustrates a conventional light-emitting diode 700 having a surface pattern substrate, including a growth substrate 701, an epitaxial laminate, a first electrode 707, and a second electrode 708. The surface 701a of the growth substrate 701 has a plurality of trapezoidal recess patterns to enhance light extraction efficiency. The epitaxial layer stack includes a buffer layer 702 grown on the growth substrate 701, an undoped semiconductor layer 703 grown on the buffer layer 702, and a first doped first semiconductor layer 704 grown on the undoped semiconductor layer. On the 703, an active layer 705 is grown on the first semiconductor layer 704, and a second doped second semiconductor layer 706 is grown on the active layer 705. The first electrode 707 is formed on the exposed first semiconductor layer 704; the second electrode 708 is formed on the second semiconductor layer 706. Due to the pattern design of the general substrate surface 701a, the pattern width and the pattern are designed. The ratio of the interval between the cases is about 1, so that most of the surface area is parallel to the surface 705a of the active layer, and the light emitted from the active layer 705 to the area is easily returned to the epitaxial stack by total reflection, and is The absorption is converted to heat, resulting in poor light extraction efficiency and heat dissipation problems. In addition, in order to compensate for the light loss caused by the parallel regions, the pattern depth is generally deepened to improve the light extraction efficiency of the patterned substrate, but thus a patterned surface having a high aspect ratio is formed, resulting in subsequent epitaxial growth. Difficulties affect the epitaxial quality of the component.

另外,一習知之表面粗化技術為以機械研磨方法造成基板表面形成隨機分佈之粗糙表面,此方法無法有效控制粗化尺寸,例如:深度或寬度;況且,於此凌亂不一之表面上成長磊晶層,容易造成磊晶層品質不佳。In addition, a conventional surface roughening technique is to form a randomly distributed rough surface on the surface of the substrate by mechanical grinding. This method cannot effectively control the roughening size, for example, depth or width. Moreover, the surface is grown on a messy surface. The epitaxial layer is liable to cause poor quality of the epitaxial layer.

本發明提供一具有圖形化表面之發光元件,能兼顧磊晶品質及光摘出效果。The invention provides a light-emitting element with a patterned surface, which can balance the epitaxial quality and the light extraction effect.

本發明之一方面在揭露一發光元件,包含一基板;一中間層形成於所述之基板上;一第一摻雜半導體層形成於所述之中間層之上,具有第一摻雜質;一第二摻雜半導體層形成於所述之第一摻雜半導體層之上,具有第二摻雜質;一活性層介於所述之第一摻雜半導體層及所述之第二摻雜半導體層之間,具有一活性層表面;以及一圖形化表面,具有複數個規則排列之單元圖案;其中,所述之圖形化表面與所述之活性層表面之相對應區域實質上互不平行。An aspect of the invention discloses a light-emitting element comprising a substrate; an intermediate layer formed on the substrate; a first doped semiconductor layer formed on the intermediate layer, having a first dopant; a second doped semiconductor layer is formed on the first doped semiconductor layer and has a second doping; an active layer is interposed between the first doped semiconductor layer and the second doping Between the semiconductor layers, having an active layer surface; and a patterned surface having a plurality of regularly arranged unit patterns; wherein the corresponding areas of the patterned surface and the surface of the active layer are substantially non-parallel to each other .

本發明之另一方面在揭露一發光元件,包含一基板; 一中間層形成於所述之基板上;一第一摻雜半導體層形成於所述之中間層之上,具有第一摻雜質;一第二摻雜半導體層形成於所述之第一摻雜半導體層之上,具有第二摻雜質;一活性層介於所述之第一摻雜半導體層及所述之第二摻雜半導體層之間,具有一活性層表面;以及一圖形化表面,具有複數個規則排列之單元圖案;其中,所述之複數個規則性排列之單元圖案呈緊密排列,使得各所述之複數個單元圖案與相鄰之單元圖案相互接觸。Another aspect of the invention discloses a light emitting device comprising a substrate; An intermediate layer is formed on the substrate; a first doped semiconductor layer is formed on the intermediate layer and has a first doping; and a second doped semiconductor layer is formed on the first doped a second doping material on the hetero semiconductor layer; an active layer interposed between the first doped semiconductor layer and the second doped semiconductor layer, having an active layer surface; and a pattern The surface has a plurality of regularly arranged unit patterns; wherein the plurality of regularly arranged unit patterns are closely arranged such that each of the plurality of unit patterns and the adjacent unit patterns are in contact with each other.

第1圖揭示一符合本發明之發光元件100,包含一成長基板101、一中間層包含一晶格緩衝層102及/或一非摻雜半導體層103磊晶形成於成長基板101上、一具有第一摻雜質之第一接觸層104磊晶形成於非摻雜半導體層103上、一具有第一摻雜質之第一束縛層105磊晶形成於第一接觸層104上、一活性層106磊晶形成於第一束縛層105上、一具有第二摻雜質之第二束縛層107磊晶形成於活性層106上、一具有第二摻雜質之第二接觸層108磊晶形成於第二束縛層107上、一電流分散層109形成於第二接觸層108上,並與第二接觸層108形成良好之歐姆接觸、一第一電極110蒸鍍或濺鍍形成於裸露之第一接觸層104上、以及一第二電極111蒸鍍或濺鍍形成於電流分散層109上。其中,成長基板101具有一圖形化表面101a,且圖形化表面101a包含複數個週期性排列之單元圖案,此複數個週期性排列之單元圖案呈最緊密排列,例如,各複數個單元圖案與相鄰之單元圖案彼此相互接觸。於本實施例 中,任一部份之圖形化表面101a,例如A1區域所示,與對應之活性層上表面106a部份,例如A2區域所示,實質上互不平行。此複數個週期性排列之單元圖案呈一固定週期排列,或亦可呈變週期、或準週期排列。複數個單元圖案之上視圖形包含一多邊形,例如為至少一種圖形選自於三角形、四邊形、以及六角形所組成之群組。此複數個單元圖案之剖面圖形包含至少一種圖形選自於V形、半圓形、弧形、以及多邊形所組成之群組。於一實施例中,此複數個單元圖案之剖面圖形具有一寬度以及一深度,其中深度小於寬度,使得後續成長之晶格緩衝層102及/或非摻雜半導體層103易於填入圖形化表面101a之凹陷區域。1 shows a light-emitting device 100 according to the present invention, comprising a growth substrate 101, an intermediate layer comprising a lattice buffer layer 102 and/or an undoped semiconductor layer 103 epitaxially formed on the growth substrate 101, The first doped first contact layer 104 is epitaxially formed on the undoped semiconductor layer 103, and a first doped layer 105 having a first doping layer is epitaxially formed on the first contact layer 104, an active layer 106 epitaxially formed on the first tie layer 105, a second tie layer 107 having a second dopant is epitaxially formed on the active layer 106, and a second contact layer 108 having a second dopant is epitaxially formed. On the second tie layer 107, a current dispersion layer 109 is formed on the second contact layer 108, and forms a good ohmic contact with the second contact layer 108, and a first electrode 110 is evaporated or sputtered to form a bare electrode. A contact layer 104 and a second electrode 111 are formed by vapor deposition or sputtering on the current dispersion layer 109. The growth substrate 101 has a patterned surface 101a, and the patterned surface 101a includes a plurality of periodically arranged unit patterns. The plurality of periodically arranged unit patterns are arranged closely, for example, a plurality of unit patterns and phases. The adjacent unit patterns are in contact with each other. In this embodiment The patterned surface 101a of any portion, as shown, for example, in the A1 region, is substantially non-parallel to the portion of the corresponding active layer upper surface 106a, such as the A2 region. The plurality of periodically arranged unit patterns are arranged in a fixed period, or may be arranged in a variable period or a quasi-period. The top view of the plurality of unit patterns includes a polygon, for example, a group of at least one pattern selected from the group consisting of a triangle, a quadrangle, and a hexagon. The cross-sectional pattern of the plurality of unit patterns includes at least one pattern selected from the group consisting of a V shape, a semicircle, an arc, and a polygon. In one embodiment, the cross-sectional pattern of the plurality of unit patterns has a width and a depth, wherein the depth is less than the width, so that the subsequently grown lattice buffer layer 102 and/or the undoped semiconductor layer 103 are easily filled into the patterned surface. The recessed area of 101a.

第2圖揭示一符合本發明之發光元件200,與第1圖之發光元件100相較,發光元件200之圖形化表面101b之剖面圖案具有複數個週期性排列之單元圖案,各單元圖案具有圓弧之剖面曲線,可進一步助於後續晶格緩衝層102及非摻雜半導體層103填入於圖形化表面101b之凹陷區域。關於形成圓弧之剖面曲線之方法,可於一平面基板表面先形成光阻罩幕層後,以微影製程將光阻罩幕層圖形化,之後置於烘烤設備中,於一適當溫度烘烤下,使光阻再流動(reflow)形成具有圓弧曲線之剖面圖案之罩幕層,再施以溼蝕刻或乾蝕刻,使光阻圖案轉移至基板101以形成如第2圖之具有圓弧剖面曲線之圖形化表面101b。其中,複數個單元圖案之上視圖形包含多邊形,例如為至少一種圖形選自於三角形、四邊形、以及六角形所組成之群組。2 shows a light-emitting element 200 according to the present invention. Compared with the light-emitting element 100 of FIG. 1, the cross-sectional pattern of the patterned surface 101b of the light-emitting element 200 has a plurality of periodically arranged unit patterns, and each unit pattern has a circle. The cross-sectional curve of the arc can further assist the subsequent lattice buffer layer 102 and the non-doped semiconductor layer 103 to be filled in the recessed region of the patterned surface 101b. The method for forming a profile curve of a circular arc can form a photoresist mask layer on a surface of a planar substrate, and then pattern the photoresist mask layer by a lithography process, and then place it in a baking device at a suitable temperature. Under baking, the photoresist is reflowed to form a mask layer having a cross-sectional pattern of a circular arc curve, and then wet etching or dry etching is applied to transfer the photoresist pattern to the substrate 101 to form a pattern as shown in FIG. The patterned surface 101b of the arc profile curve. The top view of the plurality of unit patterns includes a polygon, for example, a group of at least one selected from the group consisting of a triangle, a quadrangle, and a hexagon.

第3圖揭示一符合本發明之發光元件300,與第2圖 之發光元件200相較,發光元件300之圖形化表面101c具有不同尺寸或不同圖形之單元圖案作週期性排列,其上視圖形包含相異之多邊形,例如為相異之圖形選自於三角形、四邊形、以及六角形所組成之群組。Figure 3 discloses a light-emitting element 300 in accordance with the present invention, and Figure 2 Compared with the light-emitting element 200, the patterned surface 101c of the light-emitting element 300 has a unit pattern of different sizes or different patterns for periodic arrangement, and the upper view shape includes different polygons, for example, the different patterns are selected from triangles, A group of quadrilaterals and hexagons.

第4圖揭示一符合本發明之發光元件400,與第2圖之發光元件200相較,發光元件400之第二接觸層108之上表面108a亦具有一如上述實施例所揭示之圖形化表面,以進一步增加光摘出效率,其中任一部份之第二接觸層108之上表面108a與對應之活性層上表面106a實質上互不平行。第二接觸層108之上表面108a形成之方法,可於磊晶成長第二接觸層108時,藉由磊晶參數之調整,例如降低成長溫度、或調變反應器中氫氣/氮氣濃度比例等方式,以自然成長出內六角錐狀凹陷;亦可於第二接觸層108形成後,以傳統之微影蝕刻製程形成具有凸起及/或凹陷之圖形化表面108a。後續之電流分散層109係順應地形成於圖形化凹凸表面108a上並形成良好之歐姆接觸。4 shows a light-emitting element 400 according to the present invention. Compared with the light-emitting element 200 of FIG. 2, the upper surface 108a of the second contact layer 108 of the light-emitting element 400 also has a patterned surface as disclosed in the above embodiment. To further increase the light extraction efficiency, any portion of the second contact layer 108 upper surface 108a and the corresponding active layer upper surface 106a are substantially non-parallel to each other. The upper surface 108a of the second contact layer 108 is formed by adjusting the epitaxial parameters, such as lowering the growth temperature or adjusting the hydrogen/nitrogen concentration ratio in the reactor, when the second contact layer 108 is epitaxially grown. In a manner, the hexagonal pyramidal recess is naturally grown; after the second contact layer 108 is formed, the patterned surface 108a having protrusions and/or depressions is formed by a conventional lithography process. Subsequent current spreading layer 109 is conformally formed on patterned relief surface 108a and forms a good ohmic contact.

第5圖揭示一符合本發明之發光元件500,與第2圖之發光元件200相較,發光元件500之中間層502係為一接合(bonding)層,例如為一透明黏著層或透明氧化層,並利用接合技術,如直接接合或熱壓接合,以連接第一接觸層104及一第二基板501。依本實施例之精神,第二基板501並不限於可供成長磊晶層之材質,可依目的彈性選擇所需之材質,例如高導熱性之材質、高透光率之透明材質、導電材質、或具光反射之材質。Fig. 5 shows a light-emitting element 500 according to the present invention. Compared with the light-emitting element 200 of Fig. 2, the intermediate layer 502 of the light-emitting element 500 is a bonding layer, such as a transparent adhesive layer or a transparent oxide layer. And bonding technology, such as direct bonding or thermocompression bonding, to connect the first contact layer 104 and a second substrate 501. According to the spirit of the embodiment, the second substrate 501 is not limited to a material for growing the epitaxial layer, and the desired material can be selected according to the purpose, such as a material with high thermal conductivity, a transparent material with high transmittance, and a conductive material. Or a material with light reflection.

第6A圖至第6D圖為上述各實施例所述之圖形化表面 之上視圖。如第6A圖所示,上述之圖形化表面係由六角形之單元圖案所組成,各單元圖案係由六個內凹或凸出於基板表面之內斜面601a所組成,此些內斜面共同相接於一中心點601c,並且各單元圖案彼此相接於六個鄰邊601b,使得所述之圖形化表面實質上不具有與對應之活性層上表面106a平行之表面。如第6B圖所示,上述之圖形化表面亦可由三角形之單元圖案所組成,各單元圖案係由三個內凹或凸出於基板表面之內斜面602a所組成,此些內斜面共同相接於一中心點602c,並且各單元圖案彼此相接於三個鄰邊602b,使得所述之圖形化表面實質上不具有與對應之活性層上表面106a平行之表面。如第6C圖所示,上述之圖形化表面亦可由菱形之單元圖案所組成,各單元圖案係由四個內凹或凸出之內斜面603a所組成,此些內斜面共同相接於一中心點603c,並且各單元圖案彼此相接於四個鄰邊603b,使得所述之圖形化表面實質上不具有與對應之活性層上表面106a平行之表面。如第6D圖所示,上述之圖形化表面亦可由重疊之圓形所定義出方形之單元圖案所組成,各單元圖案係由四個凸出之外斜面604a及一圓弧頂面604c所組成,各單元圖案彼此相接於四個鄰邊604b,使得所述之圖形化表面實質上不具有與對應之活性層上表面106a平行之表面。其中,以上之各實施例所指之“圖形化表面實質上不具有與對應之活性層表面平行之表面”,在此並不排除因製程變異,如微影造成光阻圖案的變化或蝕刻造成之圖形變異等,造成部份圖形化區域仍具有平行之表面或部份區域未被圖形化而具有平 行之表面,例如中心點601c、602c、603c或圓頂面604c於製程變異範圍內仍可能形成一小平臺,但製程變異在可控制之範圍內,所造成之平行表面及未被圖形化表面其總面積不超過總基板表面之3%。又如第6E圖所示,上述之圖形化表面亦可由圓形之單元圖案所組成,各該單元圖案為一內凹或凸出之圓弧面或半球面,各單元圖案彼此相接呈最緊密排列,使得所述之圖形化表面與對應之活性層上表面106a平行之部份佔圖形化表面之比值約為如圖中之三角形面積扣除三個扇形面積所得之值除以三角形面積,約為9.3%,或不超過於10%。6A to 6D are the patterned surfaces described in the above embodiments Above view. As shown in FIG. 6A, the above-mentioned patterned surface is composed of hexagonal unit patterns, and each unit pattern is composed of six concave or convex inner surfaces 601a protruding from the surface of the substrate, and the inner inclined surfaces are common. Connected to a center point 601c, and each unit pattern is adjacent to each other to six adjacent sides 601b such that the patterned surface does not substantially have a surface parallel to the corresponding active layer upper surface 106a. As shown in FIG. 6B, the patterned surface may also be composed of a triangular unit pattern, and each unit pattern is composed of three concave or convex inner surfaces 602a protruding from the surface of the substrate, and the inner inclined surfaces are connected together. At a center point 602c, and the unit patterns are connected to each other at three adjacent sides 602b such that the patterned surface does not substantially have a surface parallel to the corresponding active layer upper surface 106a. As shown in FIG. 6C, the patterned surface may also be composed of a diamond-shaped unit pattern, and each unit pattern is composed of four concave or convex inner inclined surfaces 603a, and the inner inclined surfaces are commonly connected to a center. Point 603c, and the unit patterns are connected to each other at four adjacent sides 603b such that the patterned surface does not substantially have a surface parallel to the corresponding active layer upper surface 106a. As shown in FIG. 6D, the above-mentioned patterned surface may also be composed of a square unit pattern defined by overlapping circles, and each unit pattern is composed of four convex outer inclined surfaces 604a and one circular arc top surface 604c. The unit patterns are connected to each other at four adjacent sides 604b such that the patterned surface does not substantially have a surface parallel to the corresponding active layer upper surface 106a. In the above embodiments, the “patterned surface does not substantially have a surface parallel to the surface of the corresponding active layer”, and variations or etchings of the photoresist pattern caused by process variations such as lithography are not excluded herein. Graphical variations, etc., causing some of the patterned areas to still have parallel surfaces or portions of the area that are not graphically flat The surface of the row, such as the center point 601c, 602c, 603c or the dome surface 604c, may still form a small platform within the range of process variation, but the process variation is within a controllable range, resulting in parallel surfaces and unpatterned surfaces Its total area does not exceed 3% of the total substrate surface. As shown in FIG. 6E, the patterned surface may also be composed of a circular unit pattern, and each of the unit patterns is a concave or convex arc surface or a hemispherical surface, and each unit pattern is connected to each other. Tightly arranged such that the ratio of the portion of the patterned surface parallel to the upper surface 106a of the corresponding active layer to the patterned surface is approximately the value obtained by subtracting three sector areas from the triangular area in the figure divided by the area of the triangle. It is 9.3%, or no more than 10%.

基於上述各實施例所揭露之單元圖案,由於具有較大程度之圖案化比例,相對提高後續成長之所述之晶格緩衝層及所述之非摻雜半導體層之磊晶成長難度,為能兼顧光摘出效率及內部量子效率,上述單元圖案之剖面圖形具有一寬度以及一深度,其中深度小於寬度,或其深度/寬度之比值小於1,以形成一具有低深寬比之單元圖案,使得後續成長之所述之晶格緩衝層及/或所述之非摻雜半導體層易於填入圖形化表面之凹陷區域,以提昇磊晶成長之品質。The unit pattern disclosed in the above embodiments is capable of relatively increasing the epitaxial growth difficulty of the lattice buffer layer and the non-doped semiconductor layer of the subsequent growth due to a large degree of patterning ratio. Considering the light extraction efficiency and the internal quantum efficiency, the cross-sectional pattern of the unit pattern has a width and a depth, wherein the depth is smaller than the width, or a ratio of depth/width thereof is less than 1, to form a unit pattern having a low aspect ratio, so that The subsequently grown lattice buffer layer and/or the undoped semiconductor layer are easily filled into the recessed regions of the patterned surface to enhance the quality of epitaxial growth.

基於上述各實施例所揭露之圖形化表面並不限於形成特定結構上之圖形化表面,亦即,形成於任一結構上之符合本發明所述之圖形化表面均屬本發明之範圍,例如,圖形化表面亦可為發光元件與封裝材質相接觸之一出光面或與環境接觸之一接觸表面;於一實施例中,與圖形化表面相鄰之材質,包含但不限於發光元件內之任一結構、 封裝材質、或環境介質,具有相異之折射率,較佳地,折射率差異至少0.1以上。The patterned surface disclosed in the above embodiments is not limited to forming a patterned surface on a specific structure, that is, a patterned surface conforming to the present invention formed on any of the structures is within the scope of the present invention, for example The patterned surface may also be a light-emitting element in contact with one of the light-emitting surface or the environment contact surface; in one embodiment, the material adjacent to the patterned surface includes, but is not limited to, a light-emitting element. Any structure, The encapsulating material or the environmental medium has a different refractive index, and preferably has a refractive index difference of at least 0.1 or more.

上述之諸實施例,其中,所述之晶格緩衝層、非摻雜第一接觸層、第一束縛層、第二束縛層、第二接觸層、以及活性層之材料係包含III-V族化合物,例如Alp Gaq In(1-p-q) P或Alx Iny Ga(1-x-y) N,其中,0p, q1;p、q、x、y均為正數;(p+q)1; (x+y)1。所述之第一摻雜質為n型摻雜質,例如Si,或者是p型摻雜質,例如Mg或Zn;所述之第二摻雜質為具有與第一摻雜質相異導電型之摻雜質。所述之電流分散層包含金屬導電氧化物,例如為氧化銦錫(ITO)、或導電性良好之半導體層,例如具有高摻雜濃度之磷化物或氮化物。所述之成長基板包括至少一種透明材料選自於磷化鎵、藍寶石、碳化矽、氮化鎵、以及氮化鋁所組成之群組。所述之第二基板包括透明材料選自於磷化鎵、藍寶石、碳化矽、氮化鎵、以及氮化鋁所組成之群組;或包括導熱材料選自於鑽石、類鑽碳(DLC)、氧化鋅、金、銀、鋁等金屬材質所組成之群組。In the above embodiments, the material of the lattice buffer layer, the undoped first contact layer, the first tie layer, the second tie layer, the second contact layer, and the active layer comprises a III-V group. a compound such as Al p Ga q In (1-pq) P or Al x In y Ga (1-xy) N, wherein, 0 p, q 1; p, q, x, y are positive numbers; (p+q) 1; (x+y) 1. The first dopant is an n-type dopant, such as Si, or a p-type dopant, such as Mg or Zn; and the second dopant has a conductivity different from that of the first dopant. Type of doping. The current dispersion layer comprises a metal conductive oxide, such as indium tin oxide (ITO), or a semiconductor layer having good conductivity, such as a phosphide or nitride having a high doping concentration. The growth substrate comprises at least one transparent material selected from the group consisting of gallium phosphide, sapphire, tantalum carbide, gallium nitride, and aluminum nitride. The second substrate comprises a transparent material selected from the group consisting of gallium phosphide, sapphire, tantalum carbide, gallium nitride, and aluminum nitride; or the heat conductive material is selected from the group consisting of diamond and diamond-like carbon (DLC). A group of metal materials such as zinc oxide, gold, silver, and aluminum.

本發明所列舉之各實施例僅用以說明本發明,並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。The examples of the invention are intended to be illustrative only and not to limit the scope of the invention. Any changes or modifications of the present invention to those skilled in the art will be made without departing from the spirit and scope of the invention.

100、200、300、400、500‧‧‧發光元件100, 200, 300, 400, 500‧‧‧Lighting elements

101‧‧‧成長基板101‧‧‧ Growth substrate

101a、101b、101c、101d‧‧‧圖形化表面101a, 101b, 101c, 101d‧‧‧ graphical surface

102‧‧‧晶格緩衝層102‧‧‧ lattice buffer layer

103‧‧‧非摻雜半導體層103‧‧‧Undoped semiconductor layer

104‧‧‧第一接觸層104‧‧‧First contact layer

105‧‧‧第一束縛層105‧‧‧First tie layer

106‧‧‧活性層106‧‧‧Active layer

106a‧‧‧活性層上表面106a‧‧‧ Upper surface of the active layer

107‧‧‧第二束縛層107‧‧‧Second tie layer

108‧‧‧第二接觸層108‧‧‧Second contact layer

108a‧‧‧第二接觸層上表面108a‧‧‧Second contact layer upper surface

109‧‧‧電流傳導層109‧‧‧current conduction layer

110‧‧‧第一電極110‧‧‧First electrode

111‧‧‧第二電極111‧‧‧second electrode

112‧‧‧透明黏著層112‧‧‧Transparent adhesive layer

501‧‧‧第二基板501‧‧‧second substrate

502‧‧‧中間層502‧‧‧Intermediate

601a、602a、603a、604a‧‧‧內斜面601a, 602a, 603a, 604a‧‧‧ inner slope

601b、602b、603b、604b‧‧‧鄰邊601b, 602b, 603b, 604b‧‧‧ adjacent

601c、602c、603c‧‧‧中心點601c, 602c, 603c‧‧‧ center point

604c‧‧‧圓頂面604c‧‧‧Dome face

第1圖為一示意圖,顯示依本發明發光元件之第一實施例;第2圖為一示意圖,顯示依本發明發光元件之第二實施例;第3圖為一示意圖,顯示依本發明發光元件之第三實施例;第4圖為一示意圖,顯示依本發明發光元件之第四實施例; 第5圖為一示意圖,顯示依本發明發光元件之第五實施例;第6A圖至第6E圖為示意圖,顯示依本發明之圖形化基板之上視圖;第7圖為一示意圖,顯示先前技藝之發光元件結構。1 is a schematic view showing a first embodiment of a light-emitting element according to the present invention; FIG. 2 is a schematic view showing a second embodiment of a light-emitting element according to the present invention; and FIG. 3 is a schematic view showing light-emitting according to the present invention. a third embodiment of the component; FIG. 4 is a schematic view showing a fourth embodiment of the light-emitting component according to the present invention; 5 is a schematic view showing a fifth embodiment of a light-emitting element according to the present invention; FIGS. 6A to 6E are schematic views showing a top view of a patterned substrate according to the present invention; and FIG. 7 is a schematic view showing a front view The structure of the light-emitting elements of the art.

100‧‧‧發光元件100‧‧‧Lighting elements

101‧‧‧成長基板101‧‧‧ Growth substrate

101a‧‧‧圖形化表面101a‧‧‧Graphic surface

102‧‧‧晶格緩衝層102‧‧‧ lattice buffer layer

103‧‧‧非摻雜磊晶層103‧‧‧Undoped epitaxial layer

104‧‧‧第一接觸層104‧‧‧First contact layer

105‧‧‧第一束縛層105‧‧‧First tie layer

106‧‧‧活性層106‧‧‧Active layer

106a‧‧‧活性層上表面106a‧‧‧ Upper surface of the active layer

107‧‧‧第二束縛層107‧‧‧Second tie layer

108‧‧‧第二接觸層108‧‧‧Second contact layer

109‧‧‧電流傳導層109‧‧‧current conduction layer

110‧‧‧第一電極110‧‧‧First electrode

111‧‧‧第二電極111‧‧‧second electrode

Claims (21)

一種發光元件,包含:一基板,具有一圖形化表面,該圖形化表面具有複數個單元圖案;一中間層形成於該基板上;一第一摻雜半導體層形成於該中間層之上,具有第一摻雜質;一第二摻雜半導體層形成於該第一摻雜半導體層之上,具有第二摻雜質;以及一活性層介於該第一摻雜半導體層及該第二摻雜半導體層之間,具有一谷性層表面;;其中,任一部份之該圖形化表面與對應之該活性層表面部份實質上互不平行;以及其中,該中間層至少包含一晶格緩衝層、一非摻雜半導體層或一接合層。 A light-emitting element comprising: a substrate having a patterned surface, the patterned surface having a plurality of unit patterns; an intermediate layer formed on the substrate; a first doped semiconductor layer formed on the intermediate layer, having a first doped material; a second doped semiconductor layer formed on the first doped semiconductor layer, having a second doping; and an active layer interposed between the first doped semiconductor layer and the second doped Between the hetero-semiconductor layers, having a gluten layer surface; wherein the patterned surface of any portion is substantially non-parallel to the corresponding surface portion of the active layer; and wherein the intermediate layer comprises at least one crystal a buffer layer, an undoped semiconductor layer or a bonding layer. 如申請專利範圍第1項所述之發光元件,其中該複數個單元圖案呈一固定週期、變週期、或準週期排列。 The light-emitting element of claim 1, wherein the plurality of unit patterns are arranged in a fixed period, a variable period, or a quasi-period. 如申請專利範圍第1項所述之發光元件,其中該複數個單元圖案之上視圖形包含一多邊形。 The illuminating element of claim 1, wherein the plurality of unit patterns comprise a polygon in a top view. 如申請專利範圍第3項所述之發光元件,其中該複數個單元圖案之上視圖形包含至少一種圖形選自 於三角形、方形、以及六角形所組成之群組。 The illuminating element of claim 3, wherein the plurality of unit patterns have a top view comprising at least one graphic selected from the group consisting of A group of triangles, squares, and hexagons. 如申請專利範圍第1項所述之發光元件,其中該複數個單元圖案之剖面圖形包含至少一種圖形選自於V形、半圓形、弧形、以及多邊形所組成之群組。 The light-emitting element of claim 1, wherein the cross-sectional pattern of the plurality of unit patterns comprises at least one pattern selected from the group consisting of a V shape, a semicircle, an arc shape, and a polygon. 如申請專利範圍第1項所述之發光元件,其中該複數個單元圖案之至少一個之剖面圖形具有一寬度以及一深度小於該寬度。 The light-emitting element according to claim 1, wherein the cross-sectional pattern of at least one of the plurality of unit patterns has a width and a depth smaller than the width. 如申請專利範圍第1項所述之發光元件,其中該複數個單元圖案之剖面圖形包含至少二種不同曲率之弧線。 The illuminating element of claim 1, wherein the cross-sectional pattern of the plurality of unit patterns comprises at least two arcs of different curvatures. 如申請專利範圍第1項所述之發光元件,其中該活性層表面實質上為一平面。 The light-emitting element of claim 1, wherein the surface of the active layer is substantially a plane. 如申請專利範圍第1項所述之發光元件,其中該第二摻雜半導體層之外表面具有一多孔穴結構。 The light-emitting element of claim 1, wherein the outer surface of the second doped semiconductor layer has a porous hole structure. 一種發光元件,包含:一基板,具有一圖形化表面,該圖形化表面具有複數個單元圖案;一中間層形成於該基板上;一第一摻雜半導體層形成於該中間層之上,具有第一摻雜質;一第二摻雜半導體層形成於該第一摻雜半導體層之上,具有第二摻雜質;以及 一活性層介於該第一摻雜半導體層及該第二摻雜半導體層之間,具有一活性層表面;其中,該複數個單元圖案呈最緊密排列,使得各該複數個單元圖案與相鄰之單元圖案相互接觸;以及其中,該中間層至少包含一晶格緩衝層、一非摻雜半導體層或一接合層。 A light-emitting element comprising: a substrate having a patterned surface, the patterned surface having a plurality of unit patterns; an intermediate layer formed on the substrate; a first doped semiconductor layer formed on the intermediate layer, having a first doping; a second doped semiconductor layer formed on the first doped semiconductor layer, having a second dopant; An active layer is interposed between the first doped semiconductor layer and the second doped semiconductor layer, and has an active layer surface; wherein the plurality of unit patterns are arranged in a tightest arrangement such that each of the plurality of unit patterns and phases The adjacent unit patterns are in contact with each other; and wherein the intermediate layer includes at least one lattice buffer layer, an undoped semiconductor layer or a bonding layer. 如申請專利範圍第10項所述之發光元件,其中任一部份之該圖形化表面與對應之該活性層表面部份實質上互不平行。 The illuminating element according to claim 10, wherein the patterned surface of any one of the portions is substantially non-parallel to the corresponding surface portion of the active layer. 如申請專利範圍第10項所述之發光元件,其中該複數個單元圖案呈一固定週期、變週期、或準週期排列。 The light-emitting element of claim 10, wherein the plurality of unit patterns are arranged in a fixed period, a variable period, or a quasi-period. 如申請專利範圍第10項所述之發光元件,其中該複數個單元圖案之上視圖形包含一多邊形。 The illuminating element of claim 10, wherein the plurality of unit patterns comprise a polygon in a top view. 如申請專利範圍第13項所述之發光元件,其中該複數個單元圖案之上視圖形包含至少一種圖形選自於三角形、四邊形、以及六角形所組成之群組。 The light-emitting element of claim 13, wherein the plurality of unit patterns have an at least one pattern selected from the group consisting of a triangle, a quadrangle, and a hexagon. 如申請專利範圍第10項所述之發光元件,其中該複數個單元圖案之剖面圖形包含至少一種圖形選自於V形、半圓形、弧形、以及多邊形所組成之群組。 The light-emitting element according to claim 10, wherein the cross-sectional pattern of the plurality of unit patterns comprises at least one pattern selected from the group consisting of a V shape, a semicircle, an arc shape, and a polygon. 如申請專利範圍第10項所述之發光元件,其中該複 數個單元圖案之至少一個之剖面圖形具有一寬度以及一深度小於該寬度。 The illuminating element according to claim 10, wherein the complex The cross-sectional pattern of at least one of the plurality of unit patterns has a width and a depth less than the width. 如申請專利範圍第10項所述之發光元件,其中該複數個單元圖案之剖面圖形包含至少二種不同曲率之弧線。 The illuminating element of claim 10, wherein the cross-sectional pattern of the plurality of unit patterns comprises at least two arcs of different curvatures. 如申請專利範圍第10項所述之發光元件,其中該活性層表面為一平面。 The light-emitting element according to claim 10, wherein the surface of the active layer is a flat surface. 如申請專利範圍第10項所述之發光元件,其中該第二摻雜半導體層之外表面具有一多孔穴結構。 The light-emitting element according to claim 10, wherein the outer surface of the second doped semiconductor layer has a porous hole structure. 如申請專利範圍第10項所述之發光元件,其中該複數個單元圖案之上視圖形包含圓形。 The light-emitting element according to claim 10, wherein the plurality of unit patterns have a circular shape in a top view. 如申請專利範圍第20項所述之發光元件,部份之該圖形化表面平行於對應之該活性層表面部份不大於百分之十之該圖形化表面。 The illuminating element of claim 20, wherein the patterned surface is parallel to the patterned surface of the corresponding surface portion of the active layer by no more than ten percent.
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US14/132,819 US9257604B2 (en) 2008-08-12 2013-12-18 Light-emitting device having a patterned surface
US14/997,258 US9608162B2 (en) 2008-08-12 2016-01-15 Light-emitting device having a patterned surface
US15/428,395 US9847451B2 (en) 2008-08-12 2017-02-09 Light-emitting device having a patterned surface
US15/821,147 US10181549B2 (en) 2008-08-12 2017-11-22 Light-emitting device having a patterned surface
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CN109004075B (en) * 2017-06-06 2020-02-07 清华大学 Light emitting diode

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