TWI397983B - 封裝載板與接合結構 - Google Patents

封裝載板與接合結構 Download PDF

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Publication number
TWI397983B
TWI397983B TW097151845A TW97151845A TWI397983B TW I397983 B TWI397983 B TW I397983B TW 097151845 A TW097151845 A TW 097151845A TW 97151845 A TW97151845 A TW 97151845A TW I397983 B TWI397983 B TW I397983B
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Taiwan
Prior art keywords
conductive pattern
conductive
metal layer
bottom metal
pad
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Application number
TW097151845A
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English (en)
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TW201025540A (en
Inventor
Tsung Fu Tsai
Chau Jie Zhan
Jing Yao Chang
Tao Chih Chang
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Ind Tech Res Inst
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Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW097151845A priority Critical patent/TWI397983B/zh
Priority to US12/483,261 priority patent/US8130509B2/en
Publication of TW201025540A publication Critical patent/TW201025540A/zh
Priority to US13/363,248 priority patent/US20120125669A1/en
Application granted granted Critical
Publication of TWI397983B publication Critical patent/TWI397983B/zh

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Description

封裝載板與接合結構
本發明是有關於一種封裝載板與接合結構，且特別是有關於一種具有球底金屬層(under bump metallurgic layer,UBM layer)的封裝載板與接合結構。
隨著科技進步，各種電子產品朝向小型化、輕量、薄型、高速、高機能、高密度、低成本等多功能化的方向發展。因此，為了使電子產品中的晶片能傳輸或接收更多的訊號，電性連接於晶片與封裝載板之間的接點也朝向高密度化的方向發展。
就覆晶接合技術(flip chip bonding technology)而言，主要是利用面陣列(area array)的排列方式將晶片上多個接墊分別配置於晶片的主動表面上，並在這些接墊上分別依序形成球底金屬層及導電凸塊。之後，利用導電凸塊連接至封裝載板上的接墊，以使得晶片可經由導電凸塊而電性連接至封裝載板。由於導電凸塊是以面陣列的方式排列於晶片之主動面上，因此覆晶接合技術適於運用在高接點數及高接點密度之晶片封裝結構，例如已普遍地應用於半導體封裝產業中的覆晶/球格陣列式封裝(flip chip/ball grid array)。相較於打線接合技術，由於導電凸塊可提供晶片與封裝載板之間較短的傳輸路徑，因此覆晶接合技術可提升晶片封裝體之電性效能。
圖1是習知之一覆晶封裝體的剖面示意圖。請參考圖1，習知之覆晶封裝體(flip chip package)1包括一晶片10、一基板20、一球底金屬層30、一導電凸塊40與一封裝膠體50。晶片10具有一晶片接墊12、一連接晶片接墊12的導線結構14以及一第一保護層16，其中第一保護層16具有一開口16A以暴露出部份接墊12。球底金屬層30位於晶片接墊12與導電凸塊40之間，其中球底金屬層30是由黏著層(adhesive layer)32、阻障層(barrier layer)34以及沾錫層(wetting layer)36等複合金屬層所構成。基板20具有一基板接墊22及一第二保護層24，其中晶片接墊12與相對應的基板接墊22可經由導電凸塊40而使得晶片10與基板20電性連接。封裝膠體50位於晶片10與基板20之間，且包覆導電凸塊40。
值得注意的是，隨著構裝技術越加的精密化，導電凸塊40的尺寸也會越來越小。當晶片10之運作速度加快時，常會形成大量的電流行經球底金屬層30，並使得電流在靠近於導線結構14之區域18上造成電流擁擠(current crowing)現象。即電流在此處之密度增大，進而導致金屬原子在此處產生晶界擴散現象，即電致遷移(Electromigration)現象。而球底金屬層30之金屬原子在長時間的電流作用下會因電致遷移而流失，甚至可能會形成孔洞並造成裂縫的延伸。尤其是靠近於導線結構14之一端，其流失量將大於遠離於導線結構14的一端，進而影響覆晶封裝體1的可靠度。
本發明提供一種封裝載板，其可使電流通過接墊而進入球底金屬層時之密度能夠均勻分佈，可改善電流擁擠(current crowding)現象。
本發明提出一種封裝載板，其包括一基材、至少一球底金屬層以及至少一導電凸塊。基材具有一導電結構以及與導電結構連接的至少一接墊，其中接墊與導電結構接觸的區域為一訊號來源區。球底金屬層配置於接墊上。球底金屬層包括一第一導電圖案以及一第二導電圖案。第二導電圖案的側壁與第一導電圖案的側壁直接接觸，且第二導電圖案設置於靠近訊號來源區，其中第二導電圖案的導電率小於第一導電圖案的導電率。導電凸塊配置於球底金屬層上。
本發明提出一種封裝載板，其包括一基材、至少一球底金屬層以及至少一導電凸塊。基材具有一導電結構以及與導電結構連接的至少一接墊，其中接墊與導電結構接觸的區域為一訊號來源區。球底金屬層配置於接墊上。球底金屬層包括一導電圖案以及一柵狀導電圖案。導電圖案位於接墊的表面上。柵狀導電圖案位於導電圖案的表面上，其中柵狀導電圖案的導電率小於導電圖案的導電率，且柵狀導電圖案的一部分靠近訊號來源區。導電凸塊配置於球底金屬層上。
本發明提出一種接合結構，其包括一第一基材、至少一第一球底金屬層、一第二基材、至少一第二球底金屬層以及至少一導電凸塊。第一基材具有一第一導電結構以及與第一導電結構連接的至少一第一接墊，其中第一接墊與第一導電結構接觸的區域為一第一訊號來源區。第一球底金屬層配置於第一接墊上。第一球底金屬層包括第一導電圖案以及一第二導電圖案。第二導電圖案的側壁與第一導電圖案的側壁直接接觸，且第二導電圖案設置於靠近第一訊號來源區，其中第二導電圖案的導電率小於第一導電圖案的導電率。第二基材設置於第一基材的對向。第二基材具有一第二導電結構以及與第二導電結構連接的至少一第二接墊，其中第二接墊與第二導電結構接觸的區域為一第二訊號來源區。第二球底金屬層配置於第二接墊上。導電凸塊配置於第一球底金屬層與第二球底金屬層之間。
本發明提出一種封裝載板，其包括一基材、至少一球底金屬層以及至少一導電凸塊。基材具有一導電結構以及與導電結構連接的至少一接墊，其中接墊與導電結構接觸的區域為一訊號來源區。球底金屬層配置於接墊上，且球底金屬層包括一第一導電圖案、一第二導電圖案以及一第三導電圖案。第一導電圖案位於接墊的表面上。第二導電圖案位於第一導電圖案的表面上。第三導電圖案位於第一導電圖案的表面上，其中第三導電圖案的導電率大於第一導電圖案的導電率，第一導電圖案的導電率大於第二導電圖案的導電率，且第二導電圖案相較於第三導電圖案較靠近訊號來源區。導電凸塊配置於球底金屬層上。
基於上述，由於本發明之球底金屬層具有兩種不同導電率之第一導電圖案與第二導電圖案，且低導電率之第二導電圖案設置於靠近訊號來源區，因此當來自訊號來源區的電流通過接墊而進入球底金屬層時，電流的密度能夠均勻分佈於球底金屬層中。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖2A為本發明之一實施例之一種封裝載板的剖面示意圖，圖2B為圖2A之球底金屬層的上視圖。請同時參考圖2A與圖2B，在本實施例中，封裝載板100A包括一基材110、至少一球底金屬層120A以及至少一導電凸塊130。
詳細而言，基材110具有一導電結構112以及與導電結構112連接的至少一接墊114，其中接墊114與導電結構112接觸的區域為一訊號來源區116。在本實施例中，導電結構112與接墊114是屬於同一膜層，其例如是導線結構。在其他的實施例中，導電結構112可以是位於基材110內部的導電結構，其例如是內連線結構或是內部導線結構。
在本實施例中，基材110上更包括一保護層140，其中保護層140具有一開口142，且開口142暴露出部份接墊114。在本實施例中，基材110例如為一晶片或一電路板。在此必須說明的是，於其他實施例中，基材110亦可以沒有保護層140，也就是說，圖2A所繪示之基材110僅為舉例說明，本發明並不以此為限。
球底金屬層120A配置於接墊114上，其中球底金屬層120A一部份是位於保護層140之開口142所暴露出的接墊114上，球底金屬層120A之另一部份是位於接墊114上方的保護層140上。球底金屬層120A包括一第一導電圖案122A以及一第二導電圖案124A。第二導電圖案124A的側壁與第一導電圖案122A的側壁直接接觸，且第二導電圖案124A設置於靠近訊號來源區116，其中第一導電圖案122A與第二導電圖案124A皆為單層結構，第二導電圖案124A的導電率小於第一導電圖案122A的導電率。當然，於其他實施例中，第一導電圖案122A與第二導電圖案124A亦可皆為多層結構。另外，第二導電圖案124A的面積佔整體球底金屬層120A的面積的5%至60%。
特別是，在本實施例中，第一導電圖案122A的一側壁與第二導電圖案124A的一側壁直接接觸，且第一導電圖案122A的上表面與第二導電圖案124A的上表面共平面，其中第一導電圖案122A的材質例如是銅(Cu)，第二導電圖案124A的材質例如是鎳(Ni)。當然，本發明並不限定第一導電圖案122A與第二導電圖案124A的材質，其皆可分別選自銅、銀(Ag)、鎳、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)、銦(In)、錫(Sn)以及上述任一金屬的合金，只要所選擇之第一導電圖案122A的材質與第二導電圖案124A的材質符合第二導電圖案124A的導電率小於第一導電圖案122A的導電率，皆屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。
值得注意的是，在本實施例中，當來自訊號來源區116的電流E通過接墊114而進入球底金屬層120A時，由於第二導電圖案124A的導電率小於第一導電圖案122A的導電率，且第二導電圖案124A設置於靠近訊號來源區116，因此較多部份的電流E會經由高導電率的第一導電圖案122A流出，而較少部份的電流E會經由低導電率的第二導電圖案124A流出。換言之，流經靠近訊號來源區116的電流E量小於遠離訊號來源區116的電流E量，故本實施例可以減少電致遷移現象對鄰近訊號來源區116之球底金屬層120A的損壞，同時亦可以有效地使電流E的密度能夠均勻分佈於球底金屬層120A中，進而提高封裝載板100A的可靠度。
導電凸塊130配置於球底金屬層120A上，且導電凸塊130透過球底金屬層120A與基材110電性連接，其中導電凸塊130的材質例如是鉛錫合金。另外，在本實施例中，球底金層層120A更包括一黏著層139，其中黏著層129配置於球底金屬層120A與接墊114之間，用以加強球底金屬層12A與接墊114之間的結合性。
簡言之，本實施例之球底金屬層120A，其具有兩種不同導電率之第一導電圖案122A與第二導電圖案124A，其中第二導電圖案124A的導電率小於第一導電圖案122A的導電率，且第二導電圖案124A設置於靠近訊號來源區116。因此當來自訊號來源區116的電流E通過接墊114而進入球底金屬層120A時，流經靠近訊號來源區116的電流E量會小於遠離訊號來源區116的電流E量，使電流E的密度能夠均勻分佈於球底金屬層120A中，以有效改善電流擁擠現象。同時，亦可減少電致遷移現象對鄰近訊號來源區116之球底金屬層120A的損壞，進而可提高封裝載板100A的可靠度。
值得一提的是，本發明並不限定球底金屬層120A的型態，雖然上述實施例所提及的球底金屬層120A具體化為第一導電圖案122A的一側壁與第二導電圖案124A的一側壁直接接觸，且第一導電圖案122A的上表面與第二導電圖案124A的上表面共平面，但已知的其他能達到使電流均勻分佈於球底金屬層120A內的結構設計，仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。因此，以下將再舉例說明本發明其他多種不同型態之球底金屬層120B～120H分別應用於封裝載板100B～100H的設計。
圖3A為本發明之另一實施例之一種封裝載板的剖面示意圖，3B為圖3A之球底金屬層的上視圖。請同時參考圖3A、圖3B，在本實施例中，圖3A之封裝載板100B與圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖3A之封裝載板100B的球底金屬層120B，其第二導電圖案124B是位於第一導電圖案122B的周圍，且第二導電圖案124B的上表面與第一導電圖案122B的上表面共平面。
圖4A為本發明之另一實施例之一種封裝載板的剖面示意圖，圖4B為圖4A之球底金屬層的上視圖。請同時參考圖4A、圖4B，在本實施例中，圖4A之封裝載板100C與圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖4A之封裝載板100C的球底金屬層120C，其第二導電圖案124C是位於第一導電圖案122C的周圍，且第二導電圖案124C的上表面高於第一導電圖案122C的上表面。
圖5A為本發明之另一實施例之一種封裝載板的剖面示意圖，圖5B為圖5A之球底金屬層的上視圖。請同時參考圖5A、圖5B，在本實施例中，圖5A之封裝載板100D圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖5A之封裝載板100D的球底金屬層120D，其第二導電圖案124D是位於第一導電圖案122D的周圍，且第二導電圖案124D的上表面低於第一導電圖案122D的上表面。
圖6A為本發明之另一實施例之一種封裝載板的剖面示意圖，圖6B為圖6A之球底金屬層的上視圖。請同時參考圖6A、圖6B，在本實施例中，圖6A之封裝載板100E與圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖6A之封裝載板100E的球底金屬層120E，其第二導電圖案124E是位於第一導電圖案122E的周圍，且第二導電圖案124E更延伸至第一導電圖案122E的部分上表面。
圖6C為本發明之另一實施例之一種封裝載板的剖面示意圖，圖6D為圖6C之球底金屬層的上視圖。請同時參考圖6C、圖6D，在本實施例中，圖6C之封裝載板100E’與圖6A之封裝載板100E相似，惟二者主要差異之處在於：圖6C之封裝載板100E’的球底金屬層120E’，其第二導電圖案124E’是位於第一導電圖案122E’的周圍，且第一導電圖案122E’更延伸至第二導電圖案124E’的部分上表面。
圖7A為本發明之另一實施例之一種封裝載板的剖面示意圖，圖7B為圖7A之球底金屬層的上視圖。請同時參考圖7A、圖7B，在本實施例中，圖7A之封裝載板100F與圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖7A之封裝載板100F的球底金屬層120F，其第一導電圖案122F與第二導電圖案124F皆為柵狀結構，且第一導電圖案122F與第二導電圖案124F彼此交錯配置。
圖8A為本發明之另一實施例之一種封裝載板的剖面示意圖，圖8B為圖8A之球底金屬層的上視圖。請同時參考圖8A、圖8B、，在本實施例中，圖8A之封裝載板100G與圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖8A之封裝載板100G的球底金屬層120G具有一導電圖案126A與一柵狀導電圖案127A。
詳細而言，在本實施例中，導電圖案126A位於接墊114的表面上，柵狀導電圖案127A位於導電圖案126A的表面上，其中柵狀導電圖案127A的導電率小於導電圖案126A的導電率，且柵狀導電圖案127A的一部分靠近訊號來源區116。此外，柵狀導電圖案127A的面積佔整體球底金屬層120G的面積的5%至60%。導電圖案126A與柵狀導電圖案127A的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
上述圖7A、圖7B之實施例以及圖8A、圖8B之實施例皆有柵狀導電圖案的設計。柵狀導電結構除了可以有效達成改善球底金屬層在訊號來源區的電流擁擠現象之外，還可以對電流產生分流的效果，以使得電流能夠均勻的通過球底金屬層。
圖9A為本發明之另一實施例之一種封裝載板的剖面示意圖，圖9B為圖9A之球底金屬層的上視圖。請同時參考圖9A、圖9B，在本實施例中，圖9A之封裝載板100H與圖2A之封裝載板100A相似，惟二者主要差異之處在於：圖9A之封裝載板100H的球底金屬層120H，其更包括一第三導電圖案128A，且第二導電圖案124H是位於第一導電圖案122H之上表面的兩側邊。第三導電圖案128A位於第一導電圖案122H之上表面的中間，其中第三導電圖案128A的導電率大於第一導電圖案122H的導電率，第一導電圖案122H的導電率大於第二導電圖案124H的導電率，且第二導電圖案124H相較於第三導電圖案128A較靠近訊號來源區116。此外，第三導電圖案128A材質可選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金，
圖10A為本發明之一實施例之一種接合結構的剖面示意圖，圖10B為圖10A之第一球底金屬層的上視圖，圖10C為圖10A之第二球底金屬層的上視圖。請先參考圖10A，在本實施例中，接合結構200包括一第一基材210、第一球底金屬層220A、220B、一第二基材230、第二球底金屬層240A、240B、導電凸塊250A、250B以及一保護層260。
詳細而言，第一基材210具有第一導電結構212A、212B以及與分別與第一導電結構212A、212B相連接第一接墊214A、214B，其中第一接墊214A、214B與第一導電結構212A、212B接觸的區域為第一訊號來源區216A、216B。特別是，在本實施例中，第一基材210為一晶片，且第一接墊214A、214B與第一導電結構212A、212B皆內埋於第一基材210的表面。
請參考圖10A與圖10B，在本實施例中，第一球底金屬層220A、220B皆分別配置於第一接墊214A、214B上。第一球底金屬層220A、220B分別包括第一導電圖案222A、222B以及第二導電圖案234A、224B，其中第二導電圖案224A、224B的側壁與第一導電圖案222A、222B的側壁直接接觸，且第二導電圖案224A、224B設置於靠近訊號來源區216A、216B，其中第一導電圖案222A、222B與第二導電圖案224A、224B皆為單層結構，第二導電圖案224A、224B的導電率小於第一導電圖案222A、222B的導電率。當然，於其他實施例中，第一導電圖案222A、222B與第二導電圖案224A、224B亦可皆為多層結構。另外，第二導電圖案224A、224B的面積佔整體球底金屬層220A、220B的面積的5%至60%。
特別是，在本實施例中，球底金屬層220A之第一導電圖案222A的一側壁與第二導電圖案224A的一側壁直接接觸，且第一導電圖案222A的上表面與第二導電圖案224A的上表面共平面。球底金屬層220B之第一導電圖案222B與第二導電圖案224B皆為柵狀結構，且第一導電圖案222B與第二導電圖案224B彼此交錯配置。第一導電圖案222A、222B與第二導電圖案224A、224B的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
第二基材230設置於第一基材210的對向，且第二基材230具有一第二導電結構232以及與第二導電結構232連接的二第二接墊234A、234B，其中第二接墊234A、234B與第二導電結構234接觸的區域為一第二訊號來源區236。特別是，在本實施例中，第二基材230為一晶片，且第二接墊234A、234B與第二導電結構232皆突出於第二基材230的表面。另外，本實施例之接合結構200於第二基材230的表面上更包括一保護層260，其中保護層260具有二開口262A、262B，且開口262A、262B分別暴露出部份第二接墊234A、234B。
請參考圖10A與圖10C，在本實施例中，第二球底金屬層240A、240B分別配置於第二接墊234A、234B上，其中第二球底金屬層240A、240B一部份是位於保護層260之開口262A、262B所暴露出的第二接墊234A、234B上，第二球底金屬層240A、240B之另一部份是位於第二接墊234A、234B上方的保護層260上。
進一步而言，第二球底金屬層240A包括一第三導電圖案242以及一第四導電圖案244。第四導電圖案244的側壁與第三導電圖案242的側壁直接接觸，且第四導電圖244案設置於靠近第二訊號來源區236，其中第三導電圖案242與第四導電圖案244皆為單層結構，且第四導電圖案244的導電率小於第三導電圖案242的導電率。當然，於其他實施例中，第三導電圖案242與第四導電圖案244亦可皆為多層結構。特別是，在本實施例中，第四導電圖案244是位於第三導電圖案242的周圍，且第四導電圖案244的上表面與第三導電圖案242的上表面共平面。此外，第四導電圖案244的面積佔整體球底金屬層240A的面積的5%至60%，且第三導電圖案242與第四導電圖案244的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
第二球底金屬層240B包括一導電圖案246以及一柵狀導電圖案248。導電圖案246位於第二接墊234B的表面上，柵狀導電圖案248位於導電圖案246的表面上，其中柵狀導電圖案248的導電率小於導電圖案246的導電率，且柵狀導電圖案248的一部分靠近第二訊號來源區236。在本實施例中，柵狀導電圖案248的面積佔整體球底金屬層240B的面積的5%至60%，且導電圖案246與柵狀導電圖案248的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
請再參考圖10A，在本實施例中，導電凸塊250A、250B分別配置於第一球底金屬層220A、220B與第二球底金屬層240A、240B之間，其中來自第一基材210之第一訊號來源區216A的電流E依序通過第一接墊214A、第一球第金屬層220A、導電凸塊250A、第二球底金屬層240A以及第二接墊234A而進入第二基材230，之後，經由第二訊號來源區236使電流E依序通過第二接墊234B、第二球第金屬層240B、導電凸塊250B、第一球底金屬層220B以及第一接墊214B而回到第一基材210。換言之，第一基板210與第二基板230可透過導電凸塊250A、250B而彼此電性連接。
此外，在本實施例中，球底金屬層240A、240B更包括黏著層249A、249B，其中黏著層249A、249B分別配置於球底金屬層240A、240B與第二接墊234A、234B之間，用以加強球底金屬層240A、240B與第二接墊234A、234B之間的結合性。
值得一提的是，本發明並不限定第一球底金屬層220A、220B與第二球底金屬層240A、240B型態，只要能使電流E能均勻分佈於第一球底金屬層220A、220B與第二球底金屬層240A、240B內的結構設計，皆屬本發明所所欲保護的範圍。故，本發明所屬技術領域中具有通常知識者可以參考圖3A～圖9A而將圖10A中的第一球底金屬層220A、220B與第二球底金屬層240A、240B替換組合。
此外，本實施例之接合結構200中所提及之第一球底金屬層220A、220B、第二球底金屬層240A、240B以及導電凸塊250A、250B具體化皆為兩個，但於其他未繪示的實施例中，第一球底金屬層、第二球底金屬層以及導電凸塊皆亦可以只有一個或大於兩個，只要單一導電凸塊搭配單一第一球底金屬層與單一第二球底金屬層即可，皆屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。
此外，本實施例之接合結構200中所提及之第一基材210與第二基材230具體化皆為一晶片，但於其他實施例中，第一基材210與第二基材230亦可以是一電路板與一晶片的搭配組合，請參考圖10D。於圖10D中，第一基材210’例如為一電路板，第二基材230’例如為一晶片，其中圖10D之第一基材210’與圖10A之第一基材210惟二者主要差異之處在於：第一基材210’無球底金屬層220A、220B。故，圖10A與圖10D所述之第一基材210、210’與第二基材230、230’的形態僅為舉例說明，本發明並不以此為限。
簡言之，本實施例之接合結構200，其第一金屬層220A、220B分別具有兩種不同導電率之第一導電圖案222A、222B與第二導電圖案224A、224B。第二金屬層240A、240B分別具有兩種不同導電率之第三導電圖案242與第四導電圖案244或導電圖案246與柵狀導電圖案248。第二導電圖案224A、224B的導電率、第四導電圖案244的導電率以及柵狀導電圖案248的導電率分別小於第一導電圖案222A、222B的導電率、第三導電圖案242的導電率以及導電圖案246的導電率，且第二導電圖案224A、224B、第四導電圖案244以及柵狀導電圖案248皆分別設置於靠近第一訊號來源區216A、216B或第二訊號來源區236。因此，當來自第一訊號來源區216A的電流E進入第一球底金屬層220A、220B以及第二球底金屬層240A、240B時，流經靠近第一訊號來源區216A、216B及第二訊號來源區236的電流E量會小於遠離第一訊號來源區216A、216B及第二訊號來源區236的電流E量，使電流E的密度能夠均勻分佈於第一球底金屬層220A、220B與第二球底金屬層240A、240B中，以有效改善電流擁擠現象。同時，亦可減少電致遷移現象對鄰近第一訊號來源區216A、216B及第二訊號來源區236的第一球底金屬層220A、220B與第二球底金屬層240A、240B的損壞，進而可提高接合結構200的可靠度。
綜上所述，本發明之球底金屬層具有兩種不同導電率之導電圖案，其中導電圖案皆為單層結構，且低導電率之導電圖案設置於靠近訊號來源區，因此當來自訊號來源區的電流進入球底金屬層時，流經靠近訊號來源區的電流量會小於遠離訊號來源區的電流量，使電流的密度能夠均勻分佈於球底金屬層中。本發明之封裝載板與接合接構可使電流通過接墊而進入球底金屬層時之密度能夠均勻分佈，可有效改善電流擁擠現象，同時亦可減少電致遷移現象對鄰近訊號來源區之球底金屬層的損壞，進而可提高封裝載板及接合結構的可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1．．．覆晶封裝體
10．．．晶片
12．．．晶片接墊
14．．．導線結構
16．．．第一保護層
16A．．．開口
18．．．區域
20．．．基板
22．．．基板接墊
24．．．第二保護層
30．．．球底金屬層
32．．．黏著層
34．．．阻障層
36．．．沾錫層
40．．．導電凸塊
50．．．封裝膠體
100A～100H、100E’．．．封裝載板
110．．．基材
112．．．導電結構
114．．．接墊
116．．．訊號來源區
120A～120H、120E’．．．球底金屬層
122A～122H、122E’．．．第一導電圖案
124A～124H、124E’．．．第二導電圖案
126A．．．導電圖案
127A．．．柵狀導電圖案
128A．．．第三導電圖案
129．．．黏著層
130．．．導電凸塊
140．．．保護層
142．．．開口
200．．．接合結構
210、210’．．．第一基材
212A、212B．．．第一導電結構
214A、214B．．．第一接墊
216A、216B．．．第一訊號來源區
220A、220B．．．第一球底金屬層
222A、222B．．．第一導電圖案
224A、224B．．．第二導電圖案
230、230’．．．第二基材
232．．．第二導電結構
234A、234B．．．第二接墊
236．．．第二訊號來源區
240A、240B．．．第二球底金屬層
242．．．第三導電圖案
244．．．第四導電圖案
246．．．導電圖案
248．．．柵狀導電圖案
249A、249B．．．黏著層
250A、250B．．．導電凸塊
260．．．保護層
262A、262B．．．保護層
E．．．電流
圖1是習知之一覆晶封裝體的剖面示意圖。
圖2A為本發明之一實施例之一種封裝載板的剖面示意圖。
圖2B為圖2A之球底金屬層的上視圖。
圖3A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖3B為圖3A之球底金屬層的上視圖。
圖4A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖4B為圖4A之球底金屬層的上視圖。
圖5A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖5B為圖5A之球底金屬層的上視圖。
圖6A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖6B為圖6A之球底金屬層的上視圖。
圖6C為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖6D為圖6C之球底金屬層的上視圖。
圖7A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖7B為圖7A之球底金屬層的上視圖。
圖8A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖8B為圖8A之球底金屬層的上視圖。
圖9A為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖9B為圖9A之球底金屬層的上視圖。
圖10A為本發明之一實施例之一種接合結構的剖面示意圖。
圖10B為圖10A之第一球底金屬層的上視圖。
圖10C為圖10A之第二球底金屬層的上視圖。
圖10D為本發明之另一實施例之一種接合結構的剖面示意圖。
100A．．．封裝載板
110．．．基材
112．．．導電結構
114．．．接墊
116．．．訊號來源區
120A．．．球底金屬層
122A．．．第一導電圖案
124A．．．第二導電圖案
129．．．黏著層
130．．．導電凸塊
140．．．保護層
142．．．開口
E．．．電流

Claims (37)

  1. 一種封裝載板，包括：一基材，其具有一導電結構以及與該導電結構連接的至少一接墊，其中該接墊與該導電結構接觸的區域為一訊號來源區；至少一球底金屬層，配置於該接墊上，該球底金屬層包括：一第一導電圖案；一第二導電圖案，該第二導電圖案的側壁與該第一導電圖案的側壁直接接觸，且該第二導電圖案設置於靠近該訊號來源區，其中該第二導電圖案的導電率小於該第一導電圖案的導電率；以及至少一導電凸塊，配置於該球底金屬層上，其中該第一導電圖案連接該導電凸塊與該接墊，而該第二導電圖案連接該導電凸塊與該接墊，當來自該訊號來源區的一電流量通過該接墊進入該球底金屬層時，經由該第一導電圖案流出的該電流量多於經由該第二導電圖案流出的該電流量。
  2. 如申請專利範圍第1項所述之封裝載板，其中該第一與該第二導電圖案為單層結構或是多層結構。
  3. 如申請專利範圍第1項所述之封裝載板，其中該第二導電圖案位於該第一導電圖案的周圍或是一側。
  4. 如申請專利範圍第3項所述之封裝載板，其中該第二導電圖案的上表面與該第一導電圖案的上表面共平面。
  5. 如申請專利範圍第3項所述之封裝載板，其中該第 二導電圖案的上表面高於該第一導電圖案的上表面。
  6. 如申請專利範圍第3項所述之封裝載板，其中該第二導電圖案的上表面低於該第一導電圖案的上表面。
  7. 如申請專利範圍第1項所述之封裝載板，其中該第二導電圖案位於該第一導電圖案的周圍或一側，且該第二導電圖案更延伸至該第一導電圖案的部分上表面。
  8. 如申請專利範圍第1項所述之封裝載板，其中該第二導電圖案位於該第一導電圖案的周圍或一側，且該第一導電圖案更延伸至該第二導電圖案的部分上表面。
  9. 如申請專利範圍第1項所述之封裝載板，其中該第一導電圖案與該第二導電圖案皆為柵狀結構，且兩者彼此交錯配置。
  10. 如申請專利範圍第1項所述之封裝載板，其中該球底金屬層更包括一黏著層，配置於該球底金屬層與該接墊之間。
  11. 如申請專利範圍第1項所述之封裝載板，其中該基材為晶片或電路板。
  12. 如申請專利範圍第1項所述之封裝載板，其中該第一導電圖案與該第二導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  13. 如申請專利範圍第1項所述之封裝載板，其中該第二導電圖案的面積佔整體該球底金屬層的面積的5%至60%。
  14. 一種封裝載板，包括： 一基材，其具有一導電結構以及與該導電結構連接的至少一接墊，其中該接墊與該導電結構接觸的區域為一訊號來源區；至少一球底金屬層，配置於該接墊上，該球底金屬層包括：一導電圖案，位於該接墊的表面上；一柵狀導電圖案，位於該導電圖案的表面上，其中該柵狀導電圖案的導電率小於該導電圖案的導電率，且該柵狀導電圖案的一部分靠近該訊號來源區；以及至少一導電凸塊，配置於該球底金屬層上，其中該導電圖案連接該導電凸塊與該接墊，而該柵狀導電圖案連接該導電凸塊與該導電圖案，且當來自該訊號來源區的一電流量通過該接墊進入該球底金屬層時，經由該導電圖案流出的該電流量多於經由該柵狀導電圖案流出的該電流量。
  15. 如申請專利範圍第14項所述之封裝載板，其中該球底金屬層更包括一黏著層，配置於該球底金屬層與該接墊之間。
  16. 如申請專利範圍第14項所述之封裝載板，其中該基材為晶片或電路板。
  17. 如申請專利範圍第14項所述之封裝載板，其中該導電圖案與該柵狀導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  18. 如申請專利範圍第14項所述之封裝載板，其中該柵狀導電圖案的面積佔整體該球底金屬層的面積的5%至 60%。
  19. 一種接合結構，包括：一第一基材，其具有一第一導電結構以及與該第一導電結構連接的至少一第一接墊，其中該第一接墊與該第一導電結構接觸的區域為一第一訊號來源區；至少一第一球底金屬層，配置於該第一接墊上，該第一球底金屬層包括：一第一導電圖案；一第二導電圖案，該第二導電圖案的側壁與該第一導電圖案的側壁直接接觸，且該第二導電圖案設置於靠近該第一訊號來源區，其中該第二導電圖案的導電率小於該第一導電圖案的導電率；一第二基材，設置於該第一基材的對向，該第二基材具有一第二導電結構以及與該第二導電結構連接的至少一第二接墊，其中該第二接墊與該第二導電結構接觸的區域為一第二訊號來源區；至少一第二球底金屬層，配置於該第二接墊上；以及至少一導電凸塊，配置於該第一球底金屬層與該第二球底金屬層之間，其中該第一導電圖案連接該導電凸塊與該第一接墊，而該第二導電圖案連接該導電凸塊與該第一接墊，當來自該訊號來源區的一電流量通過該第一接墊進入該第一球底金屬層時，經由該第一導電圖案流出的該電流量多於經由該第二導電圖案流出的該電流量。
  20. 如申請專利範圍第19項所述之接合結構，其中該第一與該第二導電圖案為單層結構或是多層結構。
  21. 如申請專利範圍第19項所述之接合結構，其中該第一導電圖案與該第二導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  22. 如申請專利範圍第19項所述之接合結構，其中該第二球底金屬層包括：一第三導電圖案；一第四導電圖案，該第四導電圖案的側壁與該第三導電圖案的側壁直接接觸，且該第四導電圖案設置於靠近該第二訊號來源區，其中該第四導電圖案的導電率小於該第三導電圖案的導電率。
  23. 如申請專利範圍第22項所述之接合結構，其中該第三導電圖案與該第四導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  24. 如申請專利範圍第19項所述之接合結構，其中該第四導電圖案的面積佔整體該第二球底金屬層的面積的5%至60%。
  25. 如申請專利範圍第19項所述之接合結構，其中該第二球底金屬層包括：一導電圖案，位於該第二接墊的表面上；以及一柵狀導電圖案，位於該導電圖案的表面上，其中該柵狀導電圖案的導電率小於該導電圖案的導電率，且該柵狀圖案的一部分靠近該第二訊號來源區。
  26. 如申請專利範圍第25項所述之接合結構，其中該 導電圖案與該柵狀導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  27. 如申請專利範圍第25項所述之接合結構，其中該柵狀導電圖案的面積佔整體該第二球底金屬層的面積的5%至60%。
  28. 如申請專利範圍第19項所述之接合結構，其中該第一基材與該第二基材分別為晶片或電路板。
  29. 如申請專利範圍第19項所述之接合結構，其中該第二導電圖案的面積佔整體該第一球底金屬層的面積的5%至60%。
  30. 如申請專利範圍第19項所述之接合結構，其中該第二球底金屬層包括：一第三導電圖案，位於該第二接墊的表面上；一第四導電圖案，位於該第三導電圖案的表面上；一第五導電結構，位於該第三導電圖案的表面上，其中第五導電圖案的導電率大於該第三導電圖案的導電率，該第三導電圖案的導電率大於該第四導電圖案的導電率，且該第四導電圖案相較於該第五導電圖案較靠近該訊號來源區。
  31. 如申請專利範圍第30項所述之接合結構，其中該第三、第四以及第五導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  32. 如申請專利範圍第30項所述之接合結構，其中該 第四導電圖案的面積佔整體該第二球底金屬層的面積的5%至60%。
  33. 一種封裝載板，包括：一基材，其具有一導電結構以及與該導電結構連接的至少一接墊，其中該接墊與該導電結構接觸的區域為一訊號來源區；至少一球底金屬層，配置於該接墊上，該球底金屬層包括：一第一導電圖案，位於該接墊的表面上；一第二導電圖案，位於該第一導電圖案的表面上；一第三導電圖案，位於該第一導電圖案的表面上，其中第三導電圖案的導電率大於該第一導電圖案的導電率，該第一導電圖案的導電率大於該第二導電圖案的導電率，且該第二導電圖案相較於該第三導電圖案較靠近該訊號來源區；以及至少一導電凸塊，配置於該球底金屬層上，其中該第一導電圖案連接該導電凸塊與該接墊，而該第二導電圖案與該第三導電圖案連接該第一導電圖案與該導電凸塊，且當來自該訊號來源區的一電流量通過該接墊進入該球底金屬層時，經由該第三導電圖案流出的該電流量多於經由該第一導電圖案流出的該電流量，且經由該第一導電圖案流出的該電流量多於經由該第二導電圖案流出的該電流量。
  34. 如申請專利範圍第33項所述之封裝載板，其中該球底金屬層更包括一黏著層，配置於該球底金屬層與該接 墊之間。
  35. 如申請專利範圍第33項所述之封裝載板，其中該基材為晶片或電路板。
  36. 如申請專利範圍第33項所述之封裝載板，其中該第一、第二以及第三導電圖案的材質分別選自銅、銀、鎳、鋁、鈦、鎢、鉻、金、鋅、鉍、銦、錫以及上述任一金屬的合金。
  37. 如申請專利範圍第33項所述之封裝載板，其中該第二導電圖案的面積佔整體該球底金屬層的面積的5%至60%。
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