TWI394263B - Semiconductor struture and method of formipg the same - Google Patents

Semiconductor struture and method of formipg the same Download PDF

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Publication number
TWI394263B
TWI394263B TW98124896A TW98124896A TWI394263B TW I394263 B TWI394263 B TW I394263B TW 98124896 A TW98124896 A TW 98124896A TW 98124896 A TW98124896 A TW 98124896A TW I394263 B TWI394263 B TW I394263B
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Taiwan
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region
gate
semiconductor structure
layer
portion
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TW98124896A
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Chinese (zh)
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TW201104835A (en
Inventor
Chu Kuang Liu
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Excelliance Mos Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to an integrated power metal-oxide-semiconductor field effect transistor (power MOSFET) and a Schottky diode ( Schottky diode) semiconductor structure and its manufacturing method.

Power MOSFETs are widely used in switching components such as power supplies, rectifiers or low voltage motor controllers and the like. 1 is a schematic cross-sectional view showing a conventional power MOS field effect transistor. Referring to FIG. 1, an N-type epitaxial layer 12 is disposed on the N-type heavily doped substrate 10. The gate 16 is disposed in the N-type epitaxial layer 12. The P-type body layer 14 is disposed in the N-type epitaxial layer 12 on both sides of the gate 16. The N-type heavily doped regions 18 are disposed in the P-type body layer 14 on both sides of the gate 16. The dielectric layer 20 is disposed on the gate 16 and the N-type heavily doped region 18. The source metal layer 22 is disposed on the dielectric layer 20 and electrically connected to the N-type heavily doped region 18. The drain metal layer 24 is disposed on the other side of the N-type heavily doped substrate 10.

As notebook and handheld products become more demanding, they need to be designed to have lower output voltage, lower forward voltage drop, lower power loss, and faster reverse recovery. (reverse recovery) synchronous rectification field effect transistor (sync-FET). However, since it exists between the P-type body layer 14 and the N-type epitaxial layer 12 Intrinsic PN diodes, the above requirements are difficult to achieve.

It is known to integrate power MOS field effect transistors and Schottky diodes to meet the above requirements. Today's technologies include silicon-in-one-package (SiP) and system-in-one-chip (SOC). The single package integration encapsulates the power MOS field effect transistor and the Schottky diode in parallel, and the process is simple, but the connection of the power MOS field effect transistor and the Schottky diode wire can cause parasitic Parastitic inductances, which in turn limit overall efficiency. Although the single wafer integration can solve the above-mentioned parasitic induction effect, the cell pitch is high (greater than 2 μm), so the cell density cannot be improved.

In view of the above, the present invention provides a semiconductor structure that can effectively integrate power MOS field effect transistors and Schottky diodes and increase cell density.

The present invention further provides a method of fabricating a semiconductor structure that is simple in process and can be integrated with existing processes.

The present invention provides a semiconductor structure including a substrate having a first conductivity type, an epitaxial layer having a first conductivity type, a body layer having a second conductivity type, a first gate, a second gate, a first contact window, and a first Two contact windows and a first doped region having a first conductivity type. The substrate has a first zone, a second zone, and a third zone, wherein the second zone is located between the first zone and the third zone. The epitaxial layer is disposed on the substrate. The body layer is disposed in the epitaxial layer of the first region and the second region. First a gate and a second gate are disposed in a portion of the epitaxial layer outside the body layer and the body layer, wherein the first gate is located between the first region and the second region, and the second gate is located in the second region and Between the three districts. The first contact window is disposed in a portion of the body layer of the first region. The second contact window is disposed at least in the epitaxial layer of the third region and is in contact with the epitaxial layer and the second gate, wherein the first contact window is electrically connected to the second contact window. The first doped region is disposed in the body layer between the first contact window and the first gate.

In an embodiment of the invention, the second contact window is embedded in the second gate.

In an embodiment of the invention, the second contact window is disposed in the epitaxial layer of the third region and the portion of the second region, and the second gate is located below the second contact window.

In an embodiment of the invention, the body layer of the second region covers the sidewall of the second contact window and a portion of the bottom portion.

In an embodiment of the invention, the semiconductor structure further includes a second doped region having a second conductivity type disposed on a bottom portion and a portion of the sidewall of the first contact window.

In an embodiment of the invention, the semiconductor structure further includes a dielectric layer and a metal layer. The dielectric layer is disposed on the substrate and exposes the first contact window and the second contact window. The metal layer is disposed on the substrate and covers the dielectric layer, the first contact window, and the second contact window.

In an embodiment of the invention, the first contact window and the second contact window respectively comprise a first metal layer and a barrier layer around the first metal layer.

In an embodiment of the invention, the material of the first metal layer comprises tungsten.

In an embodiment of the invention, the material of the metal layer comprises aluminum beryllium copper.

In an embodiment of the invention, the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, and the second conductivity type is an N type.

In an embodiment of the invention, the semiconductor structure has a cell pitch of about 1.5 μm or less.

In one embodiment of the invention, the semiconductor structure has a cell density greater than or equal to about 3 x 10 8 cells per square inch (300 M cell/inch 2 ).

In an embodiment of the invention, the second gate is equipotential to the metal layer.

In an embodiment of the invention, the first zone surrounds the second zone and the second zone surrounds the third zone.

In an embodiment of the invention, the semiconductor structure further includes at least one third gate, and the third gate is disposed in the epitaxial layer of the third region and below the second contact window.

In an embodiment of the invention, the third gate is equipotential to the metal layer.

The present invention further provides a semiconductor structure including a substrate, at least one power MOS field effect transistor, a floating diode or body diode, and at least one Schottky diode. The substrate has a first zone, a second zone, and a third zone, wherein the second zone is located between the first zone and the third zone. At least one The power MOS field effect transistor is disposed in the first region. The floating diode or the body diode is disposed in the second region. At least one Schottky diode is disposed in the third zone. In addition, the material of the contact window of the power MOS field effect transistor and the Schottky diode includes tungsten and is electrically connected to each other.

In an embodiment of the invention, the first zone surrounds the second zone and the second zone surrounds the third zone.

In an embodiment of the invention, the semiconductor structure has a cell pitch of about 1.5 μm or less.

In one embodiment of the invention, the semiconductor structure described above has a cell density greater than or equal to about 3 x 10 8 cells per square inch.

The present invention further provides a method of fabricating a semiconductor structure. First, a substrate having a first conductivity type is provided, the substrate having a first region, a second region, and a third region, wherein the second region is between the first region and the third region. Next, an epitaxial layer having a first conductivity type is formed on the substrate. Then, a first gate and a second gate are formed in the epitaxial layer, wherein the first gate is located between the first region and the second region, and the second gate is located between the second region and the third region. Thereafter, a body layer having a second conductivity type is formed in the epitaxial layers of the first region and the second region. A first doped region having a first conductivity type is formed in the body layer of the first region. Forming a dielectric layer on the substrate to expose a portion of the first doped region of the first region, at least a third epitaxial layer, and at least a portion of the second gate. Using a dielectric layer as a mask, a portion of the first doped region, a portion of the epitaxial layer, and a portion of the second gate are removed to form a first doped region of the first region and a portion of the body other than the first doped region A first opening is formed in the layer, and a second opening is formed in the epitaxial layer of the third region and a portion of the second gate. Filling in the first opening and the second opening The first metal layer. A second metal layer is formed on the substrate to cover the dielectric layer and the first metal layer.

In an embodiment of the invention, the dielectric layer exposes a portion of the first doped region of the first region, the epitaxial layer of the third region, the entire second gate, and a portion of the bulk layer of the second region.

In an embodiment of the invention, after the step of forming the first opening and the second opening and before the step of filling the first metal layer, the method of the present invention further comprises forming a second portion at the bottom of the first opening. A second doped region of conductivity type.

In an embodiment of the invention, the method of the present invention further comprises forming a barrier in the first opening and the second opening after the step of forming the second doping region and before the step of filling in the first metal layer. Floor.

In an embodiment of the invention, the material of the first metal layer comprises tungsten.

In an embodiment of the invention, the material of the second metal layer comprises aluminum beryllium copper.

In an embodiment of the invention, the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, and the second conductivity type is an N type.

In an embodiment of the invention, the second gate is equipotential to the second metal layer.

In an embodiment of the invention, the first zone surrounds the second zone and the second zone surrounds the third zone.

In an embodiment of the invention, the first gate is formed in the epitaxial layer and In the step of the second gate, the manufacturing method of the semiconductor further includes forming at least one third gate in the epitaxial layer of the third region.

In an embodiment of the invention, the third gate is equipotential to the second metal layer.

Based on the above, in the semiconductor structure of the present invention, since the tungsten contact window is disposed in the power MOS field effect transistor region and the Schottky diode region, the cell pitch (adjacent power MOS field effect transistor) The distance can be reduced to about 1.5 μm or less, and the cell density can be increased to about 3 x 10 8 units per square inch or higher. Moreover, the method of the present invention is simple, easy, and can be integrated with existing processes, and is a relatively competitive practice.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a top plan view of a semiconductor structure according to a first embodiment of the present invention, in which the uppermost metal layer and the dielectric layer are hidden.

Referring to FIG. 2, in the semiconductor structure of the present invention, a floating diode surrounds a Schottky diode, and sixteen power MOS field effect transistors surround the floating diode. Around. However, the present invention does not limit the number of Schottky diodes, floating diodes, and power MOS field effect transistors, and can be adjusted according to process or design requirements. In general, the number of Schottky diodes is about one-tenth to one-thirth of the number of power MOS field effect transistors.

Fig. 2A is a schematic cross-sectional view taken along line I-I' of Fig. 2. Referring to FIG. 2A, the semiconductor structure of the present invention includes a substrate 100 having a first conductivity type. The substrate 100 is, for example, a germanium substrate having an N-type heavily doped (N+). The N-type heavily doped germanium substrate serves as the drain of the power MOS field effect transistor. The substrate 100 has a first region 102a, a second region 102b, and a third region 102c. The second zone 102b is located between the first zone 102a and the third zone 102c. The first region 102a is for forming a power MOS field effect transistor, the second region 102b is for forming a floating diode, and the third region 102c is for forming a Schottky diode. In this embodiment, the substrate 100 includes two first regions 102a, two second regions 102b, and a third region 102c, wherein the two first regions 102a are connected to each other, and the two second regions 102b are connected to each other. As shown in the upper view of FIG. 2, the first zone 102a surrounds the second zone 102b and the second zone 102b surrounds the third zone 102c.

The semiconductor structure of the present invention further includes an epitaxial layer 104 having a first conductivity type, a body layer 106 having a second conductivity type, a first gate 108, a second gate 110, a first contact window 114, and a second contact window. 116 and a first doped region 118 having a first conductivity type.

The epitaxial layer 104 is disposed on the substrate 100. The epitaxial layer 104 is, for example, an epitaxial layer having an N-type lightly doped (N-) layer. The body layer 106 is disposed in the epitaxial layer 104 of the first region 102a and the second region 102b. The body layer 106 is, for example, a P-type body layer.

The first gate 108 and the second gate 110 are disposed in the partial epitaxial layer 104 other than the body layer 106 and the body layer 106. The first gate 108 is located between the first region 102a and the second region 102b. The second gate 110 is located in the second zone Between 102b and the third zone 102c. In this embodiment, the two second gates 110 are connected to each other, and the second gate 110 is equipotential to the metal layer 120. As shown in the upper view of FIG. 2, the second gate 110 is substantially rectangular in shape and disposed along the boundary between the second region 102b and the third region 102c. In addition, the first gate 108 and the second gate 110 respectively include a polysilicon layer 109 and an oxide layer 107 located around the polysilicon layer 109.

The first contact window 114 is disposed in a portion of the body layer 106 of the first region 102a. The second contact window 116 is disposed at least in the epitaxial layer 104 of the third region 102c and is in contact with the epitaxial layer 104 and the second gate 110. In this embodiment, the second contact window 116 is disposed in the epitaxial layer 104 of the third region 102c and is embedded in the second gate 110 as shown in FIG. 2A. That is, the second gate 110 covers the sidewall and a portion of the bottom of the second contact window 116. In addition, the first contact window 114 and the second contact window 116 respectively include a metal layer 115 and a barrier layer 113 located around the metal layer 115 . The material of the metal layer 115 is, for example, tungsten, and the material of the barrier layer 113 is, for example, titanium or titanium nitride. In addition, the first doping region 118 is disposed in the body layer 106 between the first contact window 114 and the first gate 108. The first doping region 118 is, for example, a doped region having an N-type heavily doped (N+). The doped region having an N-type heavily doped is used as the source of the power MOS field effect transistor.

The semiconductor structure of the present invention further includes a dielectric layer 112, a metal layer 120, and a second doping region 122 having a second conductivity type. The dielectric layer 112 is disposed on the substrate 100 to expose the first contact window 114 and the second contact window 116. The metal layer 120 is disposed on the substrate 100 and covers the dielectric layer 112 , the first contact window 114 , and the second contact window 116 . That is, the first contact window 114 The second contact window 116 is electrically connected to the second layer via the metal layer 120. The material of the metal layer 120 is, for example, aluminum beryllium copper. The second doping region 122 is disposed on the bottom portion and a portion of the sidewall of the first contact window 114. The second doping region 122 is, for example, a doped region having a P-type heavily doped (P+) to further reduce the electrical resistance between the first contact window 114 and the body layer 106.

In this embodiment, the first region 102a is a power MOS field effect transistor. In the second region 102b, the second gate 110 is equipotential to the metal layer 120, and the metal layer 120 is not in contact with the body layer 106, so the junction between the P-type body layer 106 and the N-type epitaxial layer 104 is floating. Set the diode. In the third region 102c, since the epitaxial layer 104 is an N-type lightly doped epitaxial layer, the junction of the second contact window 116 and the N-type epitaxial layer 104 is Schottky contact.

In the first embodiment, the third region 102c is exemplified by including only one Schottky diode, but the invention is not limited thereto. A modification of the first embodiment will be described below, that is, a top view and a cross-sectional view of the third region 102c including a plurality of Schottky diodes.

Referring to FIG. 3 and FIG. 3A, the semiconductor structure of the present invention further includes two third gates 111, and the two third gates 111 are connected to each other. As shown in FIG. 3A, the third gate 111 is disposed in the epitaxial layer 104 of the third region 102c and is located below the second contact window 116. As shown in FIG. 3, the third gate 111 is substantially in a rectangular frame configuration, and the second gate 110, which is also arranged in a rectangular frame, surrounds the third gate 111. The third gate 111 and the second gate 110 are both at the same potential as the metal layer 120. In this variation, the third zone 102c includes two Schottky diodes. In addition, a floating diode surrounds the two Around the Schottky diode, and sixteen power MOS field effect transistors surround the floating diode.

Referring to FIG. 4 and FIG. 4A, the semiconductor structure of the present invention further includes three third gates 111, and the three third gates 111 are connected to each other. As shown in FIG. 4A, the third gate 111 is disposed in the epitaxial layer 104 of the third region 102c and is located below the second contact window 116. As shown in FIG. 4, the third gate 111 is substantially strip-shaped and is connected to the second gate 110 which is also arranged in a strip shape in a serpentine configuration. The third gate 111 and the second gate 110 are both at the same potential as the metal layer 120. In this variation, the third zone 102c includes four Schottky diodes. In addition, a floating diode surrounds the four Schottky diodes, and sixteen power MOSFETs surround the floating diode.

As shown in FIG. 5 and FIG. 5A, the semiconductor structure of the present invention further includes a third gate 111, and the third gate 111 is substantially fishbone. As shown in FIG. 5A, the third gate 111 is disposed in the epitaxial layer 104 of the third region 102c and is located below the second contact window 116. As shown in FIG. 5, the third gate 111 and the second gate 110 arranged in a strip shape are connected to each other, and the third gate 111 and the second gate 110 are both equipotential to the metal layer 120. In this variation, the third zone 102c includes eight Schottky diodes. In addition, a floating diode surrounds the perimeter of the eight Schottky diodes, and fourteen power MOS field effect transistors surround the floating diode.

FIG. 6 is a top plan view of a semiconductor structure according to a second embodiment of the present invention, in which the uppermost metal layer and the dielectric layer are hidden. Figure 6A is a cross-sectional view taken along line I-I' of Figure 6. Second embodiment and An embodiment is similar in that the second region 102b of the second embodiment is a body diode, which is not the floating diode of the first embodiment. Hereinafter, differences between the second embodiment and the first embodiment will be described, and the same portions will not be described again.

In the second embodiment, since the configurations of the dielectric layer 112, the second contact window 116, and the metal layer 120 are different, the second region 102b forms a body diode, and the second region 102b of the first embodiment floats. The technical characteristics of the diode are different. In detail, the second contact window 116 is disposed in the epitaxial layer 104 of the third region 102c and the portion of the second region 102b, and the second gate 110 is located below the second contact window 116, as shown in FIG. 6A. In addition, the body layer 106 of the second region 102b covers the sidewalls and a portion of the bottom of the second contact window 116. The dielectric layer 112 is disposed on the substrate 100 to expose the first contact window 114 and the second contact window 116. The metal layer 120 is disposed on the substrate 100 and covers the dielectric layer 112 , the first contact window 114 , and the second contact window 116 .

In this embodiment, the first region 102a is a power MOS field effect transistor. Since the second contact window 116 of the second region 102b is electrically connected to the metal layer 120, the junction between the P-type body layer 106 and the N-type epitaxial layer 104 is a body diode. The junction of the second contact window 116 of the third region 102c and the N-type epitaxial layer 104 is a Schottky contact.

In the second embodiment, the third region 102c is exemplified by including only one Schottky diode, but the invention is not limited thereto. Of course, the third region 102c may also include a plurality of Schottky diodes. For the modification and improvement of the third region 102c, please refer to FIGS. 3 to 5 and FIGS. 3A to 5A, and details are not described herein again.

Based on the above, the semiconductor structure of the present invention includes a substrate, a power MOS field effect transistor, a floating diode or a body diode, and Schott Base diode. The substrate has a first zone, a second zone, and a third zone, wherein the second zone is located between the first zone and the third zone. At least one power MOS field effect transistor is disposed in the first region. The floating diode or the body diode is disposed in the second region. At least one Schottky diode is disposed in the third zone. In addition, the material of the contact window of the power MOS field effect transistor and the Schottky diode includes tungsten and is electrically connected to each other.

In the semiconductor structure of the present invention, since the tungsten contact window is disposed in the power MOS field effect transistor region and the Schottky diode region, the cell pitch (distance of the adjacent power MOS field effect transistor) may be From 2.0 μm to less than or equal to 1.5 μm, the cell density can be greatly increased to about 3 x 10 8 cells per square inch (300 M cell/inch 2 ) or higher. Compared with the conventional single wafer integrated structure, the semiconductor structure of the present invention can effectively integrate not only the power MOS field effect transistor and the Schottky diode, but also can increase the cell density and greatly increase its Competitiveness

Hereinafter, a method of manufacturing the semiconductor structure of the present invention will be described. 7A to 7E are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to a first embodiment of the present invention.

First, referring to FIG. 7A, an epitaxial layer 104 having a first conductivity type is formed on a substrate 100 having a first conductivity type as a drain. The substrate 100 is, for example, a germanium substrate having an N-type heavily doped. The substrate 100 has two first regions 102a, two second regions 102b, and a third region 102c. The second zone is located between the first zone and the third zone. In this embodiment, the second area 102c is centered, and the second area 102b and the first area 102a are respectively mirrored. The epitaxial layer 104 is, for example, an epitaxial layer having an N-type light doping, and its shape The method includes performing an epitaxial growth process.

Next, a first gate 108 and a second gate 110 are formed in the epitaxial layer 104. The first gate 108 is located between the first region 102a and the second region 102b. The second gate 110 is located between the second region 102b and the third region 102c. The method of forming the first gate 108 and the second gate 110 includes the following steps. First, a trench in which the first gate 108 and the second gate 110 are formed is formed in the epitaxial layer 104. Then, an oxide layer 107 is conformally formed on the surfaces of the substrate 100 and the trench. The material of the oxide layer 107 is, for example, cerium oxide, and the method of forming the same includes performing a thermal oxidation method. Thereafter, a polysilicon layer 109 is filled in the trench. The method of forming the polysilicon layer 109 includes performing a chemical vapor deposition process. The step of forming the first gate 108 and the second gate 110 in the epitaxial layer 104 further includes forming at least one third gate (not shown) in the epitaxial layer 104 to facilitate formation of FIGS. And the final structure of Figures 3A-5A.

Then, referring to FIG. 7B, a patterned photoresist layer 105 is formed on the substrate 100. Thereafter, the patterned photoresist layer 105 is used as a mask to perform an ion implantation process to form a body layer 106 having a second conductivity type in the epitaxial layer 104 of the first region 102a and the second region 102b. The body layer 106 is, for example, a P-type body layer. Following this, the patterned photoresist layer 105 is removed and a drive-in process is performed. In this step, the patterned photoresist layer 105 covering the third region 102c can avoid unnecessary PN junctions in the third region 102c, thus facilitating the formation of the subsequent Schottky diode.

Next, referring to FIG. 7C, a first doping region 118 having a first conductivity type is formed in the body layer 106 of the first region 102a. First doped region 118 A doped region having an N-type heavily doped. The doped region having an N-type heavily doped is used as the source of the power MOS field effect transistor. The method of forming the first doped region 118 includes performing an ion implantation process and a subsequent drive-in process. Then, a dielectric material layer (not shown) and a patterned photoresist layer 117 are sequentially formed on the substrate 100. Thereafter, a portion of the dielectric material layer and the partial oxide layer 107 are removed by using the patterned photoresist layer 117 as a mask to form the dielectric layer 112. The dielectric layer 112 exposes a portion of the first doped region 118 of the first region 102a, at least the epitaxial layer 104 of the third region 102b, and at least a portion of the second gate 110. In this embodiment, the dielectric layer 112 exposes a portion of the first doped region 118 of the first region 102a, the epitaxial layer 104 of the third region 102c, and a portion of the second gate 110.

Then, referring to FIG. 7D, the dielectric layer 112 is used as a mask to remove a portion of the body layer 106, a portion of the first doping region 118, a portion of the epitaxial layer 104, and a portion of the second gate 110 for the first region. a first opening 124 is formed in a portion of the body layer 106 other than the first doped region 118 and the first doped region 118 of the first doped region 118, and is formed in the epitaxial layer 104 of the third region 102c and a portion of the second gate 110. Two openings 126. Then, a patterned photoresist layer 121 is formed on the substrate 100. Thereafter, the ionizing process is performed by using the patterned photoresist layer 121 as a mask to form a second doping region 122 having a second conductivity type at the bottom of the first opening 124. The second doping region 122 is, for example, a P-type heavily doped doped region. In this step, the second doping region 122 is formed using the same mask as the main body layer 106 (see FIG. 7B). That is, the same bulk layer mask can be used twice, and there is no need to make an additional mask to complete the second doped region 122. In this step, not only the second doping region 122 may be formed to further reduce the subsequently formed first contact window 114 and the body layer 106. The resistance between and covering the patterned photoresist layer 121 of the third region 102c can avoid the formation of unnecessary PN junctions in the third region 102c, thus facilitating the formation of subsequent Schottky diodes.

Then, referring to FIG. 7E, the patterned photoresist layer 121 is removed and a driving process is performed. In this step, the high temperature causes the second doped region 122 to diffuse around it to a portion of the sidewall covering the first opening 124. Next, the barrier layer 113 and the metal layer 115 are sequentially filled in the first opening 124 and the second opening 126. The material of the barrier layer 113 is, for example, titanium or titanium oxide, and the material of the metal layer 115 is, for example, tungsten. The method of forming the barrier layer 113 and the metal layer 115 includes performing a sputtering or chemical vapor deposition process. The barrier layer 113 and the metal layer 115 in the first opening 124 constitute a first contact window 114. The barrier layer 113 and the metal layer 115 in the second opening 126 constitute a second contact window 116. Thereafter, a metal layer 120 is formed on the substrate 100 to cover the dielectric layer 112, the barrier layer 113, and the metal layer 115. Thus, the fabrication of the power MOS field effect transistor of the first region 102a, the floating diode of the first region 102a, and the Schottky diode of the third region 102c are completed.

8A through 8B are schematic cross-sectional views showing a method of fabricating a semiconductor structure in accordance with a second embodiment of the present invention. The difference between the second embodiment and the first embodiment is that the second region 102b of the second embodiment is a body diode, which is not the floating diode of the first embodiment. Hereinafter, differences between the second embodiment and the first embodiment will be described, and the same portions will not be described again.

First, an intermediate structure as shown in Fig. 7B is provided. Next, the patterned photoresist layer 105 is removed. Then, referring to FIG. 8A, a first doping region 118 having a first conductivity type is formed in the body layer 106 of the first region 102a. First blend The impurity region 118 has an N-type heavily doped doped region. Then, a dielectric material layer (not shown) and a patterned photoresist layer 117 are sequentially formed on the substrate 100. Thereafter, a portion of the dielectric material layer and the partial oxide layer 107 are removed by using the patterned photoresist layer 117 as a mask to form the dielectric layer 112. The dielectric layer 112 exposes a portion of the first doped region 118 of the first region 102a, the epitaxial layer 104 of the third region 102b, the entire second gate 110, and a portion of the bulk layer 106 of the second region 102b.

Then, referring to FIG. 8B, the dielectric layer 112 is used as a mask to remove a portion of the body layer 106, a portion of the first doping region 118, a portion of the epitaxial layer 104, and a portion of the second gate 110 for the first region. a first opening 124 is formed in a portion of the body layer 106 other than the first doped region 118 and the first doped region 118 of the first doped region 118, and a second opening is formed in the epitaxial layer 104 of the third region 102c and the portion of the second region 102b. 126. Then, a second doping region 122 having a second conductivity type is formed at the bottom of the first opening 124. The second doping region 122 is, for example, a P-type heavily doped doped region. Next, the barrier layer 113 and the metal layer 115 are sequentially filled in the first opening 124 and the second opening 126. Thereafter, a metal layer 120 is formed on the substrate 100 to cover the dielectric layer 112, the barrier layer 113, and the metal layer 115.

In the above embodiments, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. Those skilled in the art will appreciate that the first conductivity type may also be P-type and the second conductivity type may be N-type.

In summary, in the semiconductor structure of the present invention, at least one Schottky diode is disposed in a plurality of power MOS field effect transistors, and the power MOS field effect transistor and Schottky The diodes are separated by a floating diode or a body diode. By arranging the tungsten contact windows electrically connected to each other in the power MOS field field region and the Schottky diode region, the power MOS field effect transistor and the Schottky diode can be effectively used. Integrated together, and the cell pitch (distance of adjacent power MOS field effect transistors) can be reduced from 2.0 μm to approximately equal to less than 1.5 μm. In this way, the power MOS field-effect transistor region and the Schottky diode region can be integrated in a single wafer, and the cell density can be increased to approximately equal to 3×10 8 cells per square inch or higher, which greatly enhances the competition. force. In addition, the method of the present invention accomplishes the semiconductor structure of the present invention without the need for an additional mask, which is simple in process and can be integrated with existing processes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base

12‧‧‧ epitaxial layer

14‧‧‧ body layer

16‧‧‧ gate

18‧‧‧ heavily doped area

20‧‧‧Dielectric layer

22‧‧‧ source metal layer

24‧‧‧汲metal layer

100‧‧‧Base

102a‧‧‧First District

102b‧‧‧Second District

102c‧‧‧ Third District

104‧‧‧ epitaxial layer

105‧‧‧ patterned photoresist layer

106‧‧‧ body layer

107‧‧‧Oxide layer

108‧‧‧first gate

109‧‧‧Polysilicon layer

110‧‧‧second gate

111‧‧‧third gate

112‧‧‧ dielectric layer

113‧‧‧Barrier layer

114‧‧‧First contact window

115‧‧‧metal layer

116‧‧‧Second contact window

117‧‧‧ patterned photoresist layer

118‧‧‧First doped area

120‧‧‧metal layer

121‧‧‧ patterned photoresist layer

122‧‧‧Second doped area

124‧‧‧ first opening

126‧‧‧ second opening

1 is a schematic cross-sectional view showing a conventional power MOS field effect transistor.

2 is a top plan view of a semiconductor structure according to a first embodiment of the present invention, in which the uppermost metal layer and the dielectric layer are hidden.

Fig. 2A is a schematic cross-sectional view taken along line I-I' of Fig. 2.

3 is a top plan view showing a modification of a semiconductor structure according to a first embodiment of the present invention, in which the uppermost metal layer is hidden. And dielectric layer.

Fig. 3A is a schematic cross-sectional view taken along line I-I' of Fig. 3.

4 is a top plan view showing another modification of the semiconductor structure according to the first embodiment of the present invention, in which the uppermost metal layer and the dielectric layer are hidden.

Fig. 4A is a schematic cross-sectional view taken along line I-I' of Fig. 4.

FIG. 5 is a top plan view showing still another modification of the semiconductor structure according to the first embodiment of the present invention, in which the uppermost metal layer and the dielectric layer are hidden.

Fig. 5A is a schematic cross-sectional view taken along line I-I' of Fig. 5.

FIG. 6 is a top plan view of a semiconductor structure according to a second embodiment of the present invention, in which the uppermost metal layer and the dielectric layer are hidden.

Figure 6A is a cross-sectional view taken along line I-I' of Figure 6.

7A to 7E are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to a first embodiment of the present invention.

8A through 8B are schematic cross-sectional views showing a method of fabricating a semiconductor structure in accordance with a second embodiment of the present invention.

100‧‧‧Base

102a‧‧‧First District

102b‧‧‧Second District

102c‧‧‧ Third District

104‧‧‧ epitaxial layer

106‧‧‧ body layer

107‧‧‧Oxide layer

108‧‧‧first gate

109‧‧‧Polysilicon layer

110‧‧‧second gate

112‧‧‧ dielectric layer

113‧‧‧Barrier layer

114‧‧‧First contact window

115‧‧‧metal layer

116‧‧‧Second contact window

118‧‧‧First doped area

120‧‧‧metal layer

122‧‧‧Second doped area

Claims (31)

  1. A semiconductor structure comprising: a substrate having a first conductivity type, the substrate having a first region, a second region, and a third region, wherein the second region is located in the first region and the third region Having an epitaxial layer of the first conductivity type disposed on the substrate; and having a body layer of a second conductivity type disposed in the epitaxial layer of the first region and the second region; a first gate and a second gate disposed in the body layer and a portion of the epitaxial layer other than the body layer, wherein the first gate is located in a portion of the first region and a portion of the second region, and The second gate is located in a portion of the second region and a portion of the third region; a first contact window is disposed in a portion of the body portion of the first region; and a second contact window is disposed at least in the third region And contacting the epitaxial layer and the second gate in the epitaxial layer, wherein the first contact window is electrically connected to the second contact window; and having the first doping of the first conductivity type a region disposed in the body layer between the first contact window and the first gate.
  2. The semiconductor structure of claim 1, wherein the second contact window is embedded in the second gate.
  3. The semiconductor structure of claim 1, wherein the second contact window is disposed in the epitaxial layer of the third region and a portion of the second region, and the second gate is located in the second contact window Below.
  4. a semiconductor structure as described in claim 3, wherein the The body layer of the second zone covers the sidewalls and a portion of the bottom of the second contact window.
  5. The semiconductor structure of claim 1, further comprising a second doped region having the second conductivity type disposed on a bottom portion and a portion of the sidewall of the first contact window.
  6. The semiconductor structure of claim 1, further comprising: a dielectric layer disposed on the substrate and exposing the first contact window and the second contact window; and a metal layer disposed on the substrate And covering the dielectric layer, the first contact window and the second contact window.
  7. The semiconductor structure of claim 1, wherein the first contact window and the second contact window respectively comprise a first metal layer and a barrier layer located around the first metal layer.
  8. The semiconductor structure of claim 7, wherein the material of the first metal layer comprises tungsten.
  9. The semiconductor structure of claim 6, wherein the material of the metal layer comprises aluminum beryllium copper.
  10. The semiconductor structure of claim 1, wherein the first conductivity type is N type, the second conductivity type is P type; or the first conductivity type is P type, and the second conductivity type is N type .
  11. The semiconductor structure of claim 1, wherein the semiconductor structure has a cell pitch of 1.5 μm or less.
  12. The semiconductor structure of claim 1, wherein the semiconductor structure has a cell density greater than or equal to 3 x 10 8 cells per square inch.
  13. The semiconductor structure of claim 6, wherein the second gate is equipotential to the metal layer.
  14. The semiconductor structure of claim 1, wherein the first region surrounds the second region and the second region surrounds the third region.
  15. The semiconductor structure of claim 6, further comprising at least one third gate disposed in the epitaxial layer of the third region and below the second contact window.
  16. The semiconductor structure of claim 15, wherein the third gate is equipotential to the metal layer.
  17. A semiconductor structure comprising: a substrate having a first region, a second region, and a third region, wherein the second region is between the first region and the third region; at least one power metal oxygen a semiconductor field effect transistor disposed in the first region; a floating diode or a body diode disposed in the second region; and at least one Schottky diode disposed in the third region The first contact window of the power MOS field effect transistor and the second contact window of the Schottky diode are electrically connected to each other through a metal layer, and the first contact window is disposed on the substrate The semiconductor structure further includes a gate, the gate is located in the portion of the second region and a portion of the third region, and the gate is in contact with the second contact window.
  18. The semiconductor structure of claim 17, wherein the first region surrounds the second region and the second region surrounds the third region.
  19. The semiconductor structure of claim 17, wherein the semiconductor structure has a cell pitch of 1.5 μm or less.
  20. The semiconductor structure of claim 17, wherein the semiconductor structure has a cell density greater than or equal to 3 x 10 8 cells per square inch.
  21. A method of fabricating a semiconductor structure, comprising: providing a substrate having a first conductivity type, the substrate having a first region, a second region, and a third region, wherein the second region is located in the first region and Between the third regions, an epitaxial layer having the first conductivity type is formed on the substrate; a first gate and a second gate are formed in the epitaxial layer, wherein the first gate is located in the portion In the first region and a portion of the second region, the second gate is located in a portion of the second region and a portion of the third region; and formed in the epitaxial layer of the first region and the second region a body layer of a second conductivity type; forming a first doped region having the first conductivity type in the body layer of the first region; forming a dielectric layer on the substrate to expose the first layer a portion of the first doped region, at least the epitaxial layer of the third region, and at least a portion of the second gate; removing the portion of the first doped region and the portion by using the dielectric layer as a mask The epitaxial layer and a portion of the second gate for the first doped region of the first region And forming a first opening in the portion of the body layer outside the first doped region, and forming a second opening in the epitaxial layer of the third region and a portion of the second gate; a first metal layer is formed in the first opening and the second opening, and a first contact window and a second contact window are respectively formed in the first opening and the second opening, and the second gate and the second gate The second contact window contacts; and a second metal layer is formed on the substrate to cover the dielectric layer and the first metal layer.
  22. The method of fabricating a semiconductor structure according to claim 21, wherein the dielectric layer exposes a portion of the first region, the first doped region, the epitaxial layer of the third region, and the entire second a gate and a portion of the body portion of the second region.
  23. The method for fabricating a semiconductor structure according to claim 21, further comprising the first opening after the step of forming the first opening and the second opening and before the step of filling the first metal layer A second doped region having one of the second conductivity types is formed at the bottom.
  24. The method for fabricating a semiconductor structure according to claim 23, further comprising the first opening and the second after the step of forming the second doping region and before the step of filling the first metal layer A barrier layer is formed in the opening.
  25. The method of fabricating a semiconductor structure according to claim 21, wherein the material of the first metal layer comprises tungsten.
  26. The method of fabricating a semiconductor structure according to claim 21, wherein the material of the second metal layer comprises aluminum beryllium copper.
  27. The method of fabricating a semiconductor structure according to claim 21, wherein the first conductivity type is N type, the second conductivity type is P type; or the first conductivity type is P type, the second conductivity type It is N type.
  28. The method of fabricating a semiconductor structure according to claim 21, wherein the second gate is equipotential to the second metal layer.
  29. The method of fabricating a semiconductor structure according to claim 21, wherein the first region surrounds the second region, and the second region surrounds the third region.
  30. The method for fabricating a semiconductor structure according to claim 21, wherein the step of forming the first gate and the second gate in the epitaxial layer further comprises the epitaxial layer in the third region At least one third gate is formed in the middle.
  31. The method of fabricating a semiconductor structure according to claim 30, wherein the third gate is equipotential to the second metal layer.
TW98124896A 2009-07-23 2009-07-23 Semiconductor struture and method of formipg the same TWI394263B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621107B2 (en) * 2001-08-23 2003-09-16 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621107B2 (en) * 2001-08-23 2003-09-16 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier

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