TWI393513B - Embedded circuit board and fabricating method thereof - Google Patents

Description

Buried circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to an embedded circuit board and a method of fabricating the same.

In recent years, with the rapid advancement of the production technology of the electronics industry, circuit boards can be equipped with various electronic components to be widely used in various electronic products with different functions. At present, electronic products are developing in the direction of multi-functionality and miniaturization. Under this trend, the circuit substrate needs to greatly increase its wiring density to carry more and more precise electronic components. To this end, the prior art proposes an embedded circuit board having a high wiring density.

A conventional method of manufacturing a buried wiring board is as follows. First, the circuit layer is formed on a circuit carrier by an additive method. Then, the line carrier board, a circuit board, and a dielectric layer disposed between the board and the circuit board are pressed so that the circuit layer on the line carrier board and the circuit layer of the circuit board are buried in the dielectric layer respectively. Relative to the two sides. After that, remove the line carrier. It is worth mentioning that when the fine line is formed by the addition method, the line width quality requirement cannot be achieved due to the limited analysis capability of the photoresist image transfer. In order to overcome the foregoing problems, the prior art proposes a method of first laser etching a dielectric layer to form a groove pattern on the dielectric layer and then forming a circuit layer in the groove pattern. However, the laser etching method cannot uniformly form a large-area copper surface such as a pad.

The present invention provides a method of fabricating a buried wiring board in which a wiring layer having a large area of copper surface and a conductive pattern having fine lines can be formed in one side of the dielectric layer.

The present invention provides a buried circuit board having a wiring layer having a large area of copper surface and a conductive pattern having fine lines embedded in one side of the dielectric layer, and having conductive bumps inserted into the dielectric layer To electrically connect different circuit layers.

The invention provides a method for manufacturing a buried circuit board as follows. First, a line carrier is provided. The line carrier includes a carrier layer and a first circuit layer disposed on the carrier layer. Then, a conductive bump is formed on the at least one first pad of the first circuit layer, wherein the minimum diameter of the first pad is substantially greater than or equal to 100 micrometers. Then, a circuit substrate and a dielectric layer are provided. The circuit substrate includes a base layer and a second circuit layer disposed on the base layer, and the dielectric layer is disposed between the first circuit layer and the second circuit layer. Thereafter, the line carrier, the dielectric layer and the circuit substrate are pressed, and the conductive bumps are inserted through the dielectric layer and directly contact with a second pad of the second circuit layer, and the first circuit layer and the second circuit layer are They are respectively embedded in a first side and a second side of the opposite side of the dielectric layer, wherein the minimum diameter of the second pads is substantially greater than or equal to 100 micrometers. The carrier layer is then removed. Thereafter, a trench pattern is formed on the dielectric layer. Then, a first conductive pattern is formed in the trench pattern, and the first conductive pattern is electrically connected to the first circuit layer.

In an embodiment of the present invention, the circuit carrier further includes a second conductive pattern disposed on the carrier layer, wherein the second conductive pattern has a minimum diameter of substantially greater than or equal to 100 micrometers, and the circuit substrate further includes a base layer. a third conductive pattern, the minimum diameter of the third conductive pattern is substantially greater than or equal to 100 microns, and when the line carrier, the dielectric layer and the circuit substrate are pressed, the second conductive pattern and the third conductive pattern are respectively Buried in the first side and the second side of the dielectric layer.

In an embodiment of the invention, the conductive bump is a tapered conductive bump, and when the line carrier, the dielectric layer and the circuit substrate are pressed, the tip of the conductive bump pierces the dielectric layer and Direct contact with the second pad of the second circuit layer.

In an embodiment of the invention, the conductive bump is a columnar conductive bump.

In an embodiment of the invention, the conductive bump is made of copper, silver, aluminum or tin.

In one embodiment of the invention, a method of forming a trench pattern includes laser etching.

In one embodiment of the invention, the dielectric layer is doped with a plurality of catalyst particles.

In an embodiment of the invention, the catalyst particles are selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles, and metal complex particles, or are selected from the group consisting of A group consisting of manganese, chromium, palladium, copper, aluminum, zinc, silver, gold, nickel, cobalt, ruthenium, osmium, iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum.

In an embodiment of the invention, the line carrier further includes a termination layer disposed on the carrier layer and between the carrier layer and the first circuit layer.

In an embodiment of the invention, the method further includes removing the termination layer after removing the carrier layer and before forming the trench pattern.

In an embodiment of the invention, the trench pattern penetrates the termination layer while forming the trench pattern, and the method of forming the first conductive pattern includes forming a conductive layer covering the trench pattern and the termination layer, and removing the termination The portion of the layer and the conductive layer on the termination layer.

In an embodiment of the invention, the material of the termination layer comprises tin, aluminum, gold, nickel, chromium, titanium or zinc.

The invention provides a method for manufacturing a buried circuit board as follows. First, a circuit carrier, a dielectric layer, a plurality of conductive bumps, and a circuit substrate are provided. The circuit carrier includes a carrier layer and a first circuit layer disposed on the carrier layer, and the conductive bumps penetrate the dielectric layer. The circuit substrate includes a base layer and a second circuit layer disposed on the base layer, and the dielectric layer is disposed between the first circuit layer and the second circuit layer. Then, pressing the line carrier, the dielectric layer and the circuit substrate, and connecting the conductive bumps between the plurality of first pads of the first circuit layer and the plurality of second pads of the second circuit layer, and The first circuit layer and the second circuit layer are respectively buried in opposite sides of the dielectric layer. The minimum diameter of the first pad is substantially greater than or equal to 100 microns, and the minimum diameter of the second pad is substantially greater than or equal to 100 microns. The carrier layer is then removed. Thereafter, a trench pattern is formed on the dielectric layer. Then, a first conductive pattern is formed in the trench pattern, and the first conductive pattern is electrically connected to the first circuit layer.

In an embodiment of the present invention, the circuit carrier further includes a second conductive pattern disposed on the carrier layer, wherein the second conductive pattern has a minimum diameter of substantially greater than or equal to 100 micrometers, and the circuit substrate further includes a base layer. a third conductive pattern, the minimum diameter of the third conductive pattern is substantially greater than or equal to 100 microns, and when the line carrier, the dielectric layer and the circuit substrate are pressed, the second conductive pattern and the third conductive pattern are respectively Buried in the first side and the second side of the dielectric layer.

In an embodiment of the invention, the conductive bump is a tapered conductive bump or a columnar conductive bump.

In an embodiment of the invention, the conductive bump is made of copper, silver, aluminum or tin.

In one embodiment of the invention, a method of forming a trench pattern includes laser etching.

In one embodiment of the invention, the dielectric layer is doped with a plurality of catalyst particles.

In an embodiment of the invention, the catalyst particles are selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles, and metal complex particles, or are selected from the group consisting of A group consisting of manganese, chromium, palladium, copper, aluminum, zinc, silver, gold, nickel, cobalt, ruthenium, osmium, iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum.

In an embodiment of the invention, the line carrier further includes a termination layer disposed on the carrier layer and between the carrier layer and the first circuit layer.

In an embodiment of the invention, the method further includes removing the termination layer after removing the carrier layer and before forming the trench pattern.

In an embodiment of the invention, the trench pattern penetrates the termination layer while forming the trench pattern, and the method of forming the first conductive pattern includes forming a conductive layer covering the trench pattern and the termination layer, and removing the termination The portion of the layer and the conductive layer on the termination layer.

In an embodiment of the invention, the material of the termination layer comprises tin, aluminum, gold, nickel, chromium, titanium or zinc.

The invention provides a buried circuit board comprising a circuit substrate, a dielectric layer, a second circuit layer and a plurality of conductive bumps. The circuit substrate includes a base layer and a first circuit layer disposed on the base layer. The dielectric layer is disposed on the circuit substrate, and the first circuit layer is buried in one of the first sides of the dielectric layer. The second wiring layer is buried in one of the second sides of the dielectric layer, and the second side is opposite to the first side. The conductive bump is inserted into the dielectric layer and connected between the plurality of first pads of the first circuit layer and the plurality of second pads of the second circuit layer, wherein the minimum diameter of each of the first pads is substantially greater than Or equal to 100 microns, the minimum diameter of each second pad is substantially greater than or equal to 100 microns.

In an embodiment of the invention, the circuit substrate further includes a first conductive pattern disposed on the base layer and embedded in the first side of the dielectric layer, the minimum diameter of the first conductive pattern being substantially The buried circuit board further includes a second conductive pattern buried in the second side of the dielectric layer, and the second conductive pattern has a minimum diameter substantially greater than or equal to 100 micrometers.

In an embodiment of the invention, the conductive bump is a tapered conductive bump, and the tip end of the conductive bump penetrates into the dielectric layer from the first side and directly contacts the first circuit layer.

In an embodiment of the invention, the conductive bump is a columnar conductive bump.

In an embodiment of the invention, the conductive bump is made of copper, silver, aluminum or tin.

In one embodiment of the invention, the dielectric layer is doped with a plurality of catalyst particles.

In an embodiment of the invention, the catalyst particles are selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles, and metal complex particles, or are selected from the group consisting of A group consisting of manganese, chromium, palladium, copper, aluminum, zinc, silver, gold, nickel, cobalt, ruthenium, osmium, iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum.

Based on the above, the present invention first laminates a wiring having a large area of copper surface such as a pad into a dielectric layer, and then forms a groove pattern on the dielectric layer and forms a thin line in the groove pattern. Conductive pattern. Therefore, the method for fabricating the buried wiring board of the present invention can overcome the problem that the thin line formed by the additive method has poor wire width and good quality in the prior art, and the laser etching method cannot uniformly form a large area such as a pad. The problem of the copper surface.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1F are cross-sectional views showing processes of an embedded circuit board according to an embodiment of the present invention.

First, referring to FIG. 1A, a circuit carrier 110 is provided. The circuit carrier 110 includes a carrier layer 112, a circuit layer 114, a termination layer 116, and a conductive pattern 118. The circuit layer 114 and the conductive pattern 118 are disposed on the carrier. On layer 112, termination layer 116 is between carrier layer 112 and circuit layer 114. The material of the termination layer 116 is, for example, tin, aluminum, gold, nickel, chromium, titanium or zinc. In this embodiment, the minimum diameter of the conductive pattern 118 is substantially greater than or equal to 100 microns. The conductive pattern 118 is, for example, a ground pattern, a power supply pattern, or other large-area conductive patterns. In this embodiment, the method of forming the wiring layer 114 and the conductive pattern 118 is, for example, first forming a patterned mask layer (not shown) on the termination layer 116, and then performing an electroplating process to terminate the layer 116. The wiring layer 114 and the conductive pattern 118 are formed on portions exposed outside the patterned mask layer, and then the patterned mask layer is removed. In other words, the method of forming the wiring layer 114 and the conductive pattern 118 is, for example, an additive method. In other embodiments, the method of forming the wiring layer 114 and the conductive pattern 118 is, for example, first forming a conductive layer (not shown) on the termination layer 116, and then forming a patterned mask layer on the conductive layer (not The etching process is then performed to remove portions of the conductive layer that are exposed outside the patterned mask layer and form the wiring layer 114, after which the patterned mask layer is removed. In other words, the method of forming the wiring layer 114 is, for example, a subtractive method.

Next, referring to FIG. 1B, a plurality of conductive bumps 120 are respectively formed on the plurality of pads 114a of the circuit layer 114, wherein the minimum diameter of the pads 114a is substantially greater than or equal to 100 micrometers. In this embodiment, the conductive bumps 120 are, for example, a tapered conductive bump, a columnar conductive bump, a spherical conductive bump, a semi-spherical conductive bump, or other conductive bumps having a suitable shape. The material of the conductive bump 120 is, for example, copper, silver, aluminum, tin or other suitable conductive material.

Then, referring to FIG. 1C, a circuit substrate 130 and a dielectric layer 140 are provided. The circuit substrate 130 includes a base layer 132, a circuit layer 134 disposed on the base layer 132, and a conductive pattern 136. The dielectric layer 140 is disposed on the circuit. Between layer 114 and circuit layer 134. In the present embodiment, the minimum diameter of the conductive pattern 136 is substantially greater than or equal to 100 microns. The conductive pattern 136 is, for example, a ground pattern, a power supply pattern, or other large-area conductive patterns. In this embodiment, the dielectric layer 140 may be doped with a plurality of catalyst particles (not shown), which are suitable for laser activation, and may be activated by a surface metallization process after laser activation. A metal layer is formed on the catalyst particles. The catalyst particles may be selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles, and metal complex particles, or selected from the group consisting of manganese, chromium, palladium, copper, and aluminum. a group consisting of zinc, silver, gold, nickel, cobalt, ruthenium, osmium, iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum. In other embodiments, the dielectric layer 140 can also be an ABF film (Ajinomoto build-up film).

1D, the wiring carrier 110, the dielectric layer 140 and the circuit substrate 130 are pressed, and the conductive bumps 120 are inserted through the dielectric layer 140 and directly contact with a pad 134a of the circuit layer 134. The circuit layer 114 The conductive pattern 118 is buried in the first side 142 of the dielectric layer 140. The circuit layer 134 and the conductive pattern 136 are buried in the second side 144 of the dielectric layer 140, wherein the first side 142 is opposite to the second side. Side 144. The minimum diameter of the pads 134a is substantially greater than or equal to 100 microns. At this time, if the conductive bump 120 is a tapered conductive bump, the tip end 122 of the conductive bump 120 can pierce the dielectric layer 140 and directly contact the pad 134a of the circuit layer 134.

Then, referring to FIG. 1E, the carrier layer 112 is removed. Next, the termination layer 116 is removed, for example, by etching, and the wiring layer 114 and the conductive pattern 118 are exposed. Thereafter, referring to FIG. 1F, a trench pattern 146 is formed on the dielectric layer 140 by, for example, laser etching. Then, a conductive pattern 150 is formed in the trench pattern 146, and the conductive pattern 150 is electrically connected to the circuit layer 114. It is worth noting that when the dielectric layer 140 is doped with catalyst particles, the catalyst particles exposed by the groove pattern will be activated by the laser. Therefore, a surface metallization process can be performed for laser activation. A conductive pattern 150 is formed on the subsequent catalyst particles.

In addition, in other embodiments not shown, when the dielectric layer is an ABF film, the manner of forming the conductive pattern 150 is, for example, electroplating. In detail, after removing the carrier layer, the termination layer may be left and a trench pattern is formed on the termination layer and the dielectric layer by, for example, laser etching, wherein the trench pattern penetrates the termination layer and is trapped in the dielectric layer In the first side. Then, a conductive layer is formed on the termination layer and the dielectric layer by, for example, electroplating. Thereafter, the portion of the conductive layer on the termination layer and the termination layer are removed, and portions of the conductive layer located in the trench pattern are left to form a conductive pattern.

As described above, in this embodiment, a buried wiring layer 114 is first formed on the dielectric layer 140 by, for example, an additive method (or a subtractive method), and then, after the bonding is completed and removed. After the carrier layer 112, a trench pattern 146 is formed on the dielectric layer 140 by, for example, laser etching, and a conductive pattern 150 is formed in the trench pattern 146. Therefore, in the present embodiment, the wiring layer 114 having a large-area copper surface such as the pads 114a and the conductive pattern 150 having fine lines are respectively formed by an additive method (or a subtractive method) and a laser etching method. In this way, the method for fabricating the buried circuit board of the present embodiment can overcome the problem that the thin circuit formed by the additive method has poor wire width and poor quality, and the laser etching method cannot uniformly form the pad. The problem of large areas of copper.

The structural portion of the buried wiring board 100 in Fig. 1F will be described in detail below.

Referring to FIG. 1F , the buried circuit board 100 of the present embodiment includes a circuit substrate 130 , a dielectric layer 140 , a circuit layer 114 , and a plurality of conductive bumps 120 . The circuit substrate 130 includes a base layer 132 and a wiring layer 134 disposed on the base layer 132 and a conductive pattern 136. The dielectric layer 140 is disposed on the circuit substrate 130 , and the dielectric layer 140 has a first side 142 and a second side 144 . The circuit layer 134 and the conductive pattern 136 are buried in the second side 144 of the dielectric layer 140. The circuit layer 114 and the conductive pattern 118 are buried in the first side 142 of the dielectric layer 140. In this embodiment, the minimum diameter of the conductive patterns 118, 136 is substantially greater than or equal to 100 microns.

In this embodiment, the dielectric layer 140 may be doped with a plurality of catalyst particles (not shown) suitable for laser activation, and the catalyst particles are, for example, selected from the group consisting of metal oxide particles and metal nitrides. a group consisting of particles, metal chelate particles and metal complex particles, or selected from the group consisting of manganese, chromium, palladium, copper, aluminum, zinc, silver, gold, nickel, cobalt, ruthenium, osmium, iron a group consisting of molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum. In other embodiments, the dielectric layer 140 is, for example, an ABF film.

The conductive bumps 120 are inserted into the dielectric layer 140 and connected between the plurality of pads 134a of the circuit layer 134 and the plurality of pads 114a of the circuit layer 114, wherein the minimum diameter of the pads 114a is substantially greater than or equal to 100 micrometers. The minimum diameter of the pad 134a is substantially greater than or equal to 100 microns. In the present embodiment, the conductive bumps 120 are, for example, a tapered conductive bumps. The tips 122 of the conductive bumps 120 are pierced into the dielectric layer 140 by the first side 142 and directly contact the circuit layer 134. In other embodiments, the conductive bumps 120 are, for example, a columnar conductive bump. The material of the conductive bumps 120 is, for example, copper, silver, aluminum, tin or other suitable conductive materials.

2A-2D are cross-sectional views showing processes of an embedded circuit board according to an embodiment of the present invention.

First, referring to FIG. 2A, a circuit carrier 110, a dielectric layer 140, a plurality of conductive bumps 210, and a circuit substrate 130 are provided. The circuit carrier 110 includes a carrier layer 112, a circuit layer 114, a termination layer 116, and a conductive pattern 118. The circuit layer 114 and the conductive pattern 118 are disposed on the carrier layer 112, and the termination layer 116 is located on the carrier layer 112 and the circuit layer. Between 114. The circuit substrate 130 includes a base layer 132 and a wiring layer 134 disposed on the base layer 132 and a conductive pattern 136. In this embodiment, the minimum diameter of the conductive patterns 118, 136 is substantially greater than or equal to 100 microns.

The dielectric layer 140 is disposed between the circuit layer 114 and the wiring layer 134 , and the conductive bumps 210 penetrate the dielectric layer 140 . In more detail, the conductive bumps 210 may be located between the pads 114a of the circuit layer 114 and the pads 134a of the circuit layer 134, wherein the minimum diameter of the pads 114a is substantially greater than or equal to 100 microns, and the minimum of the pads 134a The diameter is substantially greater than or equal to 100 microns. The conductive bumps 210 are, for example, a tapered conductive bump, a columnar conductive bump, or a conductive bump having other suitable shapes. The material of the conductive bump 210 is, for example, copper, silver, aluminum, tin or other suitable conductive material.

It should be noted that, in this embodiment, the structure and material of the circuit carrier 110, the dielectric layer 140, and the circuit substrate 130 and the structure and material of the circuit carrier 110, the dielectric layer 140, and the circuit substrate 130 in FIG. 1C. The same, so I won't go into details here.

Next, referring to FIG. 2B, the line carrier 110, the dielectric layer 140, and the circuit substrate 130 are laminated, and the conductive bumps 210 are connected between the circuit layer 114 and the wiring layer 134, and the wiring layer 114 and the conductive pattern 118 are connected. Buried in one of the first sides 142 of the dielectric layer 140, the wiring layer 134 and the conductive pattern 136 are buried in the second side 144 of one of the dielectric layers 140, wherein the first side 142 is opposite to the second side 144.

Then, referring to FIG. 2C, the carrier layer 112 is removed. Next, the termination layer 116 is removed, for example, by etching, and the wiring layer 114 and the conductive pattern 118 are exposed. Thereafter, referring to FIG. 2D, a trench pattern 146 is formed on the dielectric layer 140 by, for example, laser etching. Then, a conductive pattern 150 is formed in the trench pattern 146, and the conductive pattern 150 is electrically connected to the circuit layer 114. It should be noted that when the dielectric layer 140 is doped with catalyst particles (not shown), the catalyst particles exposed by the groove pattern will be activated by the laser, and therefore, a surface metallization process can be performed. A conductive pattern 150 is formed on the catalyst particles after laser activation.

In addition, in other embodiments not shown, when the dielectric layer is an ABF film, the manner of forming the conductive pattern 150 is, for example, electroplating. In detail, after removing the carrier layer, the termination layer may be left and a trench pattern is formed on the termination layer and the dielectric layer by, for example, laser etching, wherein the trench pattern penetrates the termination layer and is trapped in the dielectric layer In the first side. Then, a conductive layer is formed on the termination layer and the dielectric layer by, for example, electroplating. Thereafter, the portion of the conductive layer on the termination layer and the termination layer are removed, and portions of the conductive layer located in the trench pattern are left to form a conductive pattern.

In summary, the present invention firstly laminates a metal line having a large area such as a pad into a dielectric layer, and then forms a groove pattern on the dielectric layer and forms a thin line in the groove pattern. Conductive pattern. Therefore, the method for fabricating the buried wiring board of the present invention can overcome the poor quality of the thin line formed by the additive method in the prior art, and the large area of the metal such as the pad cannot be uniformly formed by the laser etching method. Technical bottlenecks at the circuit layer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Buried circuit board

110. . . Line carrier

112. . . Carrier layer

114. . . Circuit layer

114a, 134a. . . Pad

116. . . Termination layer

118, 136, 150. . . Conductive pattern

120, 210. . . Conductive bump

122. . . Cutting edge

130. . . Circuit substrate

132. . . Grassroots

134. . . Circuit layer

140. . . Dielectric layer

142. . . First side

144. . . Second side

146. . . Groove pattern

1A-1F are cross-sectional views showing processes of an embedded circuit board according to an embodiment of the present invention.

2A-2D are cross-sectional views showing processes of an embedded circuit board according to an embodiment of the present invention.

100. . . Buried circuit board

114, 134. . . Circuit layer

114a, 134a. . . Pad

118, 136, 150. . . Conductive pattern

120. . . Conductive bump

122. . . Cutting edge

130. . . Circuit substrate

132. . . Grassroots

140. . . Dielectric layer

142. . . First side

144. . . Second side

146. . . Groove pattern

Claims (32)

A method for fabricating a buried circuit board, comprising: providing a circuit carrier board, comprising a carrier layer and a first circuit layer disposed on the carrier layer; and at least one first pad on the first circuit layer Forming a conductive bump, wherein the first pad has a minimum diameter of substantially greater than or equal to 100 micrometers; providing a circuit substrate and a dielectric layer, the circuit substrate comprising a base layer and a second disposed on the base layer a circuit layer disposed between the first circuit layer and the second circuit layer; pressing the circuit carrier, the dielectric layer and the circuit substrate, and passing the conductive bump through the dielectric layer And directly contacting a second pad of the second circuit layer, and embedding the first circuit layer and the second circuit layer respectively in a first side and a second side of the dielectric layer Wherein the second pad has a minimum diameter substantially greater than or equal to 100 microns; and removing the carrier layer; forming a trench pattern on the dielectric layer; and forming a first conductive layer in the trench pattern a pattern, and the first conductive pattern and the first circuit layer are electrically Connection. The method for fabricating a buried circuit board according to the first aspect of the invention, wherein the circuit carrier further comprises a second conductive pattern disposed on the carrier layer, the minimum diameter of the second conductive pattern being substantially The circuit substrate further includes a third conductive pattern disposed on the base layer, and the minimum diameter of the third conductive pattern is substantially greater than or equal to 100 μm, and when the line carrier, the dielectric layer and the circuit substrate are pressed together, the second conductive pattern and the third conductive pattern are respectively buried in the first side and the second side of the dielectric layer Side. The method for manufacturing a buried circuit board according to the first or the second aspect of the invention, wherein the conductive bump is a tapered conductive bump, and when the line carrier, the dielectric layer is pressed In the circuit substrate, the tip of the conductive bump pierces the dielectric layer and is in direct contact with the second pad of the second circuit layer. The method for manufacturing a buried circuit board according to the first or second aspect of the invention, wherein the conductive bump is a columnar conductive bump. The method for manufacturing a buried circuit board according to the first or the second aspect of the invention, wherein the conductive bump is made of copper, silver, aluminum or tin. The method of fabricating a buried wiring board according to claim 1 or 2, wherein the method of forming the trench pattern comprises laser etching. The method for fabricating a buried wiring board according to claim 6, wherein the dielectric layer is doped with a plurality of catalyst particles. The method for fabricating a buried wiring board according to claim 7, wherein the catalyst particles are selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles and metal complexes. A group of particles. The method for fabricating a buried wiring board according to claim 7, wherein the catalyst particles are selected from the group consisting of manganese, chromium, palladium, copper, A group consisting of aluminum, zinc, silver, gold, nickel, cobalt, ruthenium, osmium, iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum. The method for manufacturing a buried circuit board according to the above or the second aspect of the invention, wherein the circuit carrier further comprises a termination layer disposed on the carrier layer and located on the carrier layer Between the first circuit layers. The method for fabricating a buried wiring board according to claim 10, further comprising: removing the termination layer after removing the carrier layer and before forming the trench pattern. The method of fabricating a buried wiring board according to claim 10, wherein the trench pattern penetrates the termination layer while forming the trench pattern, and the method of forming the first conductive pattern comprises: forming a conductive layer covering the trench pattern and the termination layer; and removing the termination layer and a portion of the conductive layer on the termination layer. The method for fabricating a buried circuit board according to claim 10, wherein the material of the termination layer comprises tin, aluminum, gold, nickel, chromium, titanium or zinc. A method for fabricating a buried circuit board includes: providing a circuit carrier, a dielectric layer, a plurality of conductive bumps, and a circuit substrate, wherein the circuit carrier includes a carrier layer and a carrier layer disposed on the carrier layer a first circuit layer, the conductive bumps penetrating the dielectric layer, the circuit substrate comprising a base layer and a second circuit layer disposed on the base layer, and the a dielectric layer is disposed between the first circuit layer and the second circuit layer; press-bonding the circuit carrier, the dielectric layer, and the circuit substrate, and connecting the conductive bumps to the first circuit layer Between the plurality of first pads and the plurality of second pads of the second circuit layer, and the first circuit layer and the second circuit layer are respectively buried in opposite sides of the dielectric layer, wherein The minimum diameter of each of the first pads is substantially greater than or equal to 100 micrometers, and the minimum diameter of each of the second pads is substantially greater than or equal to 100 micrometers; the carrier layer is removed; and a dielectric layer is formed on the dielectric layer a trench pattern; and forming a first conductive pattern in the trench pattern, and the first conductive pattern is electrically connected to the first circuit layer. The method of fabricating a buried circuit board according to claim 14, wherein the circuit carrier further comprises a second conductive pattern disposed on the carrier layer, the minimum diameter of the second conductive pattern being substantially The circuit substrate further includes a third conductive pattern disposed on the base layer, the third conductive pattern having a minimum diameter substantially greater than or equal to 100 micrometers, and when the line carrier is pressed, During the dielectric layer and the circuit substrate, the second conductive pattern and the third conductive pattern are respectively buried in the first side and the second side of the dielectric layer. The method for manufacturing a buried circuit board according to claim 14 or 15, wherein the conductive bump is a tapered conductive bump or a columnar conductive bump. The method for manufacturing a buried circuit board according to claim 14 or 15, wherein the conductive bump is made of copper, silver or aluminum. Or tin. The method of fabricating a buried wiring board according to claim 14 or 15, wherein the method of forming the trench pattern comprises laser etching. The method for fabricating a buried wiring board according to claim 18, wherein the dielectric layer is doped with a plurality of catalyst particles. The method for fabricating a buried wiring board according to claim 19, wherein the catalyst particles are selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles and metal complexes. A group of particles. The method for fabricating a buried wiring board according to claim 19, wherein the catalyst particles are selected from the group consisting of manganese, chromium, palladium, copper, aluminum, zinc, silver, gold, nickel, cobalt, A group consisting of ruthenium, osmium, iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum. The method for fabricating a buried circuit board according to claim 14 or 15, wherein the circuit carrier further comprises a termination layer disposed on the carrier layer and located on the carrier layer Between the first circuit layers. The method for fabricating a buried wiring board according to claim 22, further comprising: removing the termination layer after removing the carrier layer and before forming the trench pattern. The method for fabricating a buried wiring board according to claim 22, wherein the groove pattern is formed while forming the groove pattern The termination layer is formed, and the method of forming the first conductive pattern includes: forming a conductive layer covering the trench pattern and the termination layer; and removing the termination layer and a portion of the conductive layer on the termination layer. The method for fabricating a buried circuit board according to claim 22, wherein the material of the termination layer comprises tin, aluminum, gold, nickel, chromium, titanium or zinc. An embedded circuit board includes: a circuit substrate comprising a base layer and a first circuit layer disposed on the base layer; and a first conductive pattern, wherein a minimum diameter of the first conductive pattern is substantially greater than or equal to 100 micrometers; a dielectric layer disposed on the circuit substrate, wherein the first circuit layer and the first conductive pattern are buried in a first side of the dielectric layer; and a second circuit layer is embedded in the first circuit layer a second side of the dielectric layer, and the second side is opposite to the first side; a plurality of conductive bumps, a plurality of first pads inserted into the dielectric layer and connected to the first circuit layer Between the plurality of second pads of the second circuit layer, wherein the minimum diameter of each of the first pads is substantially greater than or equal to 100 micrometers, and the minimum diameter of each of the second pads is substantially greater than or equal to 100 micrometers; and a second conductive pattern buried in the second side of the dielectric layer, wherein the second conductive pattern has a minimum diameter substantially greater than or equal to 100 micrometers. For example, the buried circuit board described in claim 26 of the patent scope, The conductive bump is a tapered conductive bump, and the tip end of the conductive bump penetrates into the dielectric layer from the first side and directly contacts the first circuit layer. The buried circuit board of claim 26, wherein the conductive bump is a columnar conductive bump. The buried circuit board of claim 26, wherein the conductive bump is made of copper, silver, aluminum or tin. The buried circuit board of claim 26, wherein the dielectric layer is doped with a plurality of catalyst particles. The buried circuit board according to claim 30, wherein the catalyst particles are selected from the group consisting of metal oxide particles, metal nitride particles, metal chelate particles and metal complex particles. Group. The buried circuit board according to claim 30, wherein the catalyst particles are selected from the group consisting of manganese, chromium, palladium, copper, aluminum, zinc, silver, gold, nickel, cobalt, rhodium, ruthenium. a group of iron, molybdenum, tungsten, vanadium, niobium, indium, titanium, and platinum.