TWI393258B - Field effect transistor with indium aluminum gallium / gallium arsenide hump gate - Google Patents

Description

Field effect transistor with indium aluminum gallium phosphide/gallium arsenide gate

The invention relates to a field effect transistor with an indium aluminum gallium phosphide/gallium arsenide gate, in particular a high electron mobility transistor using a Helium gate of an InAlGaP/GaAs heterojunction.

Compared with germanium wafers, gallium arsenide materials have high electron mobility, high electron saturation speed and high impedance characteristics, so they have been widely used in high frequency circuits and microwave communication circuits. So far, in the development of heterostructure transistor elements of GaAs systems, AlGaAs/GaAs is still the mainstream. However, in recent years, the InGaP/GaAs series of heterostructure field effect transistors have gradually attracted attention, and have quite good development results, because InGaP has the following characteristics compared with AlGaAs materials:

(1) The energy gap of the regularly arranged InGaP is 1.85 eV, and the irregularly arranged InGaP energy gap is 1.9 eV, and the values are all larger than the energy gap of Al _0.3 Ga _0.7 As (1.7 eV).

(2) InGaP-free AlGaAs is susceptible to oxidation and DX center problems.

(3) InGaP has a lower surface recombination rate, resulting in lower 1/f noise.

(4) The etching solution used has a high selectivity to GaAs and InGaP, so that the yield and uniformity can be greatly improved.

In the literature related to heterojunction field effect transistors, the earliest is the traditional n ⁺ -GaAs/p ⁺ -GaAs/n-GaAs camel-type gate homojunction field-effect transistor, followed by the modified n ⁺ - The GaAs/p ⁺ -InGaP/n-GaAs camel-type gate heterojunction field effect transistor is a heterostructure n ⁺ -GaAs/p ⁺ -InGaP to replace the heterostructure n ⁺ -GaAs/p ⁺ -GaAs. The main reason is that the conduction band of the InGaP/GaAs heterojunction is discontinuous Δ E _C , which can increase the gate barrier height and effectively confine the electrons in the channel. The discontinuous value Δ E _{V of the} valence band can increase the barrier effect on the hole. Therefore, the n ⁺ -GaAs/p ⁺ -InGaP/n-GaAs camel-type heterostructure field effect transistor can obtain a high breakdown voltage, high linearity conversion characteristics, and a drain output current.

On the basis of the foregoing, if aluminium is appropriately added to the InGaP of the aforementioned heterostructure to replace the gallium therein, not only the lattice constant thereof but also the energy gap can be raised to 2.3 eV (In _0.5 Al _0.5 P). ), and the indium aluminum gallium phosphide has a chemical formula of In _0.5 (Al _X Ga _1-X ) _0.5 P, where x represents the proportion of aluminum substituted gallium, and as the aluminum content increases, the energy gap increases, and InAlGaP The Δ E _C value of /GaAs is also larger than the Δ E _C of InGaP/GaAs.

Since the InAlGaP/GaAs heterojunction has the aforementioned advantages, it can be used to improve the existing hump-type heterostructure field effect transistor to enhance its characteristics.

Therefore, the main object of the present invention is to provide an indium phosphide gallium hump-type gate field effect transistor, which mainly replaces the heterostructure in a hump-type gate field effect transistor with a heterostructure n ⁺ -GaAs/p ⁺ -InAlGaP. ⁺ -GaAs/p ⁺ -InGaP for greater output current, breakdown voltage and output power.

One of the main technical means for achieving the above purpose is to form an undoped gallium arsenide buffer layer and a gallium arsenide spatial layer on the half of the insulating gallium arsenide substrate. a high concentration doped layer and a channel layer; and further forming a barrier gate and a gate metal and a source metal forming an ohmic contact; wherein:

The high concentration doped layer is formed on the gallium arsenide space layer by Delta doping;

The potential barrier gate is composed of a heterojunction structure of n-type gallium arsenide/p-type indium phosphide/n-type gallium arsenide n ⁺ -GaAs/p ⁺ InAlGaP/n-GaAs;

The channel layer is composed of indium gallium arsenide (InGaAs);

In the field effect transistor gate design, due to the heterostructure h ⁺ -GaAs / p ⁺ -InAlGaP substituted n ⁺ -GaAs / p ⁺ -InGaP, compared to InGaP having a larger energy gap and potential energy barrier, Since the Δ E _{C of the} heterostructure InAlGaP/GaAs is larger than InGaP/GaAs, the electron injection channel layer can be effectively suppressed; the other energy barrier is made of n-type gallium arsenide, p-type indium aluminum gallium arsenide, n GaAs is formed by using InAlGaP/GaAs heterojunction with large Δ E _c value and Delta doping technology, so that larger output current, breakdown voltage and output power can be obtained, and the hump-type gate is greatly improved. The characteristics of field effect transistors.

Another object of the present invention is to provide an indium phosphide gallium hump-type gate field effect transistor in which the gate metal, the source metal and the drain metal are on the same plane.

Regarding the first preferred embodiment of the present invention, please refer to the first figure, including:

Half insulated gallium arsenide substrate (10) (S.I. GaAs Substrate);

a gallium arsenide buffer layer (11) is formed on the foregoing gallium arsenide substrate (10), the gallium arsenide buffer layer (11) having a thickness of between 0.5 and 1.5 μm;

A high concentration doped layer (12) is formed on the foregoing gallium arsenide buffer layer (11) by a delta doping method, and the doping concentration δ(n ⁺ ) is between 2×10 ¹² and 3×10 ¹² cm ⁻² . ;

a gallium arsenide space layer (13) is formed on the foregoing gallium arsenide buffer layer (11), and has a thickness of between 25 and 55 angstroms;

A channel layer (14) is formed on the gallium arsenide space layer (13) by an undoped indium gallium arsenide (In _X Ga _1-X As, 0.1) having a thickness of 90 Å. x 0.25);

A barrier gate (15) is located on the channel layer (14). The potential barrier (15) is sequentially an n-type gallium arsenide layer (n ⁺ -GaAs, doped) from top to bottom. a concentration between 2.5x10 ¹⁸ and 3.5x10 ¹⁸ cm ^-3 ), a thickness between 150 and 250 angstroms, a p-type indium phosphide layer (p ⁺ -InAlGaP, doping concentration between 2x10 ¹⁸ between ^-3 and 3x10 ¹⁸ cm ^-3 cm), a thickness of between 90 to 100 angstroms, a layer of n-type gallium arsenide (n-GaAs, doping concentration from about 1.5x10 ¹⁷ to 2.5x10 ¹⁷ cm ^-3 Between 1800 and 2200 angstroms; thereby, the potential barrier gate (15) constitutes a heterojunction structure of n ⁺ -GaAs/p ⁺ -InAlGaP/n-GaAs;

a source metal (17), a drain metal (18) and a gate metal (16), mainly plating the source metal (17) and the drain metal (18) on the potential barrier (15) The lowermost layer of GaAs (n-GaAs) (thickness between 1800 and 2200) Between, then annealing, to form the source and the drain; then plating the gate metal on the uppermost GaAs layer (n ⁺ -GaAs) of the barrier (15) (18) And using the source metal (17), the drain metal (18) and the gate metal (16) as a mask, and then removing the n ⁺ -GaAs with a GaAs etching solution, and then using the InAlGaP etching solution to n ⁺ -GaAs The lower layer of InAlGaP is removed to form a gate; the source metal (17) and the drain metal (18) are made of AuGeNi/Au, and the gate metal (16) is made of gold (Au).

A hump-type gate field effect transistor can be constructed by using the foregoing structure, since the potential barrier gate (15) is composed of an n ⁺ -GaAs/p ⁺ -InAlGaP/n-GaAs heterojunction structure, wherein InAlGaP has Larger energy gap and potential energy barrier, and InAlGaP/GaAs heterostructure has a larger Δ E _C value, so in addition to effectively suppressing the electron injection channel layer (14), a larger output current and breakdown voltage can be obtained. And output power.

Further, as shown in the second figure, a second preferred embodiment of the present invention is mainly an inverse delta-doped n ⁺ -GaAs/p ⁺ -InAlGaP/n-InAlGaP hetero-connected effect transistor, and these are The field effect electro-crystal system includes:

Half insulated GaAs substrate (20);

a gallium arsenide buffer layer (21) is formed on the foregoing gallium arsenide substrate (20), the gallium arsenide buffer layer (21) having a thickness of between 0.5 and 1 μm;

An undoped first indium aluminum gallium phosphide layer (22) is formed on the foregoing gallium arsenide buffer layer (21), and the first indium phosphide layer (22) has a thickness of 200 to 900 angstroms;

A high concentration doped layer (23A) is doped on the first indium phosphide layer (22) by a delta doping method, and the doping concentration δ(n ⁺ ) is between 2×10 ¹² and 3.5. ×10 ¹² cm ^-2 ;

a space layer (23) of undoped indium aluminum gallium is formed on the aforementioned high concentration doped layer (23A) and has a thickness of 25 to 50 angstroms;

a channel layer (24) formed on the space layer (23) is an undoped indium gallium arsenide (In _X Ga _1-X As) having a thickness of 60 to 100 angstroms. Constitute

A barrier gate (25) is located on the channel layer (24). The potential barrier (25) is sequentially an n-type gallium arsenide layer (n ⁺ -GaAs doping concentration) from top to bottom. Between 3x10 ¹⁸ and 4x10 ¹⁸ cm ^-3 ), with a thickness between 150 and 250 angstroms, a p-type indium phosphide layer (p ⁺ -InAlGaP, doping concentration between 2×10 ¹⁸ cm ^{-3 )} Between 3x10 ¹⁸ cm ^-3 ), between 90 and 110 angstroms thick, an n-type indium phosphide layer (n-InAlGaP, doping concentration between 1x10 ¹⁷ and 1.5x10 ¹⁷ cm ^-3 ) ), the thickness is between 500 and 650 angstroms;

a gate metal (26) is formed on the cap layer (251) of the barrier (25), and the gate metal (26) is formed by evaporation of gold (Au);

a source metal (27), a drain metal (28) and a gate metal (26), mainly for plating the source metal (27) and the drain metal (28) on the potential barrier (25) The uppermost layer of gallium arsenide (n ⁺ -GaAs) is then annealed to form a source and a drain; then a Mesa process is performed, and then the gate is still plated on the n ⁺ -GaAs layer. a polar metal (28), and a source metal (27), a drain metal (28) and a gate metal (26) as a mask, and then removing the n ⁺ -GaAs with a GaAs etching solution to form a gate; This allows the source, drain and gate to be on the same plane. The source metal (27) and the drain metal (28) are made of AuGeNi/Au, and the gate metal (26) is made of gold (Au).

Furthermore, as shown in the third figure, a third preferred embodiment of the present invention is mainly a double delta doped n ⁺ -GaAs/p ⁺ -InAlGaP/n-InAlGaP heterojunction field effect transistor, and The equivalent field effect crystal system includes:

Half insulated GaAs substrate (30);

a gallium arsenide buffer layer (31) is formed on the foregoing gallium arsenide substrate (30), the gallium arsenide buffer layer (31) having a thickness of between 0.5 and 1 μm;

An undoped first indium aluminum gallium phosphide layer (32) is formed on the foregoing gallium arsenide buffer layer (31), and the first indium phosphide layer (32) has a thickness of 100 to 300 Between

A first high concentration doped layer (33A) is formed on the first indium phosphide layer (32) by a delta doping method, and the doping concentration δ(n ⁺ ) is between 2×10 ¹² and 3.5×10 Between ¹² cm ^-2 ;

An undoped first space layer (33) is composed of indium aluminum gallium phosphide having a thickness of between 25 and 50 angstroms, which is formed on the first high concentration doped layer (33A);

a channel layer (34) formed on the first space layer (33) is an undoped indium gallium arsenide (In _X Ga _1-X As) having a thickness of between 60 and 100 angstroms. Constitute

An undoped second space layer (35) is composed of indium aluminum gallium phosphide having a thickness of between 25 and 55 angstroms, which is formed on the channel layer (34);

a second high concentration doped layer (33B) is doped on the second space layer (35) by a delta doping method, and the doping concentration δ(n ⁺ ) is between 2×10 ¹² and 3.5× ^{10 12} cm ⁻ Between ² ;

An undoped second indium aluminum gallium phosphide layer (36) is formed on the second high concentration doped layer (33B);

The two-position barrier gate (37) is located on the second indium aluminum gallium phosphide layer (36), and the potential barrier gate (37) is sequentially an n-type gallium arsenide layer from top to bottom ( n ⁺ -GaAs, doping concentration between 3x10 ¹⁸ and 4x10 ¹⁸ cm ^-3 ), thickness between 150 and 250 angstroms, a p-type indium phosphide layer (p ⁺ -InAlGaP, doped a concentration of between 1x10 ¹⁸ cm ^-3 and 3x10 ¹⁸ cm ^-3 ), between 90 and 110 angstroms thick, an n-type indium phosphide layer (n-InAlGaP, doping concentration between 1x10 ¹⁷ and 1.5x10 ¹⁷ cm ^-3 ), thickness between 500 and 650 angstroms;

a gate metal (381) is formed on the cap layer of the barrier (37), and the gate metal (381) is formed by evaporation of gold (Au);

a source metal (382), a drain metal (383) and a gate metal (381) mainly plate the source metal (382) and the drain metal (383) on the potential barrier (37) The uppermost layer of gallium arsenide (n ⁺ -GaAs) is then annealed to form the source and drain; followed by a Mesa process followed by plating on the n ⁺ -GaAs layer a gate metal (381) with a source metal (382), a gate metal (383), and a gate metal (381) as a mask, and a GaAs etchant to remove n ⁺ -GaAs to form a gate So that the source bungee and the gate are on the same plane. As in the previous embodiment, the source metal (382) and the drain metal (383) are made of AuGeNi/Au, and the gate metal (381) is made of gold (Au).

(10). . . Gallium arsenide substrate

(11). . . Gallium arsenide buffer layer

(12). . . Delta doped layer

(13). . . Gallium arsenide space layer

(14). . . Channel layer

(15). . . Potential barrier

(16). . . Gate metal

(17). . . Source metal

(18). . . Bungee metal

(20) (30). . . Gallium arsenide substrate

(twenty one). . . Gallium arsenide buffer layer

(twenty two). . . First indium aluminum gallium phosphide layer

(twenty three). . . Second indium aluminum gallium phosphide layer

(23A). . . Delta doped layer

(twenty four). . . Channel layer

(25). . . Potential barrier

(26). . . Gate metal

(27). . . Source metal

(28). . . Bungee metal

(31). . . Gallium arsenide buffer layer

(32). . . First indium aluminum gallium phosphide layer

(33). . . First space layer

(33A). . . First delta doped layer

(33B). . . Second delta doped layer

(34). . . Channel layer

(35). . . Second space layer

(36). . . Second indium aluminum gallium phosphide layer

(37). . . Potential barrier

(381). . . Gate metal

(382). . . Source metal

(383). . . Bungee metal

First Figure: A schematic view of the structure of a first preferred embodiment of the present invention.

Figure 2 is a schematic view showing the structure of a second preferred embodiment of the present invention.

Figure 3 is a schematic view showing the structure of a third preferred embodiment of the present invention.

(10). . . Gallium arsenide substrate

(11). . . Gallium arsenide buffer layer

(12). . . Delta doped layer

(13). . . Gallium arsenide space layer

(14). . . Channel layer

(15). . . Potential barrier

(16). . . Gate metal

(17). . . Source metal

(18). . . Bungee metal

Claims (21)

A field effect transistor having an indium aluminum gallium phosphide/gallium arsenide gate comprising: a semi-insulating gallium arsenide substrate; a gallium arsenide buffer layer formed on the gallium arsenide substrate; an arsenic a gallium space layer is formed on the foregoing gallium arsenide buffer layer; a high concentration doped layer is doped in the delta doping manner between the gallium arsenide buffer layer and the gallium arsenide space layer; An undoped indium gallium arsenide is formed on the aforementioned gallium arsenide space layer; a single barrier gate is located on the channel layer, and the potential barrier is made of n ⁺ -GaAs/p ⁺ -InAlGaP/n a heterojunction structure of GaAs; a source metal, a drain metal, and a gate metal, the source metal and the gate metal being on the n-GaAs layer of the lowermost layer of the potential barrier gate, The gate is on the n ⁺ -GaAs layer at the top of the potential barrier. For example, in the field effect transistor of the indium phosphide-gallium gallium arsenide/gallium arsenide gate type described in claim 1, the potential barrier gate is sequentially from top to bottom: an n-type gallium arsenide doped a hetero-layer having a concentration between 2.5 x 10 ¹⁸ and 3.5 x 10 ¹⁸ cm ^-3 and a thickness between 150 and 250 angstroms; a p-type indium phosphide layer with a doping concentration of 2 x 10 ¹⁸ Between ^-3 to 3x 10 ¹⁸ cm ^-3 and between 90 and 110 angstroms thick; an n-type gallium arsenide layer having a doping concentration between 1.5 x ^{10 17} and 2.5 x ^{10 17} cm ^-3 , The thickness is between 1800 and 2200 angstroms. The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate electrode as described in claim 2, the gallium arsenide buffer layer having a thickness of between 0.5 and 1.5 μm . The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate type as described in claim 3, wherein the gallium arsenide space layer has a thickness of between 25 and 50 angstroms. The field effect transistor having an indium phosphide/gallium arsenide gate electrode as described in claim 2, the doping concentration δ (n ⁺ ) of the high concentration doping layer is between 2×10 ¹² and 3×10 Between ¹² cm ^-2 . The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate electrode as described in claim 5, the indium gallium arsenide chemical formula of the channel layer is In _X Ga _1-X As, 0.1 x 0.25, its thickness is between 60 and 100 angstroms. The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate electrode as described in claim 6 of the patent application scope, wherein the gate metal is formed by evaporation of gold (Au), the source metal and the drain electrode The metal is composed of AuGeNi/Au. A field effect transistor having an indium gallium phosphide/gallium arsenide gate comprising: a semi-insulating gallium arsenide substrate; a gallium arsenide buffer layer formed on the gallium arsenide substrate; The doped first indium aluminum gallium phosphide layer is formed on the foregoing gallium arsenide buffer layer; a high concentration doped layer is doped on the first indium phosphide layer by a delta doping method; An undoped indium aluminum gallium arsenide spatial layer is formed on the high concentration doped layer; a channel layer is formed on the first indium phosphide layer by undoped indium gallium arsenide; A barrier gate is located on the channel layer, and the barrier is composed of a heterojunction structure of n ⁺ -GaAs/p ⁺ -InAlGaP/n-InAlGaP; a source metal and a drain a metal and a gate metal, the source metal and the gate metal are plated on the n ⁺ -GaAs layer of the uppermost layer of the barrier layer; the gate metal is also on the n ⁺ -GaAs layer. For example, in the field effect transistor of the indium phosphide-gallium gallium arsenide/gallium arsenide gate type described in claim 8 of the patent application, the potential barrier gate is sequentially from top to bottom: an n-type gallium arsenide doped heteroaryl layer, a concentration of between 3x10 ¹⁸ to 4x10 ¹⁸ cm ^-3, thickness is between 150 to 250 angstroms; a p-type aluminum gallium indium phosphide layer having a doping concentration of between 2x10 ¹⁸ cm ^-3 to Between 3x10 ¹⁸ cm ^-2 and a thickness between 90 and 110 angstroms; an n-type GaAs layer with a doping concentration between 1x10 ¹⁷ and 1.5x10 ¹⁷ cm ^-3 and a thickness between 500 and 650 Between the ang. The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide hump type gate according to claim 9 of the patent application scope, wherein the thickness of the gallium arsenide buffer layer is between 0.5 and 1 μm , the first The thickness of the indium phosphide layer is between 200 and 900 angstroms, and the thickness of the indium phosphide layer is between 25 and 50 angstroms. The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate electrode as described in claim 10, the doping concentration δ (n ⁺ ) of the high concentration doping layer is between 2×10 ¹² and 3.5 Between x10 ¹² cm ^-2 . The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate electrode as described in claim 11 of the patent application, the indium gallium arsenide chemical formula of the channel layer is In _X Ga _1-X As, 0.1 x 0.25, its thickness is between 60 and 100 angstroms. The field effect transistor having an indium aluminum gallium phosphide/gallium arsenide gate type as described in claim 12, wherein the gate metal is formed by evaporation of gold (Au), the source metal and the drain electrode The metal is composed of AuGeNi/Au. The field effect transistor having an indium gallium phosphide/gallium arsenide-type gate electrode according to any one of claims 8 to 13, wherein the gate metal is in the same plane as the source metal and the drain metal. on. A field effect transistor having an indium gallium phosphide/gallium arsenide gate comprising: a semi-insulating gallium arsenide substrate; a gallium arsenide buffer layer formed on the gallium arsenide substrate; The doped first indium aluminum gallium phosphide layer (having a thickness between 100 and 300 angstroms) is formed on the foregoing gallium arsenide buffer layer; a first high concentration doped layer is doped by a delta doping method Mixed with the first indium aluminum phosphide layer; a first space layer (having a thickness between 25 and 50 angstroms) formed by the undoped indium phosphide in the first high concentration doping a channel layer formed of undoped indium gallium arsenide on the first space layer; a second space layer (having a thickness between 25 and 50 angstroms) with undoped phosphating Indium aluminum gallium is formed on the channel layer; a second high concentration doped layer is formed on the second space layer by Delta doping; and an undoped second indium aluminum gallium nitride layer (thickness Between 100 and 300 angstroms, formed on the second high-concentration doped layer; a single-barrier gate is located on the channel layer, mainly by n ⁺ -GaAs/p ⁺ -InA lGaP/n-InAlGaP heterojunction structure; a source metal, a drain metal and a gate metal, the source metal and the drain metal are plated on the uppermost layer of n ⁺ -GaAs On the layer; the gate metal is also on the n ⁺ -GaAs layer. For example, in the field effect transistor of the indium phosphide-gallium gallium arsenide/gallium arsenide-type gate as described in claim 15 of the patent application, the potential barrier gate is sequentially from top to bottom: an n-type gallium arsenide doped heteroaryl layer, a concentration of between 3x10 ¹⁸ to 4x10 ¹⁸ cm ^-3, thickness is between 150 to 250 angstroms; a p-type aluminum gallium indium phosphide layer having a doping concentration of between 1x10 ¹⁸ cm ^-3 to Between 3x 10 ¹⁸ cm ^-3 and a thickness between 90 and 110 angstroms; an n-type GaAs layer with a doping concentration between 1 x 10 ¹⁷ and 1.5 x 10 ¹⁷ cm ^-3 and a thickness between 500 and Between 650 angstroms. The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide hump type gate according to claim 16 of the patent application scope, wherein the thickness of the gallium arsenide buffer layer is between 0.5 and 1 μm , The second space layer has a thickness of between 25 and 50 angstroms and the second indium phosphide layer has a thickness of between 100 and 300 angstroms. The doping concentration δ (n ⁺ ) of the first and second high-concentration doped layers is the field effect transistor having the indium aluminum gallium phosphide/gallium arsenide-type gate as described in claim 17 Between 2x10 ¹² and 3.5x10 ¹² cm ^-2 . The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate type as described in claim 18, the indium gallium arsenide chemical formula of the channel layer is In _X Ga _1-X As, 0.1 x 0.25, its thickness is between 60 and 100 angstroms. The field effect transistor having an indium phosphide gallium arsenide/gallium arsenide gate type as described in claim 15 of the patent application, wherein the gate metal is formed by evaporation of gold (Au), the source metal and the drain electrode The metal is composed of AuGeNi/Au. The field effect transistor having an indium aluminum gallium phosphide/gallium arsenide gate electrode according to any one of claims 15 to 20, wherein the gate metal is in the same plane as the source metal and the drain metal. on.