TWI388015B - 薄膜電晶體及其製造方法 - Google Patents

薄膜電晶體及其製造方法 Download PDF

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TWI388015B
TWI388015B TW098134191A TW98134191A TWI388015B TW I388015 B TWI388015 B TW I388015B TW 098134191 A TW098134191 A TW 098134191A TW 98134191 A TW98134191 A TW 98134191A TW I388015 B TWI388015 B TW I388015B
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thin film
film transistor
layer
beam structure
carrier
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TW201113953A (en
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Huang Chung Cheng
Ta Chuan Liao
sheng kai Chen
ying hui Chen
Chi Neng Mo
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Chunghwa Picture Tubes Ltd
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Description

薄膜電晶體及其製造方法
本發明是有關於一種半導體元件，且特別是有關於一種薄膜電晶體。
圖1繪示傳統一種薄膜電晶體的剖面示意圖。請參照圖1，薄膜電晶體100包括一基板110、一絕緣層120、一島狀多晶矽140、一載子穿隧層152、一載子捕捉層154、一載子阻檔層156以及一閘極160，其中絕緣層120、島狀多晶矽140、載子穿隧層152、載子捕捉層154、載子阻檔層156以及閘極160依序配置於基板110上。
在島狀多晶矽140中，兩個N型摻雜區分別作為源極140a以及汲極140b，而源極140a以及汲極140b之間的區域作為通道140c。此外，源極140a、汲極140b以及通道140c分別具有一尖端結構P，其中這些尖端結構P是透過製程繁複的順序橫向固化(Sequential Lateral Solidification,SLS)雷射結晶方法所形成。
就薄膜電晶體100所構成的非揮發性記憶體而言，這些尖端結構P可用來增加電場強度，進而提高寫入(program)以及抹除(erase)的效率。然而，透過順序橫向固化雷射結晶方法，不僅容易發生尖端結構P的高度不易控制的現象，且尖端結構P的位置與其他膜層之間也衍生對位不精確的問題。如此一來，薄膜電晶體100的電性特性便發生均勻性不佳的情形，而非揮發性記憶體的寫入以及抹除的效率也隨之降低，進而使薄膜電晶體100的整體良率下降。
本發明提供一種薄膜電晶體的製造方法，其可簡化製程、提高良率和降低成本。
本發明提供一種薄膜電晶體，其具有均勻性佳的電性特性。
本發明提出一種薄膜電晶體的製造方法，其包括下列步驟。首先，在一基板上形成一絕緣圖案層，其中絕緣圖案層具有至少一突起部。再者，在絕緣圖案層上形成至少一間隙壁以及多個彼此分離的非晶半導體圖案，其中間隙壁形成在突起部的一側邊，且間隙壁連接於非晶半導體圖案之間。之後，結晶化間隙壁以及非晶半導體圖案。而後，移除突起部以及間隙壁下方的絕緣圖案層，如此間隙壁懸空於基板上而成為具有多個轉角部的一橫樑結構。然後，在基板上依序形成一載子穿隧層、一載子捕捉層以及一載子阻檔層，其中載子穿隧層、載子捕捉層以及載子阻檔層依序順應性地包覆橫樑結構的轉角部。隨後，在基板上形成一閘極，其中閘極覆蓋橫樑結構，並包覆載子阻檔層。
在本發明之一實施例中，突起部的形狀為一長方體，且突起部的側邊為長方體的其中一長邊。在一實施例中，非晶半導體圖案分別覆蓋長方體的兩相對短邊。
在本發明之一實施例中，薄膜電晶體的製造方法更包括下列步驟。首先，將非晶半導體圖案於結晶化之後轉換為多個多晶半導體圖案。然後，對與橫樑結構的兩端相連接的多晶半導體圖案進行離子摻雜，以分別形成一源極以及一汲極，其中橫樑結構連接於源極以及汲極之間。
在本發明之一實施例中，非晶半導體圖案的材料包括非晶矽、非晶鍺或非晶矽鍺。
在本發明之一實施例中，間隙壁在結晶化之前的材料包括非晶矽、非晶鍺或非晶矽鍺。
本發明提出一種薄膜電晶體，其包括一基板、一絕緣圖案層、多個多晶半導體圖案、至少一橫樑結構、一載子穿隧層、一載子捕捉層、一載子阻檔層以及一閘極。絕緣圖案層配置於基板上，而多晶半導體圖案彼此分離地配置於絕緣圖案層上。橫樑結構位於基板上方但不與基板直接連接，並連接於多晶半導體圖案之間，且具有多個轉角部。載子穿隧層順應性地包覆橫樑結構的轉角部，而載子捕捉層順應性地包覆載子穿隧層，且載子阻檔層順應性地包覆載子捕捉層。閘極配置於基板上，並覆蓋橫樑結構，且包覆載子阻檔層。
在本發明之一實施例中，薄膜電晶體更包括一源極以及一汲極。源極以及汲極分別形成於與橫樑結構的兩端相連接的多晶半導體圖案中，其中橫樑結構連接於源極以及汲極之間。
在本發明之一實施例中，多晶半導體圖案的材料包括多晶矽、多晶鍺或多晶矽鍺。
在本發明之一實施例中，橫樑結構的材料包括多晶矽、多晶鍺或多晶矽鍺。
在本發明之一實施例中，橫樑結構具有三個轉角部。
在本發明之一實施例中，絕緣圖案層的材料包括半導體氧化物或半導體氮化物。
在本發明之一實施例中，閘極的材料包括金屬或半導體。
基於上述，本發明的薄膜電晶體具有均勻的電性特性，而本發明之薄膜電晶體的製造方法具有簡化製程、提高良率、降低成本等優勢。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖2A～圖6A繪示本發明之一實施例之薄膜電晶體的製造流程局部上視示意圖，而圖2B～圖6B分別為根據圖2A～圖6A中剖面線L-L所繪示的剖面示意圖。
首先，請參照圖2A以及圖2B，在一基板210上形成一絕緣圖案層220，且絕緣圖案層220具有至少一突起部220a，其中本實施例是以具有兩個突起部220a的絕緣圖案層220為例，但本發明不以此為限。在本實施例中，突起部220a的形狀例如是一長方體，其中圖2A可窺知突起部220a的上視輪廓(即長方體的頂面)大致呈矩形，而圖2B可窺知突起部220a的剖面觀。簡言之，本實施例之突起部220a的外觀猶如一步階形狀(Step Profile)。
在本實施例中，基板210的材質例如是玻璃，而基板210以及絕緣圖案層220之間例如設置一氮化層214。此外，本實施例之具有突起部220a的絕緣圖案層220是透過微影蝕刻製程(Photolithography and Etching Process,PEP)來達成，其中蝕刻的步驟例如利用乾式蝕刻製程，而絕緣圖案層220的材料包括半導體氧化物(例如二氧化矽)、半導體氮化物或其他合適的絕緣材料。實務上，在基板210上形成絕緣圖案層220之前，可先在基板210上形成一層氧化材質作為緩衝層212，即在基板210以及絕緣圖案層220之間形成緩衝層212。
再者，請參照圖3A以及圖3B，在絕緣圖案層220上形成至少一間隙壁230以及多個彼此分離的非晶半導體圖案240，其中間隙壁230連接於非晶半導體圖案240之間。在本實施例中，間隙壁230以及非晶半導體圖案240的形成例如是先在絕緣圖案層220上全面性地沈積一層由非晶矽、非晶鍺、非晶矽鍺或其他合適的非晶半導體材料所構成的薄膜，再利用微影蝕刻製程來形成間隙壁230以及非晶半導體圖案240兩者的圖案，其中間隙壁230的形成可透過非等向性的蝕刻製程來達成。
在本實施例中，例如形成四個間隙壁230以及兩個非晶半導體圖案240。更詳細地說，就形狀為長方體的突起部220a而言，這些彼此分離的非晶半導體圖案240分別覆蓋突起部220a的兩相對側邊，例如覆蓋突起部220a的兩相對短邊S1；另一方面，間隙壁230形成在突起部220a的另兩相對側邊，例如形成在突起部220a的兩相對長邊S2。
在此需要說明的是，本實施例主要是以具有兩個突起部220a的絕緣圖案層220進行說明，並假設每個突起部220a的兩相對長邊S2都形成間隙壁230，因而繪示於圖3A以及圖3B兩者中之間隙壁230的數量為四個。然而，本發明並無限制突起部的兩相對側邊皆必需形成間隙壁，意即間隙壁230也可僅形成於突起部220a的一側邊。
之後，結晶化間隙壁230以及非晶半導體圖案240，以進一步將間隙壁230以及非晶半導體圖案240轉換為由多晶矽、多晶鍺、多晶矽鍺或其他多晶半導體材質所組成的間隙壁230a以及多晶半導體圖案240a，如圖3A以及圖3B所示。由於本實施例在進行結晶化製程之後的圖案與結晶化製程之前的圖案大致相同，在此為了簡化說明，因而將間隙壁230、230a、非晶半導體圖案240以及多晶半導體圖案240a一併繪製於圖3A以及圖3B中。
而後，移除突起部220a以及間隙壁230a下方的絕緣圖案層220，其中移除的動作可透過濕式蝕刻製程來達成。如此一來，與間隙壁230a接觸的突起部220a以及部分絕緣圖案層220便可被移除，而形成懸空於基板210上之具有多個轉角部A的一橫樑結構230b，如圖4A以及圖4B所示。在本實施例中，橫樑結構230b具有三個轉角部A。
值得一提的是，並請參照圖4A，在前述移除突起部220a的步驟中，由於本實施例之部分突起部220a會被多晶半導體圖案240a所覆蓋，因而實際上被移除的部分為未被多晶半導體圖案240a所覆蓋的突起部220a。相反地，被多晶半導體圖案240a所覆蓋的突起部220a會遺留下來。
然後，請參照圖5A以及圖5B，在基板210上依序形成一載子穿隧層252、一載子捕捉層254以及一載子阻擋層256。詳細而言，本實施例透過連續地等向性沉積二氧化矽、氮化矽以及二氧化矽來依序形成載子穿隧層252、載子捕捉層254以及載子阻檔層256，使得載子穿隧層252、載子捕捉層254以及載子阻檔層256依序包覆橫樑結構230b的轉角部A，並進一步包覆整個橫樑結構230b。
特別一提的是，透過本實施例之橫樑結構230b的轉角部A，載子穿隧層252、載子捕捉層254以及載子阻檔層256三層可順應性地包覆橫樑結構230b，而非平坦地形成於基板210上。相較於傳統薄膜電晶體的載子穿隧層、載子捕捉層以及載子阻檔層三層僅為平坦的薄膜，本實施例不僅改善了傳統薄膜電晶體既有的電性問題，還進一步提升傳統薄膜電晶體的電性特性。
除此之外，本實施例利用微影蝕刻製程便能形成具有轉角部A的橫樑結構230b，進而形成載子穿隧層252、載子捕捉層254以及載子阻檔層256三層順應性地包覆橫樑結構230b的結構。相較於傳統技術利用製程繁複的順序橫向固化雷射結晶方法來製作先前技術所揭露的薄膜電晶體100中的尖端結構P，本實施例不僅簡化製程、降低成本，還可避免順序橫向固化雷射結晶方法導致尖端結構P的高度不易控制、位置偏移等無法預期的問題。
隨後，請參照圖6A以及圖6B，在基板210上形成一閘極260。在本實施例中，形成閘極260的方法例如是先在基板210形成一金屬層(未繪示)或一半導體層(未繪示)並覆蓋橫樑結構230b，然後再利用微影製程以及乾式蝕刻製程來圖案化此金屬層或此半導體層，以形成覆蓋橫樑結構230b並包覆載子阻檔層256的閘極260。上述至此，本實施例之薄膜電晶體200已大致製作完成。
然而，本實施例在形成閘極260之前，可先對與橫樑結構230b(繪示於圖4A)的兩端相連接的多晶半導體圖案240a進行離子摻雜，以分別形成一源極以及一汲極，使得橫樑結構230b連接於源極以及汲極之間。
由圖6A以及圖6B可知，本實施例之薄膜電晶體200包括一基板210、一絕緣圖案層220、多個多晶半導體圖案240a、至少一橫樑結構230b、一載子穿隧層252、一載子捕捉層254、一載子阻檔層256以及一閘極260。絕緣圖案層220配置於基板210上，而多晶半導體圖案240a彼此分離地配置於絕緣圖案層220上。橫樑結構230b位於基板210上方但不與基板210直接連接，並連接於多晶半導體圖案240a之間，且具有多個轉角部A。載子穿隧層252包覆橫樑結構230b的轉角部A，而載子捕捉層254包覆載子穿隧層252，且載子阻檔層256包覆載子捕捉層254。閘極260配置於基板210上，並覆蓋橫樑結構230b，且包覆載子阻檔層256。
就應用層面而言，薄膜電晶體200可作為非揮發性記憶體。在載子穿隧層252、載子捕捉層254以及載子阻檔層256三層順應性地包覆多個轉角部A的架構下，薄膜電晶體200在每個轉角部A附近皆可具有較大的電場強度，如此其進行寫入以及抹除等動作時的效率可大幅提高。此外，本實施例利用微影製程可精準地控制橫樑結構230b的形狀，因而包覆橫樑結構230b的各個膜層也能均勻地順應成形，進而使每個薄膜電晶體200的電性特性具有相當程度的一致性，其有別於先前技術所揭露的傳統薄膜電晶體100的電性特性發生均勻性不佳的情形。
由上述可知，本實施例之薄膜電晶體200可作為電場增強式薄膜電晶體非揮發性記憶體，就顯示技術而言，其還可應用於系統面板(System on Panel)中。由於透過微影製程便可形成本實施例之薄膜電晶體200，於是，整合至系統面板上的薄膜電晶體200以及系統面板上既有的薄膜可一併製作，因而無製程整合不易、製作繁複或甚至良率難以控制等技術上的問題。
綜上所述，本發明之薄膜電晶體透過特殊的結構設計，其電性特性可大幅度地提升。除此之外，本發明之薄膜電晶體的製造方法不僅可簡化傳統技術的繁複製程，且在製作的執行面上，還能大量製作出高良率以及品質一致的薄膜電晶體，進而降低製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、200．．．薄膜電晶體
110、210．．．基板
120．．．絕緣層
140．．．島狀多晶矽
140a．．．源極
140b．．．汲極
140c．．．通道
152、252．．．載子穿隧層
154、254．．．載子捕捉層
156、256．．．載子阻檔層
160、260．．．閘極
212．．．緩衝層
214．．．氮化層
220．．．絕緣圖案層
220a．．．突起部
230、230a．．．間隙壁
230b．．．橫樑結構
240．．．非晶半導體圖案
240a．．．多晶半導體圖案
A．．．轉角部
L-L．．．剖面線
P．．．尖端結構
S1．．．短邊
S2．．．長邊
圖1繪示傳統一種薄膜電晶體的剖面示意圖。
圖2A～圖6A繪示本發明之一實施例之薄膜電晶體的製造流程局部上視示意圖。
圖2B～圖6B分別為根據圖2A～圖6A中剖面線L-L所繪示的剖面示意圖。
210．．．基板
212．．．緩衝層
214．．．氮化層
230b．．．橫樑結構
252．．．載子穿隧層
254．．．載子捕捉層
256．．．載子阻檔層
260．．．閘極
A．．．轉角部

Claims (16)

  1. 一種薄膜電晶體的製造方法，包括：在一基板上形成一絕緣圖案層，其中該絕緣圖案層具有至少一突起部；在該絕緣圖案層上形成至少一間隙壁以及多個彼此分離的非晶半導體圖案，其中該間隙壁形成在該突起部的一側邊，且該間隙壁連接於該些非晶半導體圖案之間；結晶化該間隙壁以及該些非晶半導體圖案；移除該突起部以及該間隙壁下方的該絕緣圖案層，如此該間隙壁懸空於該基板上而成為具有多個轉角部的一橫樑結構；在該基板上依序形成一載子穿隧層、一載子捕捉層以及一載子阻檔層，其中該載子穿隧層、該載子捕捉層以及該載子阻檔層依序順應性地包覆該橫樑結構的該些轉角部；以及在該基板上形成一閘極，其中該閘極覆蓋該橫樑結構，並包覆該載子阻檔層。
  2. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，其中該突起部的形狀為一長方體，且該突起部的該側邊為該長方體的其中一長邊。
  3. 如申請專利範圍第2項所述之薄膜電晶體的製造方法，其中該些非晶半導體圖案分別覆蓋該長方體的兩相對短邊。
  4. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，其中該橫樑結構具有三個轉角部。
  5. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，更包括：將該些非晶半導體圖案於結晶化之後轉換為多個多晶半導體圖案；以及對與該橫樑結構的兩端相連接的該些多晶半導體圖案進行離子摻雜，以分別形成一源極以及一汲極，其中該橫樑結構連接於該源極以及該汲極之間。
  6. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，其中該絕緣圖案層的材料包括半導體氧化物或半導體氮化物。
  7. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，其中該些非晶半導體圖案的材料包括非晶矽、非晶鍺或非晶矽鍺。
  8. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，其中該間隙壁在結晶化之前的材料包括非晶矽、非晶鍺或非晶矽鍺。
  9. 如申請專利範圍第1項所述之薄膜電晶體的製造方法，其中該閘極的材料包括金屬或半導體。
  10. 一種薄膜電晶體，包括：一基板；一絕緣圖案層，配置於該基板上；多個多晶半導體圖案，彼此分離地配置於該絕緣圖案層上；至少一橫樑結構，位於該基板上方但不與該基板直接連接，並連接於該些多晶半導體圖案之間，且具有多個轉角部；一載子穿隧層，順應性地包覆該橫樑結構的該些轉角部；一載子捕捉層，順應性地包覆該載子穿隧層；一載子阻檔層，順應性地包覆該載子捕捉層；以及一閘極，配置於該基板上，並覆蓋該橫樑結構，且包覆該載子阻檔層。
  11. 如申請專利範圍第10項所述之薄膜電晶體，其中該橫樑結構具有三個轉角部。
  12. 如申請專利範圍第10項所述之薄膜電晶體，更包括：一源極以及一汲極，分別形成於與該橫樑結構的兩端相連接的該些多晶半導體圖案中，其中該橫樑結構連接於該源極以及該汲極之間。
  13. 如申請專利範圍第10項所述之薄膜電晶體，其中該絕緣圖案層的材料包括半導體氧化物或半導體氮化物。
  14. 如申請專利範圍第10項所述之薄膜電晶體，其中該些多晶半導體圖案的材料包括多晶矽、多晶鍺或多晶矽鍺。
  15. 如申請專利範圍第10項所述之薄膜電晶體，其中該橫樑結構的材料包括多晶矽、多晶鍺或多晶矽鍺。
  16. 如申請專利範圍第10項所述之薄膜電晶體，其中該閘極的材料包括金屬或半導體。
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