TWI387976B - Non-volatile storage with individually controllable shield plates between storage elements, operating method and fabricating method thereof - Google Patents

Description

Non-volatile storage device capable of separately controlling barrier plates between storage elements, operation method thereof and manufacturing method thereof

This invention relates to non-volatile memory.

This application is related to the United States Patent Application No. ___ (File No. SAND-1196US1) in the co-pending application entitled "Non-Volatile Storage With Individually Controllable Shield Plates Between Storage Elements", and US Patent Application Serial No. ___ (File No. SAND-1196US2), entitled "Method For Fabricating Non-Volatile Storage With Individually Controllable Shield Plates Between Storage Elements," which is incorporated by reference. The manner is incorporated herein.

Semiconductor memory has become increasingly popular in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically erasable and programmable read-only memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. In contrast to conventional full-featured EEPROMs, in the case of flash memory (also a type of EEPROM), the contents of the entire memory array or the contents of a portion of the memory can be erased in one step.

Both conventional EEPROM and flash memory utilize a floating gate that is positioned above and insulated from one of the channel regions of the semiconductor substrate. The floating gate is positioned between the source region and the drain region. The control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage (V _TH ) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.

Some EEPROM and flash memory devices have floating gates for storing two ranges of charge, and thus, the memory elements can be programmed/erased between two states (eg, erased state and stylized state). except. This flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one data bit.

A multi-state (also known as multi-level) flash memory device is implemented by identifying a plurality of different allowed/effectively programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value of a set of data bits encoded in the memory device. For example, when each memory element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the element can store two data bits.

Typically, the program voltage V _PGM applied to the control gate during program operation is applied as a series of pulses whose magnitude increases with time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size with each successive pulse, for example, 0.2 V to 0.4 V. V _PGM can be applied to the control gate of the flash memory component. During the period between program pulses, a verification operation is performed. That is, the stylized levels of each of the elements in a group of elements are read in parallel between consecutive stylized pulses to determine whether they are equal to or greater than the verify level to which the elements are programmed. For a multi-state flash memory device array, a verification step can be performed on each state of the component to determine if the component has reached its data association verification level. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation on three comparison points.

In addition, when programming a EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), V _PGM is typically applied to the control gate and the bit line is grounded, thereby Electrons of a cell or a channel of a memory element (eg, a storage element) are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element rises such that the memory element is considered to be in a stylized state. U.S. Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory", entitled "Source Side Self Boosting Technique For Non-Volatile Memory", U.S. Patent No. 6,859,397, issued Feb. 3, 2005. Find out more about this stylization; the entire contents of these are incorporated herein by reference.

However, as the device size scales down, various challenges arise. For example, floating gates and floating gate coupling become more problematic, resulting in a widerned threshold voltage distribution and a reduced coupling ratio from control gate to floating gate.

The present invention addresses the above and other problems by providing a method for operating a non-volatile reservoir having separately controllable barrier panels between storage elements.

In one embodiment, a method package for operating a non-volatile storage Include: applying a programmed voltage to a selected one of the set of word lines, wherein the word line is in communication with an associated plurality of non-volatile storage elements; and coupling the voltage to the set of barrier boards during application of the stylized voltage Each barrier panel, wherein each barrier panel is electrically conductive and extends between different adjacent non-volatile storage elements associated with adjacent word lines.

In another embodiment, a method for operating a non-volatile storage device includes applying a voltage to at least one non-volatile storage element of the set of word lines for sensing a non-volatile storage element set The selected word line used in the sensing operation of the condition, wherein the word line is in communication with the non-volatile storage element and the selected word line is in communication with the at least one non-volatile storage element. The method further includes coupling a voltage to the set of barrier plates during application of the voltage, wherein each barrier plate extends between different adjacent non-volatile storage elements associated with adjacent word lines; and sensing at least one non-volatile The condition of the storage component.

In another embodiment, a method for operating a non-volatile memory includes applying a voltage to a first set of word lines in communication with a first set of non-volatile storage elements, and applying a voltage to An operation involving a first set of non-volatile storage elements is performed by a first set of barrier panels extending between different adjacent non-volatile storage elements associated with adjacent word lines of the first set of word lines. A first set of non-volatile storage elements and a second set of non-volatile storage elements are formed on a common p-well. The method further includes, when performing the operation, allowing a voltage to float on a second set of word lines in communication with the second set of non-volatile storage elements, and associated with adjacent word lines of the second set of word lines Between different adjacent non-volatile storage elements Floating on the second set of extended barrier panels.

The present invention provides a method for operating a non-volatile reservoir having separately controllable barrier panels between storage elements.

One example of a memory system suitable for use in practicing the present invention uses a NAND flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series connected transistors and select gates are referred to as NAND strings. Figure 1 is a top plan view showing a NAND string. Figure 2 is its equivalent circuit. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 that are connected in series and sandwiched between a first select gate 120 and a second select gate 122. The gate 120 gate is selected to be connected to the NAND string of the bit line 126. The gate 122 gate is selected to be connected to the NAND string of the source line 128. Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is coupled to word line WL3 (or provided by a portion of word line WL3), control gate 102CG is coupled to word line WL2, control gate 104CG is coupled to word line WL1, and control gate 106CG is coupled to word Line WL0. In one embodiment, transistors 100, 102, 104, and 106 are each a storage element, also referred to as a memory unit. In other embodiments, storing The component may comprise a plurality of transistors or may be different from the storage elements depicted in Figures 1 and 2. The selection gate 120 is connected to the selection line SGD. The selection gate 122 is connected to the selection line SGS.

Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture for a flash memory system using a NAND structure would include several NAND strings. For example, three NAND strings 320, 340, and 360 are shown in a memory array with more NAND strings. Each of the NAND strings includes two select gates and four storage elements. Although four storage elements are illustrated for simplicity, modern NAND strings can have up to thirty-two or sixty-four storage elements, for example.

For example, NAND string 320 includes select gates 322 and 327, and storage elements 323 through 326, NAND string 340 includes select gates 342 and 347, and storage elements 343 through 346, and NAND string 360 includes select gates 362 and 367. And storage elements 363 to 366. Each NAND string is connected to the source line by its select gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The various NAND strings 320, 340, and 360 are connected to individual bit lines 321, 341, and 361 by selection transistors in select gates 322, 342, 362, and the like. These selective transistors are controlled by the drain select line SGD. In other embodiments, the select lines need not be common among the NAND strings; that is, different select lines can be provided for different NAND strings. Word line WL3 is coupled to the control gates of storage elements 323, 343, and 363. Word line WL2 is coupled to the control gates of storage elements 324, 344, and 364. Word line WL1 is coupled to the control gates of storage elements 325, 345, and 365. Word line WL0 is coupled to the control gates of storage elements 326, 346, and 366. everyone The meta-line and individual NAND strings contain rows or sets of storage elements. The word lines (WL3, WL2, WL1, and WL0) contain arrays or sets of columns. Each word line connects the control gate of each of the storage elements in the column. Alternatively, the control gate can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line.

Each storage element can store data. For example, when storing a digital data bit, the range of possible threshold voltages (V _TH ) of the storage elements is divided into two ranges of assigned logical data "1" and "0". In one example of a NAND type flash memory, the _VTH is negative after the storage element is erased and is defined as a logic "1." V _TH is positive after the program operation and is defined as a logical "0". When the _VTH is negative and an attempt is made to read, the storage element will turn "on" to indicate that a logical "1" is being stored. When the _VTH is positive and a read operation is attempted, the storage element will not be turned on and this indication stores a logic "0". The storage element can also store multiple information levels, for example, multiple digital data bits. In this case, the range of V _TH values is divided into the number of data levels. For example, if four information levels are stored, there will be four _VTH ranges assigned to the data values "11", "10", "01" and "00". In one example of a NAND type memory, the _VTH is negative after the erase operation and is defined as "11." Positive V _TH values are used for states "10", "01", and "00". The specific relationship between the data programmed into the storage element and the threshold voltage range of the component depends on the data encoding scheme used to store the component. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, the entire contents of each of each of each of each Program.

Examples of NAND-type flash memory and its operation are provided in U.S. Patent Nos. 5,386,422, 5,522,580, 5,570,315, 5,774,397, 6,046,935, 6,456,528 and 6,522,580, each of which One is incorporated herein by reference.

When the flash storage component is programmed, a program voltage is applied to the control gate of the storage component and the bit line associated with the storage component is grounded. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the _{VTH of the} storage element rises. To apply the program voltage to the control gate of the program element being programmed, the program voltage is applied to the appropriate word line. As discussed above, one of the storage elements in each of the NAND strings shares the same word line. For example, when the storage element 324 of FIG. 3 is programmed, the program voltage will also be applied to the control gates of storage elements 344 and 364.

However, program disturb can occur at the suppressed NAND string during stylization of other NAND strings, and sometimes at the programmed NAND string itself. Program disturb occurs when the threshold voltage of the unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements. Program disturb can occur on previously programmed storage elements and erased storage elements that are still not programmed. Various program disturb mechanisms can limit the available operational windows of non-volatile memory devices such as NAND flash memory.

For example, if NAND string 320 is suppressed (eg, it is an unselected NAND string that does not contain a currently-synchronized storage element) and NAND string 340 is being programmed (eg, it is a storage element containing the current positive stylization) Program disturb may occur at NAND string 320. For example, if the pass voltage V _PASS is low, the channel of the inhibited NAND string is not boosted well, and the selected word line of the unselected NAND string can be unintentionally programmed. In another possible scenario, boosting can be reduced by gate induced dipole leakage (GIDL) or other leakage mechanisms, resulting in the same problem. Program disturb can also be attributed to other effects such as shifting of the _VTH due to charge storage elements that are capacitively coupled to other adjacent storage elements that are later programmed. Program disturb can be reduced by the barrier board configuration and control techniques described herein.

Figure 4 depicts a cross-sectional view of a NAND string. The view is simplified and not to scale. The NAND string 400 includes a source side select gate 406, a drain side select gate 424, and eight storage elements 408, 410, 412, 414, 416, 418, 420, and 422 formed on the substrate 490. The assembly can be formed on the p-well region 492, which itself is formed in the n-well region 494 of the p-type substrate region 496. These regions are collectively part of the substrate 490. The n well can be formed in the p substrate. In addition to the bit line 426 having the potential V _BL , a power line 404 having a potential V _SOURCE is provided. The word line receives individual voltages depending on the operation being performed (eg, stylized, sensed (read or verified), or erased). In addition, the control gate of the memory storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend via control gates of storage elements 408, 410, 412, 414, 416, 418, 420, and 422, respectively. In one method, an example of the source/drain regions shown at 430 is provided between the storage elements by doping the p-well regions 492 after forming the storage elements. The source side of the word line or non-volatile storage element refers to the side facing the source end of the NAND string (eg, at power line 404), and the drain side of the word line or non-volatile storage element The side of the drain end of the NAND string (e.g., at bit line 426).

Figure 5 depicts a cross-sectional view of a NAND string with a barrier plate with source/drain regions provided in a substrate between storage elements. Here, a plurality of barrier sheets are provided from a conductive material to provide a barrier to electromagnetic radiation between adjacent floating gates of the non-volatile storage elements. The electrically conductive material may comprise a metal such as W or Ta, which may be used with barrier metal such as WN, TaN or TiN. The conductive material may include doped polysilicon or a telluride such as WSi, TiSi, CoSi or NiSi. For example, barrier panel SP0 500 is provided between SGS 406 and storage element 408, barrier panel SP1 502 is provided between storage element 408 and storage element 410, and barrier panel SP2 504 is provided between storage element 410 and storage element 412 The barrier panel SP3 506 is provided between the storage element 412 and the storage element 414, the barrier panel SP4 508 is provided between the storage element 414 and the storage element 416, and the barrier panel SP5 510 is provided between the storage element 416 and the storage element 418, the barrier A plate SP6 512 is provided between the storage element 418 and the storage element 420, a barrier plate SP7 514 is provided between the storage element 420 and the storage element 422, and a barrier plate SP8 516 is provided between the storage element 422 and the SGD 424. Each barrier panel or component can be located between floating gates of adjacent storage elements associated with adjacent word lines. For example, this configuration reduces the floating gate and floating gate coupling during a read or program operation. Note that the barrier board does not have to extend to the depicted storage element/word line top. However, each barrier panel can extend to the top or beyond the storage element/word line to also reduce control gate/word line coupling to the floating gate. In one method, the barrier panel can have a generally rectangular cross section.

By coupling the desired voltage to each barrier panel, the barrier panel can be individually controllable to optimize its effects during stylization, sensing (read/verify), and erase operations. This is an advantage over using a method that can control the barrier panel together. In addition, the barrier panel allows for reduced use of the program voltage because it provides a coupling of the voltage to the floating gate of the programmed storage element. As a result, program disturb is reduced.

Figure 6 depicts a cross-sectional view of a NAND string with a barrier plate in which source/drain regions are not provided in the substrate between the storage elements. In an embodiment, it is not necessary to provide a source/drain region in the p-well region 492 of the substrate because field induced conductivity can be provided between the storage elements due to the barrier plate. For example, during a sensing operation such as reading or verifying, a conductive path can be established in the NAND string when the selected storage element is in an on/conducting state. The conductive path can be formed via a drain select gate, a barrier plate, a word line/control gate, and a source select gate (eg, self-selected gates SGD 424 to SP8 516, to WL7, to SP7 514, Up to WL6, to SP6 512, etc. until the selection gate SGS 406 and the source are reached) is established between the bit line contact point and the cell source contact point. Basically, when an appropriate voltage, such as about 4 V to 5 V, is applied to the barrier panel and VSS = 0 V, for example, applied to the word line, a virtual junction is formed between the storage elements. The sensing operation is thus not dependent on the conductive path in the substrate. In addition, because the barrier panels are individually controllable, their voltage can be optimally adjusted according to the control scheme. This virtual junction The use is also beneficial to prevent short channel effects where source/drain regions are not provided. In addition, avoiding the need for source/drain regions avoids the corresponding steps in the manufacturing process.

To establish a virtual junction by field induced conductivity between the storage element and the barrier panel, a positive voltage is applied to the barrier panel and the storage element. However, due to the barrier plate voltage coupling to the floating gate, the barrier plate voltage will affect the selected word line read voltage. The coupling will be proportional to the barrier panel voltage x coupling ratio C (SP-FG/total FG) with a coupling ratio of approximately 5% to 15%. If the barrier voltage is high, the selected word line read voltage will increase. To reduce the virtual source-drain junction, a higher barrier voltage should be used, and to lower the selected word line read voltage, a lower barrier voltage should be used. To address these conflicting objectives, in a possible approach, alternating higher and lower barrier panel voltages (VRSPH and VRSPL, respectively) can be used on alternate barrier boards. However, it is also possible to use a common barrier panel voltage (VRSP) on all barrier boards.

The process for fabricating a non-volatile reservoir device having a barrier panel is now discussed.

Figure 7a depicts a layered semiconductor device showing a cross-sectional view across a NAND string. Depicting the intermediate stages of manufacturing. The formation of the device to this point can follow conventional techniques in which a first dielectric layer 710 (eg, a gate oxide layer) is formed over the substrate 712 and then a first polysilicon (poly) layer 708 is formed on the first On the dielectric layer 710. A first polysilicon layer 708 (which is doped such that it is electrically conductive) is used to form a floating gate of the storage element. A shallow trench isolation (STI) structure 714 is formed by patterning the substrate 712 and etching trenches through the first polysilicon layer 708 and the first dielectric layer 710. The trench also extends into the substrate 712. STI trench by material (such as SiO ₂ of a suitable dielectric material) is filled to provide electrical isolation between NAND strings. Thus, the strip of STI material forms an STI structure 714 that extends across the substrate 712 separated by the strip of first polysilicon layer 708 (in a direction perpendicular to the cross-section of the pattern).

Subsequently, a second dielectric layer 706, such as an O-N-O layer, is provided over the polysilicon layer 708. The O-N-O layer is a three-layer dielectric formed of hafnium oxide, tantalum nitride, and hafnium oxide. A second polysilicon layer 704 is deposited that covers the strips of STI structure 714 and first polysilicon material 708. The doped and electrically conductive second polysilicon layer 704 is separated from the strip of the first polysilicon 710 by the second dielectric layer 706. The second polysilicon layer 704 is used to form word gates and control gates of the storage elements. A mask layer 702 is formed on the second polysilicon layer 704. In this case, the mask layer 702 is formed of a dielectric such as tantalum nitride (SiN), but other suitable mask materials may also be used.

Figure 7b depicts a view of the NAND string of the layered semiconductor device of Figure 7a, wherein the photoresist layer is coated and patterned. Figure 7b shows a cross section of the NAND array of Figure 7a in a direction at right angles to the cross section of Figure 7a. Thus, Figure 7b shows a single strip of first polysilicon material 708 in cross section, with a second polysilicon layer 704 covering the strip. Figure 7b also shows a portion of the photoresist (PR) covering the mask layer 702. The patterned photoresist layer 716 is formed by coating a photoresist blanket and then patterning the photoresist using a lithography process. In one method, the photoresist is patterned by exposure to UV light, but other patterning processes such as electron beam lithography can also be used.

Figure 7c depicts the layered semiconductor device of Figure 7b after photoresist refinement. Resist fine graining involves subjecting a portion of the photoresist to etching to remove at least a certain photoresist And make the part of the photoresist narrower. Conventional etching such as dry etching can be used in this step.

Figure 7d depicts the layered semiconductor device of Figure 7C after SiN etching and photoresist stripping. After the resist is finely granulated, the finely granulated portion of the photoresist is used to pattern the underlying SiN mask layer 702. Etching is performed such that the unexposed portion of the mask layer 702 is removed. The remainder of the photoresist 716 is then removed. Figure 7d shows the resulting structure along the same cross section as Figure 7c. The etching stops when the second polysilicon layer 704 is reached.

FIG. 7e layered semiconductor device of FIG 7d, after silicon dioxide (SiO ₂₎ is deposited depicted. The SiO ₂ layer 718 is formed as a third dielectric layer covering the mask portion of the SiN layer 702 and the exposed region of the second polysilicon layer 704. In one method, the SiO ₂ layer 718, which may be formed as a blanket by conventional processes such as chemical vapor deposition (CVD), may be thicker than the dielectric layers 706 and 710. The SiO ₂ layer 718 extends along the exposed portion of the second polysilicon and along the top surface and sidewalls of the mask portion 702.

Figure 7f depicts the layered semiconductor device of Figure 7e after providing a photoresist mask that selects a gate. The photoresist portions 719 and 720 of the mask can be formed by masking the structure with a photoresist, followed by patterning the photoresist using a lithography process to remove unwanted portions of the photoresist. The photoresist portions 719 and 720 extend over portions of the SiO ₂ layer 718 that directly cover the second polysilicon layer 704. An etch is then performed to remove the specific exposed portion of the SiO ₂ layer 718. The photoresist mask can also be used to subsequently form areas of the word line and barrier contact points.

FIG layered semiconductor device in FIG. 7f 7g after the SiO ₂ etching, and photoresist stripping is depicted. In one method, an anisotropic etch such as reactive ion etching (RIE) is used such that the SiO ₂ layer 718 is etched through some locations, but portions of the SiO ₂ layer 718 remain along the sidewalls of the SiN mask portion 702 as sidewall spacers. Things. The size of the sidewall spacers is determined by the thickness of the SiO ₂ layer 718 and by the nature of the anisotropic etch used. After the etching is completed, photoresist stripping is also performed to remove the photoresist portions 719 and 720. The sidewall spacers that then establish the location of the gate line and word line need not be independently aligned.

FIG. 7h depicts the SiN layer 702 is removed by wet etching of the portion, whereby the position covering the second polysilicon layer 704 in FIG. 7g layered retention portion after the SiO ₂ layer 718 of the semiconductor device. Subsequently, the remaining portion of the SiO ₂ layer 718 serves as an etch mask for the patterned underlying layer to form a memory array.

In particular, Figure 7i depicts the layered semiconductor device of Figure 7h after performing an etching step to etch through the polysilicon layer 704, stopping at the O-N-O layer 706.

Figure 7j depicts the layered semiconductor device of Figure 7i after O-N-O and poly etch. Here, the O-N-O layer 706, the polysilicon layer 708, and the dielectric layer 710 are etched and stopped at the substrate 712. This etching step divides the polysilicon layer 704 into individual word lines and divides the polysilicon layer 708 into separate floating gates. The word lines form a control gate that covers the floating gates in the individual storage elements 721. Selective gates 723 and 724 are similarly formed. Since the word line and the floating gate are formed by the same etching step, they are self-aligned. The source/drain regions 722 between the storage elements 721 can also be provided by implanting dopants into the exposed regions of the substrate 712. In one method, the exposed regions are located between the floating gates such that they connect the storage elements of the NAND strings.

Figure 7k depicts the layered semiconductor device of Figure 7j after forming a barrier plate by polysilicon deposition and chemical mechanical polishing (CMP). Dielectric layer 721 is deposited on the layered structure and polysilicon is deposited on the dielectric layer. In an example embodiment, the dielectric layer comprises _{SiO 2, SiO 2 -SiN-SiO} 2, SiO 2 -AlO-SiO 2 or SiO2-HfO-SiO _2, having a physical thickness of about 9 nm to 12 nm and of from about 7 nm to Effective thickness of 11 nm. A CMP is performed to planarize the surface. The polysilicon can be doped to provide the desired conductivity. The memory array can then be covered by a protective layer such as a thick dielectric layer or other protective material. The resulting structure includes a barrier plate 725 formed between adjacent storage elements and between a select gate and a storage element adjacent the select gate. The barrier panels 725 are insulated from each other and from the storage element such that they are individually controllable. Each barrier panel extends between adjacent storage elements associated with adjacent word lines. The barrier board also traverses the NAND string extension. As a result, various optimized control modes can be provided during stylized, read, and erase operations as described further below.

In the above figures, the simplified example already has only four storage elements in the NAND string. In practice, more storage elements can be provided in the NAND string. In addition, the fabrication process covers a wider area of the substrate such that many of the collections of NAND strings are formed on a common substrate. In addition, not all details are depicted, and the drawings are not necessarily to scale. The following figures are similarly not necessarily all of the details. Also, note that the shades and patterns used do not necessarily correspond to the previous figures.

Figure 8a depicts a top or plan view of the layered semiconductor device of Figure 7b. In this and the following figures, the regions of the substrate that result in the formation of two sets of storage elements and associated word lines, barrier plates, and contact points are depicted. Each set of storage elements includes eight word lines and nine barrier boards. In addition, source select gates are provided in regions 802 and 804, while drain select gates are provided in regions 800 and 806. In detail, the patterned photoresist portion 801 is exhibited. The extension extends across the memory array to form a closed loop. In some memory arrays, several similar concentric circuits can be used. Concentric openings are similarly formed between the photoresist portions 801 except for various openings that are subsequently used to provide the word line and barrier plate contact points.

Figure 8b depicts a top view of the layered semiconductor device of Figure 7c after performing photoresist refinement. As discussed, this results in a narrowed photoresist portion 810.

Figure 8c depicts a top view of the layered semiconductor device of Figure 7d after SiN etching and photoresist stripping. In this step, the SiN layer is patterned based on the photoresist layer and the photoresist layer is removed.

Figure 8d depicts a top view of the layered semiconductor device of Figure 7f. The SiO ₂ deposition is performed across the layered structure and a photoresist mask such as the example mask 810 is provided in the regions used to form the word line and barrier plate contact points.

Figure 8e depicts a top view of the layered semiconductor device of Figure 7g. SiO ₂ etching and photoresist stripping were performed, and SiN portions and SiO ₂ sidewall spacers were retained.

Figure 8f depicts a top view of the layered semiconductor device of Figure 7h. The wet etch removes portions of the SiN layer, thereby retaining portions of the SiO ₂ sidewall spacers.

Figure 8g depicts a top view of a layered semiconductor device formed by the device of Figure 8f, showing the word line contact points and barrier plate contact points shared by the two sets of storage elements. After the process depicted in Figures 7i through 7k, the word lines and barrier plates and their contact points are formed. In the drawing, "W" indicates the word line contact point and "S" indicates the barrier board contact point. These contact points are contact points that can be coupled to word lines or barrier boards, respectively, depending on the desired control scheme. For example, the first set of storage elements 820 includes a plurality of barrier plates and words that alternately extend between the source select gate 824 and the drain select gate 822. line. Similarly, the second set of storage elements 826 includes a plurality of barrier and word lines that alternately extend between source select gate 828 and drain select gate 830. The word lines are shared by two sets of storage elements. For example, word line contact 832 is coupled to WL0, which extends in a circuit that passes through two sets of storage elements. Likewise, word line contact 834 is coupled to WL1, word line contact 836 is coupled to WL2, word line contact 838 is coupled to WL3, word line contact 840 is coupled to WL4, and word line contact 842 is coupled to WL5, word line contact Point 844 is coupled to WL6 and word line contact 846 is coupled to the last word line WL7. Again, eight word lines are only provided as examples.

Similarly, the barrier panel is shared by two sets of storage elements. For example, the barrier board contact 850 is coupled to the first barrier panel Sp0, which extends in a circuit that passes through two sets of storage elements. In particular, SP0 extends between SGS 824 and WL0 in a first set of storage elements 820 and between SGS 828 and WL0 in a second set of storage elements 826. Barrier panel contact 852 is coupled to SP1, which extends between WL0 and WL1. The barrier plate contact 854 is coupled to SP2, which extends between WL1 and WL2. Barrier panel contact 856 is coupled to SP3, which extends between WL2 and WL3. Barrier panel contact 858 is coupled to SP4, which extends between WL3 and WL4. Barrier panel contact 860 is coupled to SP5, which extends between WL4 and WL5. Barrier panel contact 862 is coupled to SP6, which extends between WL5 and WL6. Barrier panel contact 864 is coupled to SP7, which extends between WL6 and WL7. Barrier panel contact 866 is coupled to SP8, which extends between WL7 and SGD 822 in a first set of storage elements 820 and between WL7 and SGD 830 in a second set of storage elements 826.

In this configuration, the voltage can be separately coupled to a given word line or barrier board that is shared among the two sets of storage elements 820 and 826. A suitable control circuit can be used to couple the desired voltage to the contact point.

Note that the configuration shown is only an example, as other configurations are possible. For example, one or more additional sets of storage elements can be disposed to the left or right of the collection of storage elements 820 and 826. In this case, the horizontally extending word lines in the drawing may further extend horizontally across the additional set of storage elements. Moreover, for example, one or more sets of storage elements can be provided in a region of the word line that extends vertically in the drawing.

Figure 8h depicts a top view of an alternative layered semiconductor device showing common word line contact points and individual barrier board contact points for each set of storage elements. In contrast to the configuration of Figure 8g, additional barrier panel contacts 872-886 are added at the side of the collection of storage elements 820 and 826 opposite the side where the contact points discussed in connection with Figure 8g are located. Light lithography techniques similar to those previously discussed can be used to create such additional barrier plate contacts. In particular, due to isolation structures 887 and 888, such additional barrier plate contacts are coupled to a barrier panel that extends through the second set of storage elements 826 rather than the first set of storage elements. The isolation structure can be formed from a dielectric material to short the barrier panel using techniques well known to those skilled in the art to extend the barrier in the first set of storage elements 820 and to the contact points on the right hand side of the drawing. The board is not in communication with the second set of storage elements 826, and the barrier boards extending in the second set of storage elements 826 and coupled to the contact points on the left hand side of the drawing are not in communication with the first set of storage elements 820.

In particular, on the left hand side of the figure, the barrier board contact 872 is coupled to SP1, barrier plate contact 874 is coupled to SP2, barrier plate contact 876 is coupled to SP3, barrier plate contact 878 is coupled to SP4, barrier plate contact 880 is coupled to SP5, and barrier plate contact 882 is coupled to SP6, barrier plate contact Point 884 is coupled to SP7 and barrier board contact 886 is coupled to SP8. Note that in one approach, barrier plate contact 850 (see Figure 8g) can be used to store two sets of components. It is also possible to provide a separate barrier board contact point coupled to a separate barrier between SGS 824 and WL0 in the first set of storage elements 820 and between SGS 828 and WL0 in the second set of storage elements 826. In this case, a suitable insulating structure is used to insulate the barrier sheets from each other.

In this configuration, the voltages can be individually coupled to a given word line that is shared among the two sets of storage elements and individually coupled to a given barrier board associated with a given set of storage elements. As before, an appropriate control circuit can be used to couple the desired voltage to the contact point.

Figure 8i depicts a top view of an alternative layered semiconductor device showing separate word line contact points and barrier board contact points for each set of storage elements. Additional word line contacts 890 through 897 can be added to the left of the set of storage elements 820 and 826 as compared to the configuration of Figure 8h. Light lithography techniques similar to those previously discussed can be used to establish such additional word line contacts. In particular, due to isolation structures 898 and 899, the additional word line contacts are coupled to word lines that extend through the second set of storage elements 826 rather than the first set of storage elements. The isolation structures can be formed from a dielectric material to short the word lines using techniques well known to those skilled in the art, such that the contact points extending in the first set of storage elements 820 and coupled to the right hand side of the pattern can be used. The line is not in communication with the second set of storage elements 826, and is in the storage element 826 The word lines extending in the two sets and coupled to the contact points on the left hand side of the drawing are not in communication with the first set of storage elements 820.

In particular, on the left hand side of the figure, word line contact 890 is coupled to WL0, word line contact 891 is coupled to WL1, word line contact 892 is coupled to WL2, and word line contact 893 is coupled to WL3, word line contact Point 894 is coupled to WL4, word line contact 895 is coupled to WL5, word line contact 896 is coupled to WL6, and word line contact 897 is coupled to WL7.

In this configuration, the voltages can be individually coupled to a given word line associated with a given set of storage elements and to a given barrier board associated with a given set of storage elements. As before, an appropriate control circuit can be used to couple the desired voltage to the contact point.

Figure 9 depicts four blocks or other sets of storage elements in an array, where the word lines and barrier boards are shared by the block pairs. Here, four blocks 900, 910, 920, and 930 are depicted as examples, but additional block pairs may be used. In addition, blocks can be provided on a common p-well. In a possible configuration, blocks n and n+1 share the word line and the barrier board, and blocks n+2 and n+3 share the word line and the barrier board. As an illustration, eight word lines WL0 to WL7 and nine barrier boards SP0 to SP8 are provided. The word line is depicted by the solid line on the right hand side of the block, while the barrier board is depicted by a dashed line. The drain select gate (SGD) and the source select gate (SGS) are also depicted for each block. In one method, each block decodes the shared column/word line and the barrier board because the word lines and the barrier boards are shared, while each block has its own select gate source and drain decoding.

Figure 10 depicts a process for making a non-volatile reservoir with a barrier panel. Step 1000 includes forming a layered structure, for example, as depicted in Figure 7a. Step 1005 includes applying a photoresist and a patterned photoresist (see Figure 7b). Step 1010 includes photoresist refinement (see Figure 7c). Step 1015 includes SiN etching and photoresist stripping. Step 1020 includes SiO ₂ deposition (see Figure 7e). Step 1025 includes coating a photoresist mask for selecting a gate (see Figure 7f). Step 1030 includes performing SiO ₂ etching and photoresist stripping. Step 1035 includes performing a SiN wet etch (see Figure 7h). Step 1040 includes performing a polysilicon etch for the polysilicon layer above the word line (see Figure 7i). Step 1045 includes etching the O-N-O layer and the lower polysilicon layer for the floating gate (see Figure 7j). Step 1050 includes depositing and grinding a polysilicon layer to provide a barrier plate (see Figure 7k).

11 is a flow chart depicting one embodiment of a method for staging non-volatile memory. In one implementation, the components are erased (by block or other unit) prior to stylization. In step 1100, the "data load" command is issued by the control circuit. In step 1105, the address data of the specified page address is input from the controller or host to the decoder. In step 1110, the program data page of the addressed page is input to the data buffer for stylization. The data is latched into the appropriate set of latches. In step 1115, a "stylized" instruction is issued.

Triggered by the "stylized" instruction, the data latched in step 1110 will use the stepping pulses 1205, 1210, 1215, 1220, 1225, 1230 of the burst 1200 of FIG. 12 applied to the appropriately selected word line, 1235, 1240, 1245, 1250, ... are programmed into the selected storage element. In step 1120, the program voltage V _{PGM is} initialized to a start pulse (eg, 13 V or other value) and the program counter (PC) is initialized to zero. In step 1125, the barrier plate voltage for stylization is applied according to the desired programmatic control scheme (see further examples below). In step 1130, a first V _PGM pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. If a logic "0" is stored in a specific data latch indicating that the corresponding storage element should be programmed, the corresponding bit line is grounded. On the other hand, if the logic "1" is stored in a specific latch, indicating that the corresponding storage element should remain in its current data state, connect the corresponding bit line to Vdd (about 2 V internal regulation voltage) to suppress the program. Chemical.

In step 1135, the barrier panel voltage is applied according to the desired sensing control scheme (see further examples below). In step 1140, the status of the selected storage element is verified. If it is detected that the target threshold voltage of the selected storage element has reached the proper level, the data stored in the corresponding data latch is changed to logic "1". If it is detected that the threshold voltage has not reached the proper level, the data stored in the corresponding data latch has not changed. In this way, the bit lines having the logic "1" stored in the corresponding data latch need not be programmed. When all data latches store a logic "1", all selected storage elements are already programmed. In step 1145 (verification state), a check is made as to whether all data latches store a logical "1". If all data latches store a logic "1", the stylization process is complete and successful because all selected storage elements are programmed and verified. The status of "pass" is reported in step 1150.

If it is determined in step 1145 that not all of the data latches store a logical "1", the stylization process continues. In step 1155, the program counter PC is checked against the program limit value PCmax. An example of one of the program limits is twenty; however, other numbers can be used. If the program counter PC is not less than PCmax, the program process has failed and the status of "failed" is reported in step 1160. If the program counter PC is less than PCmax, V _PGM increments the step size and increments the program counter PC in step 1165 and the process loops back to step 1125.

Figure 12 depicts an example pulse train 1200 applied to a control gate of a non-volatile storage element during stylization. Pulse train 1200 includes a series of program pulses 1205, 1210, 1215, 1220, 1225, 1230, 1235, 1240, 1245, 1250, ... applied to a word line selected for programming. In one embodiment, the stylized pulses have a voltage V _PGM that begins at 13 V and increments (eg, 0.5 V) for each successive stylized pulse until a maximum of 21 V is reached. A system verification pulse in the middle of the program pulse. For example, the set of verification pulses 1206 includes three verification pulses. In some embodiments, there may be a verify pulse for each state (eg, states A, B, and C) that the data is being programmatically programmed. In other embodiments, there may be more or fewer verification pulses.

Figure 13 is a flow chart depicting one embodiment of a process for reading non-volatile memory. The reading process begins at step 1300. In step 1310, the barrier plate voltage for sensing is applied according to the desired control scheme. At step 1320, for example, V _{CGR is} set based on the highest read level. Step 1330 includes applying V _CGR to the selected word line and applying a voltage to the unselected word line in accordance with a control scheme. At step 1340, a determination is made as to when the selected storage element transitions from off to on. If there is a next read level at decision step 1350, then the process continues at step 1320 with a different V _CGR . If there is no next read level, the read process ends at step 1360.

An example control scheme is provided below for illustration. The control scheme is applied to the condition that the word line and the barrier board are shared by the two blocks of the storage element. However, the control scheme can also be used to store a single block or other collection of components. Other control options are also possible.

Table 1 depicts the voltages that may be used for embodiments that do not use source/drain implants during sensing operations (eg, read or verify operations). See also Figure 6. In this and other tables, operations are performed on block n+1, where blocks n and n+1 share the word line and the barrier board. However, the voltages used to perform operations on block n are similar. In particular, the voltages depicted to SGD and SGS applied to block n+1 will be applied to block n, and the voltages depicted to SGD and SGS applied to block n will be applied to block n+1. Similarly, the voltages used to perform operations on block n+2 or n+3 are similar. Moreover, by using the provided voltage control word lines and/or unshared sets of barrier boards, the control scheme can be adapted for use with word lines and/or barrier boards that are not shared among the set of storage elements.

The voltage applied to the drain select gate (SGD), word line, source select gate (SGS), array source, and p well is depicted. In an example implementation, VREAD (read pass voltage applied to unselected word lines) is about 4.5 V, VRSPH (read, barrier, high voltage) is about 4 V, VRSPL (read, barrier, low voltage) ) is about 2 V and VSS (steady state voltage) is about 0 V. Note that in one possible approach, the VRSPL can be about 30% to 90% of the VRSPH. In addition, VRSPH can be about 50% to 150% of VREAD. VCGR (Control Gate Read Voltage) is applied to the selected word line and is paired with different stylized states or conditions The different comparison levels of the association change. The VGCRs are set at different levels at different times to determine when the selected storage element transitions between the on/off states. The value "i" indicates the number of word lines, and the word line is numbered from the WL0 on the source side of the NAND string to WLi-1 on the drain side of the NAND string. The barrier plate is numbered from SP0 on the source side of WL0 to SPi on the drain side of WLi-1.

Apply VREAD to the unselected word line while applying VCGR to the selected word line. In addition, VRSPL is applied to the barrier panel adjacent to the selected word line. Specifically, VRSPL is applied to SPn located on the source side of WLn and applied to SPn+1 located on the drain side of WLn. The remaining barrier boards alternately receive VRSPH and VRSPL. For example, VRSPH is located on SPn+2, VRSPL is located on SPn+3, VRSPH is located on SPn+4, and VRSPH is located on SPn-1, VRSPL is located on SPn-2, and VRSPH is located on SPn-3. . In addition, the voltage floats on the word lines and barrier plates of the other block pairs (blocks n+2 and n+3) formed on the same p-well as the blocks n and n+1.

Table 2 depicts an alternative to the control scheme of Table 1 and can be used to sense in the presence or presence of a passive pole-drain implant. Here, a single barrier panel voltage VRSP is used to replace the high and low barrier panel voltages VRSPH and VRSPL, respectively. In an example implementation, the VRSP is about 4 V to 5 V. For example, VRSP can be about 50% to 150% of VREAD. VSS (0 V) is applied to the barrier plate adjacent to the selected word line. Specifically, VSS is applied to SPn on the source side of WLn and applied to SPn+1 on the drain side of WLn. The remaining unselected barriers alternately receive VSS and VRSP. For example, VRSP is on SPn+2, VSS is on SPn+3, VRSP is on SPn+4, and VRSP is on SPn-1, VSS is on SPn-2, and VRSP is on SPn-3. Superior.

Table 3 depicts the voltages that can be used during stylized operations for embodiments with or with passive pole/drain implants in self-boost mode. In the example implementation, VPASS (the pass voltage applied to the unselected word line) is about 9 V, VRSPH (program, barrier board, high voltage) is also about 9 V, VRSPL (program, barrier board, The low voltage) is about 6 V and the VDD (internal regulation voltage) is about 2 V. VTH is the threshold voltage for the drain select gate and can range from approximately 0.7 V to 1.2 V. Note that in one possible approach, the VPSPL can be about 50% to 90% of the VPSPH. In addition, VRSPH can be from about 50% to 100% of VPGM. VPGM (stylized voltage) is applied to the selected word line and is typically increased from approximately 13 V to 21 V in a stepwise manner. See Figure 12.

Apply VPASS to the unselected word line while applying VPGM to the selected word line. In addition, VPSPH is applied to the barrier panel adjacent to the selected word line. Specifically, VRSPH is applied to SPn on the source side of WLn and applied to SPn+1 on the drain side of WLn. The remaining unselected barriers alternately receive VPSPH and VPSPL. For example, VPSPL is located on SPn+2, VPSPH is located on SPn+3, VPSPL is located on SPn+4, etc., and VPSPL is located on SPn-1, VPSPH is located on SPn-2, and VPSPL is located on SPn-3. Superior. In addition, the voltage floats on the word lines of n+2 and n+3 and on the barrier board.

Table 4 depicts the voltages that can be used during stylized operations for embodiments of passive pole/drain implants in the erase region self-boost (EASB) mode. In an example implementation, VPASS is about 9 V, VPSPH is about 10 V, VPSPL is about 6 V and VDD is about 2 V. VPASS is applied to WLn-1 receiving VDD and unselected word lines except WLn-2 receiving 0 V. Apply VPGM to the selected word line. In addition, VPSPH is applied to the barrier panel adjacent to the selected word line. Specifically, VRSPH is applied to SPn on the source side of WLn and applied to SPn+1 on the drain side of WLn. The remaining unselected barriers alternately receive VPSPH and VPSPL, except for SPn-1 and SPn-2 that receive VDD. For example, control provides VPSPL on SPn+2, VPSPH on SPn+3, VPSPL on SPn+4, and VPSPH on SPn-3, VPSPL on SPn-4, VPSPH on SPn-5, and so on. In addition, the voltage floats on the word lines of n+2 and n+3 and on the barrier board.

For memory devices that are programmed in EASB mode, including source-drain implants, the control scheme of Table 4 can be used, with VSS instead of VDD on the specified barrier and word lines.

Table 5 depicts the voltages that can be used during stylized operations for embodiments of passive pole/drain implants in a zone self-boosting (LSB) mode. In an example implementation, VPASS is about 9 V, VPSPH is about 10 V, VPSPL is about 6 V and VDD is about 2 V. VPASS is applied to WLn-1 and WLn+1 receiving VDD and unselected word lines except WLn-2 and WLn+2 receiving 0V. Apply VPGM to the selected word line. In addition, VPSPH is applied to the barrier panel adjacent to the selected word line. Specifically, VRSPH is applied to SPn on the source side of WLn and applied to SPn+1 on the drain side of WLn. The remaining unselected barriers alternately receive VPSPH and VPSPL, except for SPn-1, SPn-2, SPn+2, and SPn+3 that receive VDD. For example, control provides VPSPH on SPn+4, VPSPL on SPn+5, VPSPH on SPn+6, and VPSPH on SPn-3, on SPn-4 VPSPL, VPSPH and the like are provided on SPn-5. In addition, the voltage floats on the word lines of n+2 and n+3 and on the barrier board.

For memory devices that are programmed in the LSB mode, including source-drain implants, the control scheme of Table 5 can be used, with VSS instead of VDD on the specified barrier and word lines.

Table 6 depicts the voltages that can be used during an erase operation for an embodiment with or with a passive pole/drain implant. In an example implementation, the VERASE (erase voltage) is about 20 volts. Applying this relatively high voltage to the p-well while applying VSS to the word lines and barrier plates of the blocks being erased (eg, blocks n and n+1), thereby The charge stored in the floating gate of the storage element is removed. The voltage floats on the word lines n+2 and n+3 and on the barrier board.

The foregoing embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen to best explain the principles of the invention and its application, and the The invention is best utilized with various modifications of the particular use. It is intended that the scope of the invention be defined by the scope of the appended claims.

100‧‧‧Optoelectronics

100CG‧‧‧Control gate

100FG‧‧‧ floating gate

102‧‧‧Optoelectronics

102CG‧‧‧Control gate

102FG‧‧‧ Floating Gate

104‧‧‧Optoelectronics

104CG‧‧‧Control gate

104FG‧‧‧Floating gate

106‧‧‧Optoelectronics

106CG‧‧‧Control gate

106FG‧‧‧ Floating Gate

120‧‧‧First choice gate

120CG‧‧‧Control gate

122‧‧‧Second selection gate

122CG‧‧‧Control gate

126‧‧‧ bit line

128‧‧‧ source line

320‧‧‧NAND strings

321‧‧‧ bit line

322‧‧‧Select gate

323‧‧‧Storage components

324‧‧‧Storage components

325‧‧‧Storage components

326‧‧‧Storage components

327‧‧‧Selected gate

340‧‧‧NAND string

341‧‧‧ bit line

342‧‧‧Select gate

343‧‧‧Storage components

344‧‧‧Storage components

345‧‧‧Storage components

346‧‧‧Storage components

347‧‧‧Selecting the gate

360‧‧‧NAND string

361‧‧‧ bit line

362‧‧‧Select gate

363‧‧‧Storage components

364‧‧‧Storage components

365‧‧‧Storage components

366‧‧‧Storage components

367‧‧‧Select gate

400‧‧‧NAND strings

404‧‧‧Power cord

406‧‧‧Source side selection gate

408‧‧‧Storage components

410‧‧‧Storage components

412‧‧‧Storage components

414‧‧‧Storage components

416‧‧‧Storage components

418‧‧‧Storage components

420‧‧‧Storage components

422‧‧‧Storage components

424‧‧‧汲polar selection gate

426‧‧‧ bit line

430‧‧‧Source/bungee area

490‧‧‧Substrate

492‧‧‧p well area

494‧‧‧n well area

496‧‧‧p-type substrate area

500‧‧‧Barrier SP0

502‧‧‧Barrier SP1

504‧‧‧Barrier SP2

506‧‧‧Barrier SP3

508‧‧‧Barrier SP4

510‧‧‧Barrier SP5

512‧‧‧Barrier SP6

514‧‧‧Barrier SP7

516‧‧‧Barrier SP8

702‧‧‧Mask layer/SiN mask part

704‧‧‧Second polysilicon layer

706‧‧‧Dielectric layer/O-N-O layer

708‧‧‧Polysilicon layer/first polysilicon material

710‧‧‧Dielectric layer/first polysilicon

712‧‧‧Substrate

714‧‧‧Shallow Trench Isolation (STI) Structure

716‧‧‧ patterned photoresist layer

718‧‧‧SiO ₂ layer

719‧‧‧ photoresist part

720‧‧‧ photoresist part

721‧‧‧Storage component/dielectric layer

722‧‧‧Source/bungee area

723‧‧‧Select gate

724‧‧‧Selected gate

725‧‧‧Barrier board

800‧‧‧ area

801‧‧‧ patterned resistive part

802‧‧‧ area

804‧‧‧Area

806‧‧‧Area

810‧‧‧Narrowed photoresist part/mask

820‧‧‧Storage components

822‧‧‧Bungee selection gate

824‧‧‧Source selection gate

826‧‧‧Storage components

828‧‧‧Source selection gate

830‧‧‧Bungee selection gate

832‧‧‧ word line contact points

834‧‧‧Word line contact points

836‧‧‧ word line contact points

838‧‧‧Word line contact points

840‧‧‧ word line contact points

842‧‧‧Word line contact points

844‧‧‧Word line contact points

846‧‧‧Word line contact points

850‧‧‧Barrier plate contact points

852‧‧‧Barrier plate contact points

854‧‧‧Barrier plate contact points

856‧‧‧Barrier plate contact points

858‧‧‧Barrier plate contact points

860‧‧‧Barrier plate contact points

862‧‧‧Barrier plate contact points

864‧‧‧Barrier plate contact points

866‧‧‧Barrier plate contact points

872‧‧‧Barrier plate contact points

874‧‧‧Barrier plate contact points

876‧‧‧Barrier plate contact points

878‧‧‧Barrier plate contact points

880‧‧‧Barrier plate contact points

882‧‧‧Barrier plate contact points

884‧‧‧Barrier plate contact points

886‧‧‧Barrier plate contact points

887‧‧‧Isolation structure

888‧‧‧Isolation structure

890‧‧‧ word line contact points

891‧‧‧Word line contact points

892‧‧‧Word line contact points

893‧‧‧Word line contact points

894‧‧‧ word line contact points

895‧‧‧Word line contact points

896‧‧‧Word line contact points

897‧‧‧Word line contact points

898‧‧‧Isolation structure

899‧‧‧Isolation structure

900‧‧‧ Block

910‧‧‧ Block

920‧‧‧ Block

930‧‧‧ Block

1200‧‧‧pulse

1205‧‧‧Program pulse

1206‧‧‧Verification pulse set

1210‧‧‧Program pulse

1215‧‧‧Program pulse

1220‧‧‧Program pulse

1225‧‧‧Program pulse

1230‧‧‧Program pulse

1235‧‧‧Program pulse

1240‧‧‧Program pulse

1245‧‧‧Program pulse

1250‧‧‧Program pulse

SGD‧‧‧Selection line/dippole selection gate

SGS‧‧‧Select Line/Source Select Gate

SP0‧‧‧ barrier board

SP1‧‧‧ barrier board

SP2‧‧‧ barrier board

SP3‧‧‧ barrier board

SP4‧‧‧ barrier board

SP5‧‧‧ barrier board

SP6‧‧‧ barrier board

SP7‧‧‧ barrier board

SP8‧‧‧ barrier board

WL0‧‧‧ word line

WL1‧‧‧ word line

WL2‧‧‧ word line

WL3‧‧‧ word line

WL4‧‧‧ word line

WL5‧‧‧ word line

WL6‧‧‧ word line

WL7‧‧‧ word line

Figure 1 is a top plan view of a NAND string.

2 is an equivalent circuit diagram of the NAND string of FIG. 1.

3 is a block diagram of an array of NAND flash memory elements.

Figure 4 depicts a cross-sectional view of a NAND string.

Figure 5 depicts a cross-sectional view of a NAND string with a barrier plate with source/drain regions provided in a substrate between storage elements.

Figure 6 depicts a cross-sectional view of a NAND string with a barrier plate, where the source / The drain region is not provided in the substrate between the storage elements.

Figure 7a depicts a layered semiconductor device showing a cross-sectional view across a NAND string.

Figure 7b depicts a view of the NAND string of the layered semiconductor device of Figure 7a, wherein the photoresist layer is coated and patterned.

Figure 7c depicts the layered semiconductor device of Figure 7b after photoresist refinement.

Figure 7d depicts the layered semiconductor device of Figure 7C after SiN etching and photoresist stripping.

FIG. 7e layered semiconductor device of FIG. 7d after the SiO ₂ deposition is depicted.

Figure 7f depicts the layered semiconductor device of Figure 7e after providing a photoresist mask that selects a gate.

FIG layered semiconductor device in FIG. 7f 7g after the SiO ₂ etching, and photoresist stripping is depicted.

Figure 7h depicts the layered semiconductor device of Figure 7g after SiN wet etching.

Figure 7i depicts the layered semiconductor device of Figure 7h after polysilicon etch.

Figure 7j depicts the layered semiconductor device of Figure 7i after O-N-O and polysilicon etch.

Figure 7k depicts the layered semiconductor device of Figure 7j after forming a barrier plate by polysilicon deposition and CMP.

Figure 8a depicts a top view of the layered semiconductor device of Figure 7b.

Figure 8b depicts a top view of the layered semiconductor device of Figure 7c.

Figure 8c depicts a top view of the layered semiconductor device of Figure 7d.

Figure 8d depicts a top view of the layered semiconductor device of Figure 7f.

Figure 8e depicts a top view of the layered semiconductor device of Figure 7g.

Figure 8f depicts a top view of the layered semiconductor device of Figure 7h.

Figure 8g depicts a top view of a layered semiconductor device formed by the device of Figure 8f, showing the word line contact points and barrier plate contact points shared by the two sets of storage elements.

Figure 8h depicts a top view of an alternative layered semiconductor device showing common word line contact points and individual barrier board contact points for each set of storage elements.

Figure 8i depicts a top view of an alternative layered semiconductor device showing individual word line contact points and barrier board contact points for each set of storage elements.

Figure 9 depicts four blocks of storage elements in which the word lines and barrier boards are shared by block pairs.

Figure 10 depicts a process for making a non-volatile reservoir with a barrier panel.

11 is a flow chart depicting one embodiment of a method for staging non-volatile memory.

Figure 12 depicts an example pulse train applied to a control gate of a non-volatile storage element during stylization.

Figure 13 is a flow chart depicting one embodiment of a process for reading non-volatile memory.

(no component symbol description)

Claims (20)

A method for operating a non-volatile memory, comprising: applying a programmed voltage to one of a plurality of word lines, the plurality of word lines associated with a plurality of non-volatile storage elements Communication; and during the application of the stylized voltage, coupling a voltage to each of the plurality of barrier plates, each barrier plate being conductive and extending between adjacent non-volatile storage elements associated with adjacent word lines . The method of claim 1, wherein: coupling the voltage to each barrier panel comprises applying alternating higher and lower voltages to the barrier plates on the source side and the drain side of the selected word line. Alternate barrier panels. The method of claim 2, wherein the higher voltage is received by the barrier board adjacent to the selected word line on the source side and the drain side. The method of claim 1, wherein: coupling the voltage to each of the barrier boards comprises applying alternating first and second voltages to the drain and source sides of the selected word line The alternating barrier plate, the first voltage being higher than the second voltage. The method of claim 4, wherein: coupling the voltage to each of the barrier boards comprises applying the first voltage to a first barrier adjacent to the selected word line on one of the drain sides of the selected word line A board is applied to a second barrier panel adjacent to the selected word line on one of the source sides of the selected word line. The method of claim 5, wherein: coupling the voltage to each of the barrier plates comprises applying a third voltage to one of the third barrier plates on a source side of the second barrier plate, the third voltage being lower than The second voltage. The method of claim 6, wherein: coupling the voltage to each of the barrier boards comprises applying a fourth voltage to one of the fourth barrier plates on one of the first barrier plates, the fourth voltage being lower than The second voltage. The method of claim 6, wherein: coupling the voltage to each of the barrier boards comprises applying a fourth voltage to a fourth barrier panel on one of the first barrier plates, the fourth voltage and the The third voltage is the same. The method of claim 1, wherein the plurality of non-volatile storage elements are disposed in the NAND string, and the plurality of barrier boards extend across the NAND strings. The method of claim 1, wherein: the voltages are separately coupled to each of the barrier boards. A non-volatile storage device comprising: a substrate on which a plurality of non-volatile storage elements connected in series are formed; a plurality of word lines communicating with the plurality of non-volatile storage elements; and a plurality of barriers A plate, each barrier plate extending across each of the plurality of strings and extending between different adjacent non-volatile storage elements associated with adjacent word lines, each barrier plate being electrically conductive and separately controllable. The non-volatile storage device of claim 11, further comprising: at least one control circuit for separately coupling a voltage to each of the barrier boards. The non-volatile storage device of claim 11, wherein: each non-volatile storage element comprises a floating gate, and each barrier plate comprises a floating gate at least partially adjacent to the different adjacent non-volatile storage elements An electrically conductive material extending between the different adjacent non-volatile storage elements. The non-volatile storage device of claim 11, wherein: the plurality of non-volatile storage elements are disposed in the NAND string, and the plurality of barrier boards extend across the NAND strings. The non-volatile storage device of claim 11, further comprising: a first plurality of electrical contacts carried by the substrate transverse to the substrate for forming an area of the plurality of non-volatile storage elements, the first plurality Each of the electrical contacts is associated with a respective barrier plate for coupling a voltage thereto; and a second plurality of electrical contacts are carried by the substrate transverse to the region, the second plurality Each of the electrical contacts is associated with a respective word line for coupling a voltage thereto. The non-volatile storage device of claim 15, wherein: the first plurality of electrical contacts and the second plurality of electrical contacts are carried by the substrate on a common side of the region. A method for manufacturing a non-volatile storage, comprising: forming a plurality of strings on a substrate to connect non-volatile storage elements in series Forming a plurality of word lines in communication with the plurality of non-volatile storage elements; and forming a plurality of barrier plates, each barrier plate extending across each of the plurality of strings and being associated with an adjacent word line Extending between adjacent non-volatile storage elements, each barrier plate is electrically conductive and separately controllable; and provides at least one control circuit for separately coupling a voltage to each of the barrier plates. The method of claim 17, wherein: each non-volatile storage element comprises a floating gate, and each barrier plate comprises a conductive portion extending at least partially between floating gates of the different adjacent non-volatile storage elements The material extends between the different adjacent non-volatile storage elements. The method of claim 17, wherein: the plurality of non-volatile storage elements are disposed in the NAND string, and the plurality of barrier boards extend across the NAND strings. The method of claim 17, further comprising: forming a first plurality of electrical contacts carried by the substrate transverse to the substrate for forming a region of the plurality of non-volatile storage elements, the first plurality of electrical contacts Each of the electrical contacts in the point is associated with a respective barrier plate for coupling a voltage thereto; and forming a second plurality of electrical contacts carried by the substrate transversely to the region, the second plurality of electrical Each of the contact points is associated with a respective word line for coupling a voltage thereto, the first plurality The electrical contact and the second plurality of electrical contacts are carried by the substrate on a common side of the region.