TWI385406B - Motherboard testing apparatus - Google Patents

Motherboard testing apparatus Download PDF

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TWI385406B
TWI385406B TW97100370A TW97100370A TWI385406B TW I385406 B TWI385406 B TW I385406B TW 97100370 A TW97100370 A TW 97100370A TW 97100370 A TW97100370 A TW 97100370A TW I385406 B TWI385406 B TW I385406B
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transistor
resistor
control circuit
grounded
motherboard
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TW97100370A
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TW200931050A (en
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Jin-Liang Xiong
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Hon Hai Prec Ind Co Ltd
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Description

主機板測試裝置Motherboard test device

本發明係關於一種主機板測試裝置,特別係關於一種可對電腦主機板進行迴圈開關機測試之主機板測試裝置。The invention relates to a motherboard testing device, in particular to a motherboard testing device capable of performing a loop switch test on a computer motherboard.

電腦生產廠商在對電腦之品質驗證過程中,電腦主機板之DC Power on/off測試,即直流開關機測試是一個重要之驗證項目。習知之測試方法是測試人員定期手動按下電腦電源按鍵使得電腦主機板上電,而手動按下電腦電源按鍵之實質是給電腦主機板上之輸入輸出控制器一個低電平訊號,而放開電腦電源按鍵後該輸入輸出控制器又被置回高電平,由此完成電腦開機。在電腦開機後執行測試程式,當開機達到一定之時間後測試人員手動操作電腦軟關機。而當關閉電腦一段時間後又重新按電腦電源按鍵,如此循環往復進行開關機操作,直至測試次數達到預定之次數後停止測試。為了完成此項測試, 需要花費大量之人力,增加了生產成本。In the process of verifying the quality of the computer by the computer manufacturer, the DC Power on/off test of the computer motherboard, that is, the DC switch test is an important verification project. The test method is that the tester manually presses the computer power button periodically to make the computer main board power on, and the essence of manually pressing the computer power button is to give the input and output controller on the computer motherboard a low level signal, and let go. After the computer power button is pressed, the input/output controller is set back to a high level, thereby completing the computer booting. After the computer is turned on, the test program is executed. When the computer is turned on for a certain period of time, the tester manually operates the computer to softly shut down. When the computer is turned off for a while, press the power button of the computer again, and then cycle the operation of the switch machine until the number of tests reaches a predetermined number of times and then stop the test. In order to complete this test, it takes a lot of manpower and increases production costs.

鑒於上述內容,有必要提供一種低成本之主機板測試裝置,可自動對電腦主機板進行迴圈開關機測試。In view of the above, it is necessary to provide a low-cost motherboard test device that can automatically perform a loop switch test on a computer motherboard.

一種主機板測試裝置,包括:一脈波訊號發生電路,其包括一輸入端和一輸出端,該輸入端接收一待機電壓訊號,並在輸出端產生一脈波訊號;一第一控制電路,其包括一第一電晶體、一第二電晶體、一第三電晶體、一場效電晶體、一二極體、一第一電阻、一第二電阻、一第三電阻和一第一電容,該第一電晶體之基極同脈波訊號發生電路之輸出端相連,該第一電晶體之集極同第二電晶體之基極相連,該第一電晶體之射極接地,該第二電晶體之集極連接一電腦主機板上之輸入輸出控制器,該第二電晶體之射極同第三電晶體之集極相連,該第三電晶體之射極接地,該第三電晶體之基極同場效電晶體之汲極相連,並透過第二電阻接收該待機電壓訊號,該場效電晶體之源極接地,該場效電晶體之閘極經第一電容接地,並透過第三電阻同該二極體之陰極相連,該二極體之陽極接收該主機板之系統電壓訊號,該第一控制電路輸出一第一控制訊號至輸入輸出控制器,該輸入輸出控制器在接收到低電平之第一控制訊號後控制電腦開機;及一第二控制電路,其包括一第一輸入端、一第二輸入端和一輸出端,該第一輸入端接收該待機電壓訊號,該第二輸入端接收該系統電壓訊號,該第二控制電路之輸出端同該場效電晶體之閘極相連,電腦在軟關機後該第二控制電路輸出一第二控制訊號至第一控制電路,使得第一控制電路在接收到低電平之脈波訊號後可再次開機。A motherboard testing device includes: a pulse signal generating circuit, comprising: an input end and an output end, the input end receiving a standby voltage signal, and generating a pulse signal at the output end; a first control circuit, The method includes a first transistor, a second transistor, a third transistor, a field transistor, a diode, a first resistor, a second resistor, a third resistor, and a first capacitor. a base of the first transistor is connected to an output end of the pulse signal generating circuit, a collector of the first transistor is connected to a base of the second transistor, and an emitter of the first transistor is grounded, the second The collector of the transistor is connected to an input/output controller on a computer motherboard, the emitter of the second transistor is connected to the collector of the third transistor, and the emitter of the third transistor is grounded, the third transistor The base is connected to the drain of the field effect transistor, and receives the standby voltage signal through the second resistor. The source of the field effect transistor is grounded, and the gate of the field effect transistor is grounded through the first capacitor and transmitted through The third resistor is connected to the cathode of the diode The anode of the diode receives the system voltage signal of the motherboard, and the first control circuit outputs a first control signal to the input/output controller, and the input/output controller controls the first control signal after receiving the low level. The computer is powered on; and a second control circuit includes a first input end, a second input end, and an output end, the first input end receives the standby voltage signal, and the second input end receives the system voltage signal, The output end of the second control circuit is connected to the gate of the field effect transistor, and after the soft shutdown, the second control circuit outputs a second control signal to the first control circuit, so that the first control circuit receives the low After the pulse signal of the level, it can be turned on again.

相較習知技術,該主機板測試裝置可不需測試人員手動操作待測電腦主機板上電和關機,透過脈波訊號控制該第一控制電路輸出給輸入輸出控制器之高低電平訊號可對主機板進行自動迴圈開關機測試,其電路簡單、成本較低、易於實現。Compared with the prior art, the motherboard testing device can manually control the power on and off of the computer to be tested without the test personnel, and control the high and low level signals output by the first control circuit to the input and output controller through the pulse signal. The motherboard performs automatic loop switch test, which is simple in circuit, low in cost and easy to implement.

請參照圖1,本發明主機板測試裝置之較佳實施方式包括一脈波訊號發生電路10、一第一控制電路20和一第二控制電路30。Referring to FIG. 1, a preferred embodiment of the motherboard testing apparatus of the present invention includes a pulse signal generating circuit 10, a first control circuit 20, and a second control circuit 30.

該脈波訊號發生電路10包括一555計時器U1、兩電阻R6、R7,以及兩電容C3、C4,該555計時器U1包括一電源端11、一低觸發端12、一清零端13、一控制端14、一高觸發端15、一放電端16、一輸出端17和一接地端18。該電源端11同清零端13相連後連接一待測電腦主機板之5V_STBY電壓,該低觸發端12和高觸發端15相連後經該電容C3接地,並透過該電阻R6和R7連接該5V_STBY電壓,該放電端16同該電阻R6和R7之間之連接節點相連,該控制端14透過該電容C4接地。The pulse signal generating circuit 10 includes a 555 timer U1, two resistors R6 and R7, and two capacitors C3 and C4. The 555 timer U1 includes a power terminal 11, a low trigger terminal 12, and a clear terminal 13. A control terminal 14, a high trigger terminal 15, a discharge terminal 16, an output terminal 17, and a ground terminal 18. The power terminal 11 is connected to the clear terminal 13 and connected to a 5V_STBY voltage of a computer motherboard to be tested. The low trigger terminal 12 is connected to the high trigger terminal 15 and grounded via the capacitor C3, and connected to the 5V_STBY through the resistors R6 and R7. The voltage is connected to the connection node between the resistors R6 and R7, and the control terminal 14 is grounded through the capacitor C4.

該第一控制電路20包括三個電晶體T1、T2、T3,一場效電晶體Q1、一二極體D1、五電阻R1、R2、R3、R4、R5和兩電容C1、C2。該電晶體T1之基極透過電阻R4同555計時器U1之輸出端17相連,該電晶體T1之集極同電晶體T2之基極相連,該電晶體T1之射極接地。該電晶體T2之集極連接一電腦主機板上之輸入輸出控制器,該電晶體T2之集極經電容C2接地,並透過電阻R5連接該5V_STBY電壓,該電晶體T2之射極同電晶體T3之集極相連。該電晶體T3之射極接地,該電晶體T3之基極同場效電晶體Q1之汲極相連,並透過第二電阻R2連接該5V_STBY電壓。該場效電晶體Q1之源極接地,該場效電晶體Q1之閘極經電容C1接地,並透過電阻R3同該二極體D1之陰極相連,該二極體D1之陽極連接該主機板之5V_SYS電壓。The first control circuit 20 includes three transistors T1, T2, T3, a field effect transistor Q1, a diode D1, five resistors R1, R2, R3, R4, R5 and two capacitors C1, C2. The base of the transistor T1 is connected to the output terminal 17 of the 555 timer U1 through a resistor R4. The collector of the transistor T1 is connected to the base of the transistor T2, and the emitter of the transistor T1 is grounded. The collector of the transistor T2 is connected to an input/output controller on a computer motherboard. The collector of the transistor T2 is grounded via a capacitor C2, and is connected to the 5V_STBY voltage through a resistor R5. The emitter of the transistor T2 is the same as the transistor. The collectors of T3 are connected. The emitter of the transistor T3 is grounded, and the base of the transistor T3 is connected to the drain of the field effect transistor Q1, and is connected to the 5V_STBY voltage through the second resistor R2. The source of the field effect transistor Q1 is grounded. The gate of the field effect transistor Q1 is grounded via a capacitor C1 and connected to the cathode of the diode D1 through a resistor R3. The anode of the diode D1 is connected to the motherboard. 5V_SYS voltage.

該第二控制電路30包括一比較器U2、一電晶體T4和四電阻R8、R9、R10、R11,該比較器U2之同相輸入端經電阻R8連接該5V_STBY電壓,並透過電阻R9接地,該比較器U2之反相輸入端連接該5V_SYS電壓,該比較器U2之輸出端透過電阻R10連接該電晶體T4之基極,該電晶體T4之集極透過電阻R11連接該場效電晶體Q1之閘極,該電晶體T4之射極接地。其中電晶體T1、T2、T3,T4均為NPN型電晶體,場效電晶體Q1為N溝道MOS型場效電晶體。The second control circuit 30 includes a comparator U2, a transistor T4, and four resistors R8, R9, R10, and R11. The non-inverting input terminal of the comparator U2 is connected to the 5V_STBY voltage via a resistor R8, and is grounded through a resistor R9. The inverting input terminal of the comparator U2 is connected to the 5V_SYS voltage, and the output terminal of the comparator U2 is connected to the base of the transistor T4 through a resistor R10. The collector of the transistor T4 is connected to the field effect transistor Q1 through a resistor R11. The gate of the transistor T4 is grounded. Among them, the transistors T1, T2, T3, and T4 are all NPN type transistors, and the field effect transistor Q1 is an N-channel MOS type field effect transistor.

使用本發明主機板測試裝置對待測電腦主機板進行測試時,先將主機板之電源供應器接入市電並閉合其開關,待測主機板即輸出該5V_STBY電壓。該5V_STBY電壓透過電阻R6和電阻R7給該電容C3充電,在電容C3上之電壓充至5V_STBY電壓之三分之二前,該555計時器U1之輸出端17一直輸出高電平訊號。當電容C3上之電壓充至5V_STBY電壓之三分之二時,該電容C3透過電阻R7向該555計時器U1之放電端16放電,此時該555計時器U1之輸出端17輸出低電平。該電容C3不斷之充放電在該555計時器U1之輸出端17產生脈波訊號。當該555計時器U1之輸出端17輸出低電平時,此時由於5V_SYS電壓還未輸出,場效電晶體Q1之閘極為低電平而截止,電晶體T3之基極為高電平而導通,而電晶體T1之基極為低電平截止,使得電晶體T2之基極為高電平而導通,該電晶體T2之集極為低電平,此時相當於測試人員手動按下了電源按鍵。該輸入輸出控制器接收到低電平訊號時輸出各組系統電壓使得待測主機板上電,5V_SYS電壓透過二極體D1和電阻R3給該電容C1充電,在電容C1上之電壓充至場效電晶體Q1之導通電壓後,場效電晶體Q1導通,使得該電晶體T3之基極為低電平而截止,該電晶體T2也截止,此時相當於測試人員又放開了電源按鍵,由此完成了電腦自動開機。When testing the computer motherboard to be tested by using the motherboard test device of the present invention, first connect the power supply of the motherboard to the mains and close its switch, and the motherboard to be tested outputs the 5V_STBY voltage. The 5V_STBY voltage charges the capacitor C3 through the resistor R6 and the resistor R7. Before the voltage on the capacitor C3 is charged to two-thirds of the 5V_STBY voltage, the output terminal 17 of the 555 timer U1 always outputs a high level signal. When the voltage on the capacitor C3 is charged to two-thirds of the 5V_STBY voltage, the capacitor C3 is discharged through the resistor R7 to the discharge terminal 16 of the 555 timer U1, and the output terminal 17 of the 555 timer U1 outputs a low level. . The capacitor C3 is continuously charged and discharged to generate a pulse wave signal at the output end 17 of the 555 timer U1. When the output terminal 17 of the 555 timer U1 outputs a low level, at this time, since the 5V_SYS voltage has not been output, the gate of the field effect transistor Q1 is turned off at a low level, and the base of the transistor T3 is extremely high and turned on. The base of the transistor T1 is extremely low-cut, so that the base of the transistor T2 is extremely high and turned on, and the set of the transistor T2 is extremely low, which is equivalent to the tester manually pressing the power button. When the input/output controller receives the low level signal, the system voltages of each group are output so that the main body of the test board is powered, and the 5V_SYS voltage is charged to the capacitor C1 through the diode D1 and the resistor R3, and the voltage on the capacitor C1 is charged to the field. After the on-voltage of the transistor Q1 is turned on, the field effect transistor Q1 is turned on, so that the base of the transistor T3 is turned off at a low level, and the transistor T2 is also turned off. At this time, the tester has released the power button. This completes the automatic booting of the computer.

在電腦開機達到一預設時間後該輸入輸出控制器發出關機訊號使電腦軟關機,此時5V_SYS電壓關閉,但5V_STBY電壓仍然輸出。該比較器U2之輸出端輸出高電平使得該電晶體T4導通,該電容C1透過電阻R11放電。當電容C1上之電壓放至場效電晶體Q1之截止電壓時,場效電晶體Q1再次截止,電晶體T3再次導通,當該555計時器U1之輸出端17再次輸出低電平時該電晶體T2也可再次導通,電腦也可再次開機。由此透過該555計時器U1之輸出端17不斷輸出之高低電平脈波訊號實現了對待測主機板之迴圈開關機測試。After the computer is turned on for a preset time, the input/output controller sends a shutdown signal to make the computer softly shut down. At this time, the 5V_SYS voltage is turned off, but the 5V_STBY voltage is still output. The output terminal of the comparator U2 outputs a high level such that the transistor T4 is turned on, and the capacitor C1 is discharged through the resistor R11. When the voltage on the capacitor C1 is placed to the cutoff voltage of the field effect transistor Q1, the field effect transistor Q1 is turned off again, and the transistor T3 is turned on again. When the output terminal 17 of the 555 timer U1 outputs a low level again, the transistor T2 can also be turned on again, and the computer can be turned on again. Therefore, the high-low pulse signal continuously outputted by the output terminal 17 of the 555 timer U1 realizes the loop switch test of the motherboard to be tested.

該主機板測試裝置可自動對電腦主機板進行迴圈開關機測試,具有結構簡單、實用性強、成本較低等優點。The motherboard test device can automatically perform loopback switch test on the computer motherboard, and has the advantages of simple structure, strong practicability and low cost.

綜上所述,本發明符合發明專利要件,爰依法提出專利申請。惟,以上所述者僅為本發明之具體實施方式,舉凡熟悉本案技藝之人士,在爰依本發明精神所作之等效修飾或變化,皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above-mentioned embodiments are only the specific embodiments of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

脈波訊號發生電路...10Pulse signal generation circuit. . . 10

第一控制電路...20First control circuit. . . 20

第二控制電路...30Second control circuit. . . 30

555計時器...U1555 timer. . . U1

比較器...U2Comparators. . . U2

電晶體...T1~T4Crystal. . . T1~T4

場效電晶體...Q1Field effect transistor. . . Q1

二極體...D1Diode. . . D1

電阻...R1~R11resistance. . . R1~R11

電容...C1~C4capacitance. . . C1~C4

圖1係本發明主機板測試裝置之較佳實施方式之電路圖。1 is a circuit diagram of a preferred embodiment of a motherboard test apparatus of the present invention.

脈波訊號發生電路...10Pulse signal generation circuit. . . 10

第一控制電路...20First control circuit. . . 20

第二控制電路...30Second control circuit. . . 30

555計時器...U1555 timer. . . U1

比較器...U2Comparators. . . U2

電晶體...T1~T4Crystal. . . T1~T4

場效電晶體...Q1Field effect transistor. . . Q1

二極體...D1Diode. . . D1

電阻...R1~R11resistance. . . R1~R11

電容...C1~C4capacitance. . . C1~C4

Claims (7)

一種主機板測試裝置,包括:一脈波訊號發生電路,其包括一輸入端和一輸出端,該輸入端接收一待機電壓訊號,並在輸出端產生一脈波訊號;一第一控制電路,其包括一第一電晶體、一第二電晶體、一第三電晶體、一場效電晶體、一二極體、一第一電阻、一第二電阻、一第三電阻和一第一電容,該第一電晶體之基極同脈波訊號發生電路之輸出端相連,該第一電晶體的集極同第二電晶體的基極相連,該第一電晶體之射極接地,該第二電晶體之集極連接一電腦主機板上之輸入輸出控制器,該第二電晶體之射極同第三電晶體的集極相連,該第三電晶體之射極接地,該第三電晶體之基極同場效電晶體之汲極相連,並透過第二電阻接收該待機電壓訊號,該場效電晶體之源極接地,該場效電晶體之閘極經第一電容接地,並透過第三電阻同該二極體的陰極相連,該二極體之陽極接收該主機板之系統電壓訊號,該第一控制電路輸出一第一控制訊號至輸入輸出控制器,該輸入輸出控制器在接收到低電平之第一控制訊號後控制電腦開機;及一第二控制電路,其包括一第一輸入端、一第二輸入端和一輸出端,該第一輸入端接收該待機電壓訊號,該第二輸入端接收該系統電壓訊號,該第二控制電路之輸出端同該場效電晶體之閘極相連,電腦在軟關機後該第二控制電路輸出一第二控制訊號至第一控制電路,使得第一控制電路在接收到低電平之脈波訊號後可再次開機。A motherboard testing device includes: a pulse signal generating circuit, comprising: an input end and an output end, the input end receiving a standby voltage signal, and generating a pulse signal at the output end; a first control circuit, The method includes a first transistor, a second transistor, a third transistor, a field transistor, a diode, a first resistor, a second resistor, a third resistor, and a first capacitor. a base of the first transistor is connected to an output end of the pulse signal generating circuit, a collector of the first transistor is connected to a base of the second transistor, and an emitter of the first transistor is grounded, the second The collector of the transistor is connected to an input/output controller on a computer motherboard, the emitter of the second transistor is connected to the collector of the third transistor, and the emitter of the third transistor is grounded, the third transistor The base is connected to the drain of the field effect transistor, and receives the standby voltage signal through the second resistor. The source of the field effect transistor is grounded, and the gate of the field effect transistor is grounded through the first capacitor and transmitted through The third resistor is connected to the cathode of the diode The anode of the diode receives the system voltage signal of the motherboard, and the first control circuit outputs a first control signal to the input/output controller, and the input/output controller controls the first control signal after receiving the low level. The computer is powered on; and a second control circuit includes a first input end, a second input end, and an output end, the first input end receives the standby voltage signal, and the second input end receives the system voltage signal, The output end of the second control circuit is connected to the gate of the field effect transistor, and after the soft shutdown, the second control circuit outputs a second control signal to the first control circuit, so that the first control circuit receives the low After the pulse signal of the level, it can be turned on again. 如申請專利範圍第1項所述之主機板測試裝置,其中該第一控制電路還包括一第四電阻,該第四電阻連接於脈波訊號發生電路之輸出端和第一電晶體之基極之間。The motherboard test apparatus of claim 1, wherein the first control circuit further includes a fourth resistor connected to the output end of the pulse signal generating circuit and the base of the first transistor. between. 如申請專利範圍第1項所述之主機板測試裝置,其中該第一控制電路還包括一第五電阻和一第二電容,該第二電晶體之集極經第五電阻接收該待機電壓訊號,並透過第二電容接地。The motherboard test apparatus of claim 1, wherein the first control circuit further includes a fifth resistor and a second capacitor, and the collector of the second transistor receives the standby voltage signal via the fifth resistor. And grounded through the second capacitor. 如申請專利範圍第1項所述之主機板測試裝置,其中該脈波訊號發生電路包括一555計時器、一第六電阻、一第七電阻、一第三電容和一第四電容,該555計時器包括一電源端、一低觸發端、一清零端、一控制端、一高觸發端、一放電端和一輸出端,該電源端作為脈波訊號發生電路之輸入端同清零端相連,該低觸發端和高觸發端相連後經第三電容接地,並透過第六電阻和第七電阻接收該待機電壓訊號,該放電端同第六電阻和第七電阻之間之連接節點相連,該控制端透過第四電容接地,該555計時器之輸出端作為該脈波訊號發生電路之輸出端。The motherboard testing device of claim 1, wherein the pulse signal generating circuit comprises a 555 timer, a sixth resistor, a seventh resistor, a third capacitor and a fourth capacitor, the 555 The timer includes a power terminal, a low trigger terminal, a clear terminal, a control terminal, a high trigger terminal, a discharge terminal and an output terminal, and the power terminal serves as an input end of the pulse signal generating circuit and a clear terminal. Connected, the low trigger end is connected to the high trigger end, grounded through the third capacitor, and receives the standby voltage signal through the sixth resistor and the seventh resistor, and the discharge end is connected to the connection node between the sixth resistor and the seventh resistor The control terminal is grounded through the fourth capacitor, and the output end of the 555 timer serves as an output end of the pulse signal generating circuit. 如申請專利範圍第4項所述之主機板測試裝置,其中該第二控制電路包括一比較器、一第四電晶體、一第八電阻、一第九電阻、一第十電阻和一第十一電阻,該比較器之同相輸入端作為第二控制電路之第一輸入端經第八電阻接收該待機電壓訊號,並透過第九電阻接地,該比較器之反相輸入端作為第二控制電路之第二輸入端,該比較器之輸出端透過第十電阻連接該第四電晶體之基極,該第四電晶體之集極作為第二控制電路之輸出端透過第十一電阻連接該場效電晶體之閘極,該第四電晶體之射極接地。The motherboard testing device of claim 4, wherein the second control circuit comprises a comparator, a fourth transistor, an eighth resistor, a ninth resistor, a tenth resistor, and a tenth a resistor, the non-inverting input of the comparator as the first input end of the second control circuit receives the standby voltage signal via the eighth resistor, and is grounded through the ninth resistor, and the inverting input of the comparator serves as the second control circuit a second input end, the output end of the comparator is connected to the base of the fourth transistor through a tenth resistor, and the collector of the fourth transistor is connected to the field through the eleventh resistor as an output end of the second control circuit The gate of the transistor, the emitter of the fourth transistor is grounded. 如申請專利範圍第5項所述之主機板測試裝置,其中該第一、第二、第三、第四電晶體均為NPN型電晶體。The motherboard test apparatus of claim 5, wherein the first, second, third, and fourth transistors are all NPN type transistors. 如申請專利範圍第1項所述之主機板測試裝置,其中該場效電晶體為N溝道MOS型場效電晶體。The motherboard test apparatus of claim 1, wherein the field effect transistor is an N-channel MOS type field effect transistor.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200724936A (en) * 2005-12-16 2007-07-01 Hon Hai Prec Ind Co Ltd System and method for testing power on-off of a computer's motherboard
TW200727549A (en) * 2006-01-10 2007-07-16 Giga Byte Tech Co Ltd Testing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200724936A (en) * 2005-12-16 2007-07-01 Hon Hai Prec Ind Co Ltd System and method for testing power on-off of a computer's motherboard
TW200727549A (en) * 2006-01-10 2007-07-16 Giga Byte Tech Co Ltd Testing system

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