CN210983376U - Testing device and related reset circuit - Google Patents

Abstract

The test device comprises a test fixture, a test machine table and a reset circuit, wherein the reset circuit generates a reset pulse to the test fixture when the test machine table is changed from a power-on state to a power-off state, so that the test fixture is powered on and restarted; the upper pole plate of the capacitor is connected to the ground to be low level when the second transistor is conducted, and an intermediate node connected to the first resistor and the second resistor is charged when the first transistor is conducted, so that a reset pulse signal is generated at the intermediate node. The utility model discloses produce reset pulse to tool by reset circuit when the board outage, make the tool end can realize going up the electricity without the outage and restart, multiplicable tool stability, reduction board card machine condition, improvement production efficiency.

Description

Testing device and related reset circuit

Technical Field

The utility model relates to an electronic equipment technical field, in particular to testing arrangement and relevant reset circuit.

Background

Along with the increase of the demand of the test fixture in the factory, the requirements of the stability and the reliability of the test fixture are higher and higher, the hardware design needs to meet the specification, and the software design needs to meet the production requirement. In general, in factory operation, a tester is used to operate and control a test fixture to realize automatic control, such as a chord lighting tester. However, the amount of the product is large, so that the test fixture is in a working state for a long time, and the situation that the program runs away cannot be avoided, and this can lead to the situation that the test machine reports errors or is jammed, and the operator needs to power off and restart. If the times are too many, the endurance of personnel is influenced, and the production efficiency is also influenced.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, an object of the present invention is to provide a testing apparatus and a related reset circuit.

According to the utility model discloses an aspect provides a testing device, including the test board and with the test fixture that the test board supplied power respectively to the test module that awaits measuring, the test board regards as with power supply enable signal test fixture's drive signal, its characterized in that, testing device still includes:

the reset circuit is connected with the test machine and the test fixture, acquires the power supply enabling signal from the test machine, and generates a reset signal to the test fixture according to the power supply enabling signal when the test machine is powered off, so that the test fixture is reset.

Preferably, the reset circuit includes:

the first resistor and the second resistor are sequentially connected between a voltage source and the ground in series, and the middle node of the first resistor and the second resistor is a reset pin for outputting the reset signal;

and the control module adjusts the voltage of the reset pin according to the power supply enabling signal to generate the reset signal.

Preferably, the control module comprises:

a first transistor and a capacitor which are sequentially connected in series between the reset pin and the ground, wherein the grid electrode of the first transistor receives the power supply enabling signal;

a second transistor connected between an intermediate node of the first transistor and the capacitor and ground, a gate of the second transistor receiving the power supply enable signal; wherein the content of the first and second substances,

the first transistor and the second transistor are turned on in a time-sharing manner according to the power supply enabling signal.

Preferably, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

Preferably, the power supply enable signal is at a low level when the test machine is in a power-on state, and is at a high level when the test machine is in a power-off state.

Preferably, the control module further comprises:

a third resistor through which gates of the first and second transistors are connected to ground.

Preferably, the resistance value of the second resistor is larger than the resistance value of the first resistor.

According to another aspect of the present invention, there is provided a reset circuit, including:

the circuit comprises a first resistor and a second resistor which are sequentially connected in series between a voltage source and the ground, wherein a middle node of the first resistor and the second resistor is a reset signal output pin;

a first transistor and a capacitor connected in series between the output pin and ground in sequence;

a second transistor connected between an intermediate node of the first transistor and the capacitor and ground; wherein the content of the first and second substances,

the grid electrodes of the first transistor and the second transistor receive control signals, and the first transistor and the second transistor are conducted in a time-sharing mode according to the control signals.

Preferably, the method further comprises the following steps:

a third resistor through which gates of the first and second transistors are connected to ground, the control signal being directly connected to the gates of the first and second transistors.

Preferably, the resistance value of the second resistor is larger than the resistance value of the first resistor.

The utility model provides a testing arrangement controls the charge and discharge of reset circuit's electric capacity through the power supply enable signal of test board to realize pin output reset pulse resets. The test fixture after reset by the external reset operation is switched to a power-off state every time, and the fixture end can realize power-on restart without power-off.

The utility model discloses not only increase test fixture's stability, reduced the test board simultaneously and appeared the condition of card machine, improved the production efficiency of mill.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic block diagram of a testing apparatus according to an embodiment of the present invention.

Fig. 2 shows a schematic structural diagram of a reset circuit provided in accordance with an embodiment of the present invention.

Fig. 3 shows a timing diagram of a test machine status signal and a reset pulse signal of the test apparatus according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

Referring to fig. 1 and 3, the embodiment of the utility model provides an include the test board, with test board is the test fixture and the reset circuit of power supply respectively, the test board produces power supply enable signal CONTRO L _ EN give the test board is as drive signal, reset circuit basis power supply enable signal produces reset signal RST output and gives the test fixture, power supply enable signal is in the test board is the low level when going up the electric state the test board is the high level when being the outage state.

In this embodiment, when the test apparatus performs power-off control on the module once, the test machine is changed from a power-on state to a power-off state, and at this time, the reset circuit generates a reset pulse to the test fixture according to the corresponding power supply enable signal, so as to restart the test fixture after power is supplied.

Referring to fig. 2, the reset circuit according to an embodiment of the present invention includes a first resistor R1 and a second resistor R2 sequentially connected in series between a voltage source and ground, an NMOS transistor M1 and a capacitor C1 sequentially connected in series between an intermediate node of the first resistor R1 and the second resistor R2, a PMOS transistor M2 connected between an intermediate node of the NMOS transistor M1 and the capacitor C1 and ground, and a third resistor R3 connected between a gate of the NMOS transistor M1 and the PMOS transistor M2 and ground, a power supply enable signal CONTRO L _ EN directly connected to the gate of the NMOS transistor M1 and the gate of the PMOS transistor M2, the intermediate node of the first resistor R1 and the second resistor R2 serving as a reset pin to output a reset signal to a fixture terminal, and the second resistor R2 being greater than the first resistor R1, so as to ensure that the reset pin outputs a high level at a lower voltage source, wherein the fixture terminal is a fixture receiving the reset signal.

Referring to fig. 3, at time t1, the test fixture starts to be powered on, at this time, the test machine is in a power-off state, the power supply enable signal CONTRO L _ EN is in a high level, the NMOS tube M1 is turned on, the PMOS tube M2 is turned off, the capacitor C1 is charged, and the reset pin outputs a high level, at time t2, the test machine becomes in a power-on state, the power supply enable signal CONTRO L _ EN is in a low level, the NMOS tube M1 is turned off, the PMOS tube M2 is turned on, the capacitor C1 is discharged, so that the upper plate voltage of the capacitor C1 is in a low level, and the reset pin voltage outputs a high level, at time t3, the test machine becomes in a power-off state, the power supply enable signal CONTRO L _ EN is in a high level, the NMOS tube M1 is turned on, the PMOS tube M2 is turned off, at this time, the upper potential of the capacitor C1 is in a low level, and is connected to the reset pin, so that the reset signal potential is changed from a high level at the instant, and the reset time t1 is the reset time.

In the embodiment of the present invention, when the testing device stops working, the reset circuit makes the NMOS transistor M1 and the PMOS transistor M2 empty through the third resistor R3 to protect the circuit.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. The utility model provides a testing arrangement, including test board and with the test fixture that test board supplied power respectively to the test module that awaits measuring, the test board regards as with power supply enable signal test fixture's drive signal, its characterized in that, testing arrangement still includes:

the reset circuit is connected with the test machine and the test fixture, acquires the power supply enabling signal from the test machine, and generates a reset signal to the test fixture according to the power supply enabling signal when the test machine is powered off, so that the test fixture is reset.

2. The test device of claim 1, wherein the reset circuit comprises:

the first resistor and the second resistor are sequentially connected between a voltage source and the ground in series, and the middle node of the first resistor and the second resistor is a reset pin for outputting the reset signal;

and the control module adjusts the voltage of the reset pin according to the power supply enabling signal to generate the reset signal.

3. The testing device of claim 2, wherein the control module comprises:

a first transistor and a capacitor which are sequentially connected in series between the reset pin and the ground, wherein the grid electrode of the first transistor receives the power supply enabling signal;

a second transistor connected between an intermediate node of the first transistor and the capacitor and ground, a gate of the second transistor receiving the power supply enable signal; wherein the content of the first and second substances,

the first transistor and the second transistor are turned on in a time-sharing manner according to the power supply enabling signal.

4. The test device of claim 3,

the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

5. The test device of claim 4,

the power supply enabling signal is at a low level when the test machine is in a power-on state, and is at a high level when the test machine is in a power-off state.

6. The testing device of claim 3, wherein the control module further comprises:

a third resistor through which gates of the first and second transistors are connected to ground.

7. The test device of claim 2,

the resistance value of the second resistor is larger than that of the first resistor.

8. A reset circuit, comprising:

the circuit comprises a first resistor and a second resistor which are sequentially connected in series between a voltage source and the ground, wherein a middle node of the first resistor and the second resistor is a reset signal output pin;

a first transistor and a capacitor connected in series between the output pin and ground in sequence;

a second transistor connected between an intermediate node of the first transistor and the capacitor and ground; wherein the content of the first and second substances,

the grid electrodes of the first transistor and the second transistor receive control signals, and the first transistor and the second transistor are conducted in a time-sharing mode according to the control signals.

9. The reset circuit of claim 8, further comprising:

a third resistor through which gates of the first and second transistors are connected to ground, the control signal being directly connected to the gates of the first and second transistors.

10. The reset circuit of claim 8,

the resistance value of the second resistor is larger than that of the first resistor.

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