TWI381486B - Method for manufacturing semiconductors (1) - Google Patents

Description

Semiconductor manufacturing method (1)

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor manufacturing method, and more particularly to a semiconductor manufacturing method capable of reducing the number of lithography processes required in a manufacturing process in a process of a complementary metal oxide semiconductor (CMOS) of 0.5 mm or less (including 0.5 mm).

The Complementary Metal Oxide Semiconductor (CMOS) process is the most important semiconductor integrated circuit technology, and it has the advantages of low power consumption, so it is widely used in a variety of products such as memory and logic.

N-type microdoped germanium of N-type gold oxide semiconductor (NMOS) included in the fabrication of complementary metal oxide semiconductors is generally fabricated in a 0.5 mm or less (including 0.5 mm) complementary metal oxide semiconductor (CMOS) process. In the process of pole and source and N-type heavily doped drain and source, each step of at least one lithography procedure is required to complete the N-type gold-doped semiconductor (NMOS) N-type micro-doped bungee And the fabrication of source and N-type heavily doped drains and sources to continue the subsequent process, so N-type MOS semiconductors (NMOS) are conventionally fabricated with complementary MOS devices below 0.5 mm (including 0.5 mm). The N-type micro-doped drain and source and N-type heavily doped drain and source processes require a total of at least two lithography procedures to complete the complementary MOS N The fabrication of N-type microdoped drain and source of N-type gold oxide semiconductor (NNOS) and N-type heavily doped drain and source. Among them, the lithography program is sequentially: upper photoresist, photoresist exposure, development, and photoresist removal. Since this technology is well known to engineers familiar with complementary MOS processes, This will not be repeated here. However, in the process of complementary MOS, the process of the lithography process is quite complicated. If a lithography process is to be performed, it takes a considerable amount of time, and the cost is also complementary. The most expensive semiconductor process. Therefore, how to reduce the number of lithography processes required in the fabrication of complementary MOS processes to effectively improve the production efficiency of complementary MOS semiconductors has become an extremely important development issue in the development of complementary MOSs. .

In view of the above-mentioned lack of prior art, how to provide a semiconductor manufacturing method capable of improving production efficiency and effectively reducing cost has become an important issue in the development of semiconductor technology.

SUMMARY OF THE INVENTION The object of the present invention is to provide a method for manufacturing a semiconductor of 0.5 mm or less (including 0.5 mm), which can effectively reduce the number of times of lithography processes to be performed, greatly improve the efficiency of semiconductor production, and also reduce the cost of semiconductor production.

The invention provides a method for manufacturing a semiconductor of 0.5 mm or less (including 0.5 mm), the semiconductor comprising a first well region bottom, a second well region, an oxide layer, a first gate electrode, a second gate electrode, a first drain electrode and a first source region, wherein the second well region is formed on one side of the second (P) well region, and the first gate electrode system is formed on the second well region The oxide layer is formed on the second (P) well region and adjacent to the first well region, the second gate electrode is formed on the first well region and its position is associated with the first gate The electrodes are opposite to each other, and the first drain and the first source are Formed by an ion micro-doping process and an ion heavy doping process, the semiconductor manufacturing method is characterized in that the ion micro-doping process and the ion heavy doping process method only need one of the two to perform a micro Shadow program. Wherein, the lithography program comprises the following steps: upper photoresist, photoresist exposure, development, and photoresist removal.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Referring to FIG. 1 and FIG. 2, FIG. 1 is a schematic view showing an embodiment of a semiconductor according to a method of fabricating a semiconductor of the present invention. Fig. 2 is a view showing another embodiment of a semiconductor according to the method of fabricating a semiconductor of the present invention. As shown in FIG. 1 and FIG. 2, the present invention is a method for fabricating a semiconductor, which is suitable for use in a case where a semiconductor (50, 70) is less than or equal to 0.5 mm, and a semiconductor (50, 70) Less than or equal to 0.5 mm means that the method of the present invention is applicable to 0.5 mm or 0.45 mm or 0.4 mm or 0.35 mm, etc. Generally, the semiconductor (50, 70) is less than or equal to 0.5 mm is an expression process. More and more advanced meaning.

The semiconductor (50, 70) is a complementary metal oxide semiconductor (CMOS). The semiconductor (50, 70) includes a second well region 52, a first well region 54, an oxide layer 60, a first gate electrode 58, a second gate electrode 56, a first drain 62, and a first Source 64. In a specific embodiment, the method of fabricating the semiconductor of the present invention is applicable to a condition in which the semiconductor (60, 70) is less than or equal to 0.5 mm. The second well area (52) is a P well area, the first well area (54) It is an N Well (N Well) formed by implanting an N-type ion. The second well region (52) is formed on one side of the first well region (54), and the second gate electrode (56) is formed on the first well region (54), and the oxide layer (60) is formed. Above the second well region (52) and adjacent to the first well region (54), the oxide layer (52) is formed of hafnium oxide (SiO2). The second gate electrode (56) is formed on the first well region (54) and is located opposite to the first gate electrode (58). The first drain electrode (62) and the first source electrode (64) are borrowed. Formed by an ion micro-doping process and an ion heavy doping process. In this embodiment, the first drain (62) and the first source (64) are formed by an N-type ion micro-doping program and an N-type ion heavy doping procedure. The first drain (62) is an N-type drain, and the first source (64) is an N-type source.

The semiconductor (50, 70) further includes an N-type metal oxide semiconductor (NMOS), as shown in FIG. 1, by the second well region 52, the first gate electrode 58, a first drain 62, and a first source. a pole 64, wherein the N-type micro-doped drain (62) and source (64) of the N-type MOS and the N-type heavily doped drain (62) and source (64) are implanted Enter the P well area (52).

In the present embodiment, the semiconductor (50) performs an N-type ion micro-doping process and an N-type ion heavy doping process to generate an N-type drain when the first gate electrode (58) has not formed a spacer. N-type source. There are two methods for the method. The first method is to perform only the N-type ion heavy doping procedure when the spacer is not formed, and the N-type ion micro-doping procedure is not performed. The second way is to simultaneously implant the N-type ion heavy doping program with an N-type ion microdoping procedure. Both of the above methods can produce N-type bungee And N-type source. However, it is important to note that the N-type ion micro-doping process and the original lithography process of the ion-doping process are combined into one lithography process. Wherein, the lithography program sequentially comprises the following steps: upper photoresist, photoresist exposure, development, and photoresist removal.

In the embodiment of FIG. 2, the semiconductor (70) further includes at least one spacer (66), and at least one spacer 66 is formed on both sides of the first gate electrode 58. This embodiment and FIG. 1 The difference of the embodiment is that the N-type N-type ion heavy doping procedure and the N-type ion micro-doping procedure are performed after forming the spacers (66) on both sides of the first gate electrode (58) in this embodiment. The above two doping procedures are the same as the embodiment of Fig. 1, and there are two ways. The first one is to perform only the N-type ion heavy doping procedure after forming the spacers (66), and the N-type ion micro-doping is not performed. Miscellaneous procedures. The second way is to implant an N-type ion heavily doping program with an N-type ion microdoping procedure after forming the spacers (66). Both of the above methods can generate N-type drains and N-type sources. However, it is important to note that the N-type ion micro-doping process and the original lithography process of the ion-doping process are combined into one lithography process.

Wherein, the lithography program sequentially comprises the following steps: upper photoresist, photoresist exposure, development, and photoresist removal.

The manufacturing method of the semiconductor of the present invention improves the conventional semiconductor manufacturing method, and reduces the number of times of performing the most costly lithography process in the semiconductor manufacturing process, compared with the conventionally manufactured gold of 0.5 mm or less (including 0.5 mm). N-type gold-doped semiconductor (NMOS) N-type micro-doped drain and source and N-type During the process of heavily doping the drain and the source, at least two steps of the lithography process are required, and the semiconductor manufacturing method of the present invention only needs to perform lithography to complete the fabrication of the semiconductor, and utilizes the present invention. The manufacturing method of the semiconductor can solve the shortcomings of the prior art, effectively improve the efficiency of semiconductor manufacturing and greatly reduce the manufacturing cost, and not only improve the competitiveness of the industry due to the improvement of production efficiency and the reduction of production cost, but also the simplification of the process. The reduction of waste generated by the manufacture of semiconductors effectively achieves the current trend of environmental protection and energy conservation.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

50, 70‧‧‧ semiconductor

52‧‧‧Second (P) well area

54‧‧‧First (N) Well Area

56‧‧‧second gate electrode

58‧‧‧First gate electrode

60‧‧‧Oxide layer

62‧‧‧First bungee

64‧‧‧first source

66‧‧‧ spacer

Fig. 1 is a schematic view showing an embodiment of a semiconductor according to a method of fabricating a semiconductor of the present invention.

Fig. 2 is a view showing another embodiment of a semiconductor according to the method of fabricating a semiconductor of the present invention.

70‧‧‧ Semiconductor

52‧‧‧Second (P) well area

54‧‧‧First (N) Well Area

56‧‧‧second gate electrode

58‧‧‧First gate electrode

60‧‧‧Oxide layer

62‧‧‧First bungee

64‧‧‧first source

66‧‧‧ spacer

Claims (14)

The present invention provides a method of fabricating a semiconductor including a first well region, a second well region, an oxide layer, a first gate electrode, a second gate electrode, a first drain, and a first source. a pole, wherein the second well is formed on one side of the first well region, and the first gate electrode is formed on the second well region, and the oxide layer is formed in the second well region Adjacent to and adjacent to the first well region, the first gate electrode is formed on the first well region and is located opposite to the first gate electrode, and the first drain and the first source are Formed by an ion micro-doping process and an ion heavy doping process, the semiconductor manufacturing method is characterized in that the ion micro-doping process and the ion heavy doping process only need to perform a lithography process. The method for producing a semiconductor according to claim 1, wherein the oxide layer is formed of cerium oxide (SiO2). The method for manufacturing a semiconductor according to claim 1, wherein the first well region is an N well region, and the second well region is a P well region, and the P well region is implanted by Formed by P-type ions, the N-well region is formed by implanting an N-type ion. The method of fabricating a semiconductor according to claim 3, wherein the first drain and the first source are formed by an N-type ion micro-doping and an N-type ion heavy doping. The method of manufacturing a semiconductor according to claim 4, wherein the semiconductor further comprises an N-type gold oxide semiconductor (NMOS), the N-type micro-doped drain and source of the N-type gold-oxide semiconductor, and N Type heavily doped drains and sources are implanted in the P well region. The method of manufacturing a semiconductor according to claim 5, wherein the semiconductor is a complementary metal oxide semiconductor (CMOS). The method of fabricating a semiconductor according to claim 5, wherein the semiconductor further comprises at least one spacer formed on both sides of the first and second gate electrodes. The method of fabricating a semiconductor according to claim 7, wherein the method is to implant only the N-type heavily doped source and the drain before the spacer is formed. The method of manufacturing a semiconductor according to claim 7, wherein the method is preceded by the formation of the N-type slightly doped drain and source and the N-type heavily doped drain and Source. The method of manufacturing a semiconductor according to claim 7, wherein the method is such that only the N-type heavily doped source and the drain are implanted after the spacer is formed. The method of manufacturing a semiconductor according to claim 7, wherein the method is after the spacer is formed, simultaneously implanting an N-type slightly doped drain and source and an N-type heavily doped drain and Source. The method of manufacturing a semiconductor according to claim 1, wherein the lithography process comprises the steps of: upper photoresist, photoresist exposure, development, and photoresist removal. The method of manufacturing a semiconductor according to claim 1, wherein the semiconductor system is less than or equal to 0.5 mm. The method of manufacturing a semiconductor according to claim 1, wherein the semiconductor system is less than or equal to 0.5 mm.