CN101442001B - Method for etching polysilicon gate - Google Patents
Method for etching polysilicon gate Download PDFInfo
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- CN101442001B CN101442001B CN2007101706159A CN200710170615A CN101442001B CN 101442001 B CN101442001 B CN 101442001B CN 2007101706159 A CN2007101706159 A CN 2007101706159A CN 200710170615 A CN200710170615 A CN 200710170615A CN 101442001 B CN101442001 B CN 101442001B
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- polysilicon
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Abstract
The invention provides a method for etching a polysilicon grid, which comprises the steps of deposing polysilicon, completing polysilicon photoetching, completing polysilicon etching, and cleaning polysilicon on the back of a wafer bottom layer which finishes the process of cleaning the polysilicon on the back of the wafer bottom layer. The method for etching the polysilicon grid increases the tensile stress of a wafer by cleaning off the polysilicon on the back of the wafer bottom layer, thereby effectively avoiding the forming of a grid foot, and improving wafer performance.
Description
Technical field
The invention belongs to the chip manufacturing field, relate to chip etching technology, relate in particular to a kind of method of etching polysilicon gate.
Background technology
Two kinds of basic etching technics are arranged: dry etching and wet etching in the semiconductor manufacturing.Dry etching is that silicon chip surface is exposed to the plasma that produces in the gaseous state, and the window of plasma by leaving in the photoresist in silicon chip generation physical reactions or chemical reaction (or two kinds of reactions), thereby removes the surfacing of exposure.Dry etching is the main method of etched features under the submicron-scale.
Dry etching divides according to material, mainly is divided into three kinds: metal etch, dielectric etch and silicon etching.Wherein, silicon etching is applied to need to remove the occasion of silicon, as etch polysilicon transistor gate and silicon groove electric capacity.
In MOS (metal-oxide semiconductor (MOS)) device, the LPCVD of doping (low-pressure chemical vapor phase deposition) polysilicon is the electric conducting material as grid.The doped polycrystalline silicon live width has determined that the grid of active device are long, and can influence transistorized performance.Fig. 2 shows the structure of wafer before the etching of existing polysilicon gate, comprises upper strata polysilicon layer 21 ', oxide layer 3 ', bottom 4 ', lower floor's polysilicon layer 22 ' and is positioned at photoresist layer 11 ', 12 ' above the upper strata polysilicon layer 21 '; Photoresist layer 11 ', 12 ' divides the both sides that are listed in upper strata polysilicon layer 21 '.
See also Fig. 1, the lithographic method of existing polysilicon gate mainly may further comprise the steps:
Steps A ': the step of polysilicon deposition; Finish the deposition process of polysilicon, make the two sides of polycrystalline silicon growth in oxide layer and bottom.
Step B ': the step of polysilicon photoetching; Finish the process of polysilicon photoetching.
Step C ': the step of etching polysilicon; Finish the process of etching polysilicon.
Yet the method for existing etching polysilicon has its weak point.Through after the existing lithographic method etching, the place that has a common boundary in the root and the oxide layer 3 ' of upper strata polysilicon layer 21 ' forms the grid foot.The generation of this grid foot can influence the effective dimensions of gate bottom, thereby reduces the speed of CMOS (complementary metal oxide semiconductors (CMOS)), and then influences the performance of wafer.One of reason that causes this result is that the tension stress of wafer is too small.Traditional engraving method is difficult to eliminate this grid foot.The change that studies show that wafer stress has the influence that worsens and improve to the grid foot.
Summary of the invention
The purpose of this invention is to provide and a kind ofly can increase the wafer tension stress, reduce the grid foot, improve the etching polysilicon gate method of wafer property.
To achieve these goals, the invention provides a kind of method of etching polysilicon gate, this method comprises the step of finishing polysilicon deposition, finish the step of polysilicon photoetching and finish the step of etching polysilicon; Described method comprises also and washes the step that the wafer bottom back side surpasses the polysilicon of half that this step is finished the process of clean wafers bottom back side polysilicon.
As a preferred embodiment of the present invention, the step of described clean wafers bottom back side polysilicon the step of polysilicon deposition, and the step of polysilicon photoetching between carry out.
As a preferred embodiment of the present invention, the step of described clean wafers bottom back side polysilicon washes the whole polysilicon in the wafer bottom back side.
Compared with prior art, the method of the etching polysilicon gate that the present invention discloses, between the deposition of polysilicon and photoetching, increase clean wafers bottom back side polysilicon step, increase the tension stress of wafer, thus can effectively avoid the grid foot formation, improve wafer property.
Description of drawings
Fig. 1 is the flow chart of etching polysilicon gate method in the prior art.
Fig. 2 is the structural representation of the preceding wafer of etching of polysilicon gate in the prior art.
Fig. 3 is the flow chart of etching polysilicon gate method of the present invention.
Fig. 4 is the structural representation of the preceding wafer of etching of polysilicon gate of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is done concrete introduction.
Embodiment one
See also Fig. 3, the present invention has introduced a kind of method of etching polysilicon gate, mainly may further comprise the steps:
Steps A: the step of polysilicon deposition; Finish the deposition process of polysilicon, make the two sides of polycrystalline silicon growth in oxide layer and bottom.
Step B: the step of clean wafers bottom back side polysilicon; This step is finished the process of clean wafers bottom back side polysilicon.In the present embodiment, this step washes the whole polysilicon layer in the wafer bottom back side.Chip architecture after the cleaning as shown in Figure 4.
Step C: the step of polysilicon photoetching; Finish the process of polysilicon photoetching.
Step D: the step of etching polysilicon; Finish the process of etching polysilicon.
The present invention passes through to increase clean wafers bottom back side polysilicon step between the deposition of polysilicon and photoetching, increase the tension stress of wafer, thereby can effectively avoid the formation of grid foot, the performance of raising entire wafer.
Embodiment two
The difference of present embodiment and embodiment one is, in the present embodiment, in the step of step B clean wafers bottom back side polysilicon, does not wash the whole polysilicon layer in the wafer bottom back side, surpasses the polysilicon of half and only wash the wafer bottom back side; As wash 3/4 polysilicon layer.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only.Any modification or partial replacement that does not break away from spirit and scope of the invention all should be encompassed in the middle of the claim scope of the present invention.
Claims (3)
1. the method for an etching polysilicon gate, this method comprise the step of finishing polysilicon deposition, finish the step of polysilicon photoetching and finish the step of etching polysilicon; It is characterized in that,
Described method comprises also and washes the step that the wafer bottom back side surpasses the polysilicon of half that this step is finished the process of clean wafers bottom back side polysilicon.
2. the method for claim 1 is characterized in that, the step of described clean wafers bottom back side polysilicon the step of polysilicon deposition, and the step of polysilicon photoetching between carry out.
3. the method for claim 1 is characterized in that, the step of described clean wafers bottom back side polysilicon washes the whole polysilicon in the wafer bottom back side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101706159A CN101442001B (en) | 2007-11-19 | 2007-11-19 | Method for etching polysilicon gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101706159A CN101442001B (en) | 2007-11-19 | 2007-11-19 | Method for etching polysilicon gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101442001A CN101442001A (en) | 2009-05-27 |
| CN101442001B true CN101442001B (en) | 2011-03-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101706159A Expired - Fee Related CN101442001B (en) | 2007-11-19 | 2007-11-19 | Method for etching polysilicon gate |
Country Status (1)
| Country | Link |
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| CN (1) | CN101442001B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615669A (en) * | 2016-12-12 | 2018-10-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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2007
- 2007-11-19 CN CN2007101706159A patent/CN101442001B/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN101442001A (en) | 2009-05-27 |
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Granted publication date: 20110323 Termination date: 20191119 |
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