六、發明說明： 【發明所屬之技術領域】 本發明涉及一種管線式（pipelined)類比至數位轉換器 (Analog-to-Digital Converter , ADC)，尤其涉及一種包含倍 增數位至類比轉換器（Multiplying Digital-to-Analog Converter， MDAC)的管線式類比至數位轉換器》 【先前技術】 類比至數位轉換過程將類比信號轉換為數位格式，其 中類比信號通常由電壓來表示。已知的類比至數位轉換方 法包括串列結構、三角積分(delta-sigma)結構、並列結構 以及管線式結構。不同的結構適用於不同的需求。 串列類比至數位結構提供在類比至數位轉換中廣泛 的性能範圍，為量化提供低電力消耗與低解析度。串列結 構通常以每周期1位元的速率對類比資料進行量化。因 此，具有N位元解析度的數位取樣需經過n個周期完成量 化。 三角積分類比至數位結構常用於音頻信號處理。這種 結構設計為用於將高速度而低解析度的取樣轉換為更高解 析度而更低速度的輸出。由於比實際輸出更多的類比資料 取樣被量化’所以此過程也被稱為超取樣(oversampling)。 相反，並列類比至數位結構提供最快的每類比信號量 化速率。對於並列（或「flash」）結構而言，為每一個類比 資料取樣產生每周期的數位數值’而無須考慮解析度的位 元數目N疋多少。並列結構要求所有量化位準需同時與類 0758-A33〇86TWF_MTKI-〇7-081 4 1376103 比信號比較。這導致需要使用2(N])個比較器以及2(N+1) ' 個電阻器以達到數位數值，其中每周期解析度為N位元。 - 若想達到更高的解析度，flash類比至位元轉換器的電路複 雜度會大大提高。 管線式類比至數位結構，相似於串列類比至數位結 構，是級内的類比信號量化方法。存在獲得每級1位元或 1.5位元解析度的算法。在1.5位元每級的轉換器中，每一 級的數位輸出Di為1、0或者-1。在1位元每級的轉換器 • 中，每一級的數位輸出Di為1或者-1(或1或0)。對於兩 者中的任一種算法，對N位元數位數值都要使用到N個 級。對下一個位元的解析，在每一級首先解析一個位元， 然後傳送馀下的類比信號取樣至下一級以解析另一位元。 【發明内容】 為了解決資料的類比至數位轉換過程中難以達到較 優化平衡的問題，本發明提供一種管線式類比至數位轉換 • 器。 根據本發明的實施例，提供一種管線式類比至數位轉 換器，包含：至少一個倍增數位至類比轉換器，包含：至 少一個第一電容器；至少一個第二電容器；一放大器，耦 接於該第一電容器與該第二電容器；複數個切換器，根據 一第一控制信號、一第二控制信號以及一數位信號’控制 該第一電容器與該第二電容器之間的連接，其中在一第一 時期，該第一電容器與該第二電夸器並列連接，而在一第 二時期，該第一電容器與該第二電容器串列連接，以及該 0758-AJ3086TWF_MTKI-07-081 5 1376103 些切換器當中的-第一切換器由一第一電晶體組成；以及 至少-個子類比至數位轉換器，用於根據該第—控制信號 與該第一控制信號提供一數位信號。 通過利用本發明的管線式類比至數位轉換器，可以較 低的電路複雜度對資料進行較高的解析度的轉換，同時電 力消耗可減少並且電路㈣鐘分布可得以顯著簡化。 【實施方式】 下述之貫施例僅用來例舉本發明之實施態樣，以及閣 釋本發明之技術特徵’並非絲限制本發明之料。本發 明之權利範圍應以申請專利範圍為準。 第1圖為根據本發明的管線式類比至數位轉換器的較 佳實施例簡略示意圖m式類比至數位轉換器(ADC)l〇〇 包含變換級ΤγΤη以及數位校正區塊11〇。變換級τ〗〜Tn將 包含差分k號Vip與Vin的類比信號分別變換為數位信號 D广Dn(請注意輸入信號Vin為正信號）。數位信號D〗〜队構 成類比信號的數位格式，其中Di代表最重要的位元，％ 代表最無足輕重的位元。於是數位校正區塊11〇對數位信 號進行時間校準(time_aligned)與數位校正，輸出校 正的數位信號D。由於變換級Tl〜Tn的操作都相似，所以 本說明書中僅給出級Τ!作為例子。 第2圖為根據本發明的變換級的較佳實施例簡略示意 圖。變換級包含倍增數位至類比轉換器（MDAC)21()與 子ADC 220〇MDAC210根據數位信號仏處理差分輸入信 號Vin與Vip以及控制信號ph 1與ph2。接著，MDAC 210 0758-A33086TWF_MTKI，〇7-〇81 6 ^/0103 發送處理結果至下一變換級T2<J子adc 220根據控制信號 PM與Ph2變換輸入信號Vin與Vip，於是產生數位信號 D! 〇 第3a圖為根據本發明的倍增數位至類比轉換器210 的較佳實％例的簡略示意圖e MDAc 210包含切換器311 〜316和321〜326、電容器331〜334以及放大器34卜因 為切換器311〜316與電容器33丨、332之間的連接關係相 似於切換器321〜326與電容器333、334之間的連接關係， 本說明書中僅給出切換器311〜316與電容器331、332之 間的連接關係作為例子。請注意儘管第圖的實施例中顯 不了 12個切換器與4個電容器以作例舉之用’切換器與電 容器的數量及排布並不限於此。事實上，切換器與電容器 的數量及排布可根據對管線式ADc 1〇〇的性能需求來進行 設計。 參照第3a圖’切換器311〜316根據控制信號Phi與 Ph2以及數位彳g號以控制電容器331與332之間的連接。 其中，切換器311〜316可分別稱為第一至第六切換器， Phi與Ph2可分別稱為第一控制信號與第二控制信號，電 容器331與332可分別稱為第一電容器與第二電容器。如 第3b圖所示，在本實施例中’控制信號phl與ph2兩者為 無重疊的時鐘信號。控制信號Phi與phl_互逆。控制信號 Ph2與Ph2一互逆。在一個實施例中變換級Τι產生一個位元 的輸出，數位信號Di為邏輯「0」或邏輯「1」。信號Ph2a 與Ph2b與數位信號D!有關。相似的，信號Ph2a與信號 Ph2a_互逆。信號Ph2b與信號Ph2b_互逆。 0758-A33086TWF_MTKJ-〇7-〇81 7 1376103 在第一時期，即當Phl信號為高電歷位準而Ph2信號 為低電壓位準時，根據信號Phl_、Ph2__、Ph2a一以及Ph2b， 切換器311、314與316開啟，而切換器312、313與315 關閉。因此’電容器331與332並列連接於輸入信號vip 與電壓Vcm之間，以對輸入信號vip進行取樣。在本實施 例中’切換器311與314分別由PMOS電晶體實作。所以， 電容器331僅通過一個電晶體接收輸入信號Vip。相似的， 電容器332僅通過一個電晶體接收輸入信號Vip。 在第二時期，即當phl信號為低電壓位準而Ph2信號 為高電壓位準時’切換器313與切換器312或315開啟， 而切換器311、314與316關閉，於是，電容器331與332 串列連接於參考信號Vrefp或Vrefn與放大器341的負輪 出終知之間。參考信號Vrefp與Vrefn可分別稱為第一參 考信號與第二參考信號。放大器341的負輸出終端輸出負 輸出信號von ’正輸出終端輸出正輸出信號vop。切換器 312與315分別由信號Ph2b與ph2a-控制。由於信號扑孔 與Ph2a-有關於數位信號Di，每個切換器312和315根據 數位信號D〗開啟或關閉。例如，假設切換器與開 啟而使得電容器331與332串列連接於參考信號Vrefp與 放大器341的負輸出終端之間，放大器341對參考信號 Vrefp與取樣結果之間差異進行放大，其中取樣結果存儲於 電容器331和332中。在本實施例中，電容器332僅利用 切換器312的電晶體或是僅利用切換器315的電晶體以接 收參考信號Vrefp或V.refn，其中切換器312的電晶體為 NMOS電晶體而切換器315的電晶體為pM〇s電晶體。參 〇758-A33086TWF_MTKI-07-081 〇 丄376103 考信號Vrefp與Vrefn具有不同的電壓位準。 另外，輸入至切換器311與316的控制信號並不限於 具有完全相同的波形。例如，切換器311可由控制信號phl 控制，而切換器316可由另一控制信號Phle—控制。第几 圖顯示控制信號Phi與Phle之間的關係。信號phle與信 號Phle一互逆。如圖所示，控制信號phl與phle的上升邊 緣同步，但控制信號Ph 1 e在控制信號p h 1之前下降。相似 的，輸入至切換器321與326的控制信號並不限於具有完 全相同的波形。切換器321可由控制信號phl_控制，而切 換盗326可由另一控制信號phle_控制。 切換器311〜316其中的一個由電晶體組成，如PM〇s 電晶體或NMOS電晶體。在本實施例中，切換器312與322 為N型電晶體而其它的切換器為！>型電晶體。在一個實施 例中（如第3c圖所示），切換器312與322為P型電晶體而 其它的切換器為N型電晶體。 參照第3a圖’當切換器311與314的電晶體為P型 時’配置電晶體的井(well)以接收電壓vipbulk，此内容將 在下面段落中進一步說明。切換器315的電晶體包含接收 電源信號vdd的井（電源信號vdd為第一電源信號）。切換 器312的電晶體包含接收接地信號gn(i的基底（接地信號 gnd為第二電源信號）。切換器313的電晶體包含接收電壓 vonbulk的井’此内容將在下面段落中進一步說明。切換器 316的電晶體包含接收電壓Vcm的井。電壓Vcm具有介於 參考、電壓位準Vrefp與Vrefn之間的電壓位準。在一聲實 施例中’配置切換器3 11、313〜316的電晶體的井以接收 0758-A33086TWF—MTKI-07-081 。 9 電源信號vdd。切換器321〜326的情況分別與上述切換写 11〜316的情況相似，差別僅在於切換器321盥324接^ :號Vin，而且當它們的電晶體為p型時，配置電晶體的 井以接收電壓vinbulk。 第3c圖為根據本發明的倍增數位至類比轉換器的 -個較佳實施例的簡略示意圖。第乂圖所示的實施例與第 &圖的相似，差別僅在於切換器312與322為1>型電晶體 而其它的切換器為N型電晶體，僅配置切換器312盘曰曰322 的電晶體的井以接收電源顧vdd，其它切換器的電晶體 :井接地，以及除切換器312與322外其它切換器的電晶 的控制信號為第3a圖中相應控制信號的逆信號。細節此 處不再贅述。 第4a圖〜第4d圖顯示電壓與控制信號之間的關係。 參照第4a圖’根據信號Phl，切換器41〇提供輸入信號 ViP以作為電壓vipbulk。根據信號Phl_，切換器42〇提供 電源k號vdd以作為電壓vipbulk。由於第4a圖〜第如圖 的原理相同，簡潔起見略去對第4b圖〜第4d圖的說明。 另外，第4c圖與第4d圖的電壓vop與v〇n分別代表放大 器341提供的正輸出信號與負輸出信號。 第5a圖為根據本發明倍增數位至類比轉換器的另一 個較佳實施例的簡略示意圖。第5a圖與第3a圖相似，不 同之處僅在於第5a圖中切換器312與322由P型電晶體組 成’且切換器312與322的井分別接收電壓vrefnbulkb與 vrefnbulka。切換器312的電晶體包含接收電壓vrefnbulkb 的井。切換器322包含接收電壓vrefnbuika的井。第7a圖 0758-A33086TWF_MTKI-07-081 10 1376103 與第7b圖為根據本發明第5a圖所示的參考電壓較佳實施 - 例的簡略示意圖。如第7a圖所示，根據控制信號Ph2b與 Ph2b_ ’參考信號Vrefn與電源信號vdd交替作為電壓 vrefnbulkb。如第7b圖所示，根據控制信號Ph2a與Ph2a_， 參考信號Vrefn與電源信號vdd交替作為電麼vrefnbulka。 儘管如此，在另一實施例當中，電壓vrefnbulkb與 vrefnbulka可由電源信號vdd代替。換言之，切換器312 與322的電晶體的井接收電源信號Vdd。 φ 在第5a圖中，所有的切換器有PMOS電晶體實作。 第5b圖為根據本發明的倍增數位至類比轉換器另一個較 佳實施例的簡略示意圖。第5b圖與第5a圖相似，不同之 處僅在於第5b圖中所有的切換器由NMOS電晶體實作， 且第5b圖中所有切換器的控制信號為第5a圖中切換器控 制信號的逆信號。N型電晶體的基底接收接地信號gnd。 在本實施例中，由於子ADC 220提供的數位信號d! 包含兩種狀態（0與1)’切換器311〜316與電容器331、332 φ 之間的連接關係如在第3a圖中所示。如果數位信號Di包 含7種狀態（000〜110)，MDAC的結構如則第6圖中所示， 第6圖為根據本發明的倍增數位至類比轉換器另一個較佳 實施例的簡略示意圖。MDAC 600的模組610〜680輕接於 放大器691的正輸入終端與負輸出終端之間。模組61〇與 模組620的結構相同。模組630〜680的結構都相同。接收 參考信號Vrefp或Vrefn的電晶體包含接收來自子ADC的 數位信號的巧極(gate)。簡潔起見，不再贅述耦接於放大器 691負輸入終端與正輸出終端之間的模組。 0758-A33086TWF_MTKI-07-081 11 1376103 可根據電晶體控制電容器C1〜C8之間的連接關係。 在第一時期中（例如當控制信號phl為高電壓位準時），電 容器C1〜C8並列連接於輸入信號Vip與電壓之間， 以對輸入信號Vip取樣。在第二時期（例如當控制信號 為高電壓位準時），電容器Cl與C2並列連接。電容器dC8 並列連接，然後與電容器Cl串列連接於參考信號Vre印 Vrefn與放大器691的負輸出終端之間。 艺 通過利用PMOS或NMOS電晶體來實作切換器，其 式ADC 100的電力消耗可減少並且電路的時鐘分二以 顯著簡化。 呷J侍以 上述之實細例僅用來例舉本發明之冑施態樣 釋本發明之技術紐’並非絲限制本發明之料 熟悉此技術者可輕易絲之改㈣均#性之㈣均屬於^ 發明所主張之範圍’本發明之權利範圍應以中請專利範圍 為準。 【圖式簡單說明】 比至數位轉換器的較6. Description of the Invention: [Technical Field] The present invention relates to a pipelined analog-to-digital converter (ADC), and more particularly to a multiplying digital to analog converter (Multiplying Digital) -to-Analog Converter, MDAC) Pipeline Analog to Digital Converter [Prior Art] The analog to digital conversion process converts an analog signal into a digital format, where the analog signal is usually represented by a voltage. Known analog to digital conversion methods include tandem structures, delta-sigma structures, side-by-side structures, and pipelined structures. Different structures are available for different needs. The serial analog to digital structure provides a wide range of performance in analog to digital conversion, providing low power consumption and low resolution for quantization. The serial structure typically quantifies the analog data at a rate of 1 bit per cycle. Therefore, digital samples with N-bit resolution are quantized in n cycles. Triangular integral analog to digital structures are commonly used for audio signal processing. This structure is designed to convert high speed, low resolution samples to higher resolution and lower speed outputs. Since more analog data samples are quantized than the actual output, this process is also referred to as oversampling. In contrast, the parallel analog to digital structure provides the fastest rate of each analog signal. For a side-by-side (or "flash") structure, the number of digits per cycle is generated for each analog data sample' without regard to the number of bits N of the resolution. The parallel structure requires that all quantization levels be compared to the signals of class 0758-A33〇86TWF_MTKI-〇7-081 4 1376103. This results in the need to use 2(N)) comparators and 2(N+1)' resistors to achieve digital values, where the resolution per cycle is N bits. - If you want to achieve higher resolution, the circuit complexity of the flash analog to bit converter will be greatly improved. The pipeline analog to digital structure is similar to the serial analog to digital structure and is an analog signal quantization method within the level. There is an algorithm that obtains a 1-bit or 1.5-bit resolution per level. In a converter of 1.5 bits per stage, the digital output Di of each stage is 1, 0 or -1. In a converter of 1 bit per stage, the digital output Di of each stage is 1 or -1 (or 1 or 0). For either of the two algorithms, N levels are used for N-bit digit values. For the parsing of the next bit, one bit is first parsed at each level, and then the analog signal of the subordinate is transmitted to the next stage to resolve another bit. SUMMARY OF THE INVENTION In order to solve the problem that it is difficult to achieve a better balance in the analog-to-digital conversion process of data, the present invention provides a pipeline analog to digital converter. According to an embodiment of the present invention, a pipeline analog to digital converter is provided, comprising: at least one multiplying digital to analog converter, comprising: at least one first capacitor; at least one second capacitor; an amplifier coupled to the first a capacitor and the second capacitor; a plurality of switches controlling a connection between the first capacitor and the second capacitor according to a first control signal, a second control signal, and a digital signal, wherein in a first period The first capacitor is connected in parallel with the second electric bolus, and in a second period, the first capacitor is connected to the second capacitor string, and the 0758-AJ3086TWF_MTKI-07-081 5 1376103 among the switches The first switch is composed of a first transistor; and at least one sub-analog to digital converter for providing a digital signal according to the first control signal and the first control signal. By utilizing the pipeline analog to digital converter of the present invention, higher resolution conversion of data can be achieved with lower circuit complexity, while power consumption can be reduced and circuit (four) clock distribution can be significantly simplified. [Embodiment] The following examples are merely illustrative of the embodiments of the present invention, and the technical features of the present invention are not intended to limit the material of the present invention. The scope of the invention should be determined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a preferred embodiment of a pipeline analog to digital converter in accordance with the present invention. The analog-to-digital converter (ADC) includes a transform stage ΤγΤη and a digital correction block 11〇. The conversion stages τ 〜 Tn convert the analog signals including the differential k numbers Vip and Vin into digital signals D wide Dn (note that the input signal Vin is a positive signal). The digital signal D _ ~ team constitutes the digital format of the analog signal, where Di represents the most important bit, and % represents the most insignificant bit. The digital correction block 11 进行 time-aligned and digitally corrects the digital signal, and outputs the corrected digital signal D. Since the operations of the conversion stages T1 to Tn are all similar, only the level Τ is given in this specification! As an example. Figure 2 is a schematic illustration of a preferred embodiment of a transform stage in accordance with the present invention. The transform stage includes a multiplier-to-analog converter (MDAC) 21() and a sub-ADC 220 〇 MDAC 210 that processes the differential input signals Vin and Vip and control signals ph 1 and ph2 based on the digital signal. Next, the MDAC 210 0758-A33086TWF_MTKI, 〇7-〇81 6^/0103 transmits the processing result to the next conversion stage T2<J sub-adc 220 converts the input signals Vin and Vip according to the control signals PM and Ph2, thus generating the digital signal D! Figure 3a is a simplified schematic diagram of a preferred real-world example of the multiplier-to-analog converter 210 in accordance with the present invention. The MDAc 210 includes switches 311-316 and 321-326, capacitors 331-334, and amplifier 34. The connection relationship between 311 to 316 and the capacitors 33A and 332 is similar to the connection relationship between the switches 321 to 326 and the capacitors 333 and 334. Only the switches 311 to 316 and the capacitors 331, 332 are provided in this specification. The connection relationship is an example. Note that although the switch and the four capacitors are shown in the embodiment of the figure as an example, the number and arrangement of the switch and the capacitor are not limited thereto. In fact, the number and arrangement of switches and capacitors can be designed based on the performance requirements of the pipelined ADc 1〇〇. Referring to Fig. 3a, the switches 311 to 316 control the connections between the capacitors 331 and 332 in accordance with the control signals Phi and Ph2 and the digits 彳g. The switches 311 316 316 may be referred to as first to sixth switches, respectively, Phi and Ph2 may be referred to as a first control signal and a second control signal, respectively, and capacitors 331 and 332 may be referred to as a first capacitor and a second, respectively. Capacitor. As shown in Fig. 3b, in the present embodiment, both of the control signals ph1 and ph2 are clock signals having no overlap. The control signal Phi is reciprocal to phl_. The control signals Ph2 and Ph2 are mutually reciprocal. In one embodiment, the transform stage 产生ι produces an output of a bit, the digit signal Di being a logic "0" or a logic "1". The signals Ph2a and Ph2b are related to the digital signal D!. Similarly, signal Ph2a is reciprocal to signal Ph2a_. The signal Ph2b is reciprocal to the signal Ph2b_. 0758-A33086TWF_MTKJ-〇7-〇81 7 1376103 In the first period, when the Ph1 signal is at the high electric level and the Ph2 signal is at the low voltage level, according to the signals Phl_, Ph2__, Ph2a1, and Ph2b, the switches 311, 314 Turns on with 316 and switches 312, 313, and 315 are turned off. Therefore, the capacitors 331 and 332 are connected in parallel between the input signal vip and the voltage Vcm to sample the input signal vip. In the present embodiment, the switches 311 and 314 are respectively implemented by PMOS transistors. Therefore, the capacitor 331 receives the input signal Vip through only one transistor. Similarly, capacitor 332 receives input signal Vip through only one transistor. In the second period, when the ph1 signal is at a low voltage level and the Ph2 signal is at a high voltage level, the switch 313 and the switch 312 or 315 are turned on, and the switches 311, 314 and 316 are turned off, so that the capacitors 331 and 332 The series is connected between the reference signal Vrefp or Vrefn and the negative turn-off of the amplifier 341. The reference signals Vrefp and Vrefn may be referred to as a first reference signal and a second reference signal, respectively. The negative output terminal of the amplifier 341 outputs a negative output signal von 'the positive output terminal outputs a positive output signal vop. Switches 312 and 315 are controlled by signals Ph2b and ph2a-, respectively. Since the signal puncturing hole and Ph2a- are related to the digital signal Di, each of the switches 312 and 315 is turned on or off according to the digital signal D. For example, assuming that the switch is turned on and the capacitors 331 and 332 are connected in series between the reference signal Vrefp and the negative output terminal of the amplifier 341, the amplifier 341 amplifies the difference between the reference signal Vrefp and the sampling result, wherein the sampling result is stored in In capacitors 331 and 332. In the present embodiment, the capacitor 332 uses only the transistor of the switch 312 or only the transistor of the switch 315 to receive the reference signal Vrefp or V.refn, wherein the transistor of the switch 312 is an NMOS transistor and the switch The transistor of 315 is a pM〇s transistor. 〇 〇 758-A33086TWF_MTKI-07-081 〇 丄 376103 The test signals Vrefp and Vrefn have different voltage levels. In addition, the control signals input to the switches 311 and 316 are not limited to having exactly the same waveform. For example, switch 311 can be controlled by control signal ph1 and switch 316 can be controlled by another control signal Phle. The first few figures show the relationship between the control signals Phi and Phle. The signal phle is reciprocal to the signal Phle. As shown, the control signals ph1 are synchronized with the rising edge of phle, but the control signal Ph 1 e falls before the control signal p h 1 . Similarly, the control signals input to the switches 321 and 326 are not limited to having exactly the same waveform. The switch 321 can be controlled by the control signal phl_, and the switch thief 326 can be controlled by another control signal phle_. One of the switches 311 to 316 is composed of a transistor such as a PM〇s transistor or an NMOS transistor. In this embodiment, the switches 312 and 322 are N-type transistors and the other switches are! > type transistor. In one embodiment (as shown in Figure 3c), switches 312 and 322 are P-type transistors and the other switches are N-type transistors. Referring to Figure 3a' when the transistors of switches 311 and 314 are P-type, the well of the transistor is configured to receive the voltage vipbulk, as will be further explained in the following paragraphs. The transistor of switch 315 includes a well that receives a power signal vdd (power signal vdd is the first power signal). The transistor of switch 312 includes a substrate that receives ground signal gn (i (ground signal gnd is a second power signal). The transistor of switch 313 contains a well that receives voltage vonbulk' as will be further explained in the following paragraph. The transistor of the device 316 comprises a well receiving a voltage Vcm. The voltage Vcm has a voltage level between the reference, voltage levels Vrefp and Vrefn. In an embodiment, the power of the switch 3 11 , 313 - 316 is configured The well of the crystal receives 0758-A33086TWF-MTKI-07-081. 9 The power signal vdd. The cases of the switches 321~326 are similar to those of the above-mentioned switching writes 11~316, respectively, except that the switches 321盥324 are connected: No. Vin, and when their transistors are p-type, the well of the transistor is configured to receive the voltage vinbulk. Figure 3c is a simplified schematic diagram of a preferred embodiment of a multiplicative digital to analog converter in accordance with the present invention. The embodiment shown in the figure is similar to the & figure, except that the switches 312 and 322 are 1> type transistors and the other switches are N type transistors, and only the switch 312 is configured. Transistor The well receives the power supply vdd, the transistors of the other switches: well ground, and the control signals of the crystals of the switches other than the switches 312 and 322 are the inverse signals of the corresponding control signals in Fig. 3a. Details are not here. 4a to 4d show the relationship between the voltage and the control signal. Referring to Fig. 4a', according to the signal Phl, the switch 41A provides the input signal ViP as the voltage vipbulk. According to the signal Phl_, the switch 42〇 The power supply k number vdd is provided as the voltage vipbulk. Since the principle of Fig. 4a to Fig. 4 is the same, the description of Fig. 4b to Fig. 4d is omitted for brevity. In addition, the voltage vp of the 4c and 4d diagrams is omitted. And v〇n respectively represent the positive output signal and the negative output signal provided by the amplifier 341. Fig. 5a is a schematic diagram showing another preferred embodiment of the multiplying digital to analog converter according to the present invention. Fig. 5a is similar to Fig. 3a The only difference is that switches 312 and 322 are composed of P-type transistors in Figure 5a and the wells of switches 312 and 322 receive voltages vrefnbulkb and vrefnbulka, respectively. The transistor of switch 312 contains the received voltage vrefn The well of the bulkb. The switch 322 includes a well that receives the voltage vrefnbuika. Fig. 7a is a diagram of 0758-A33086TWF_MTKI-07-081 10 1376103 and Fig. 7b is a preferred embodiment of the reference voltage shown in Fig. 5a of the present invention - a schematic diagram of an example As shown in Fig. 7a, the reference signal Vrefn and the power supply signal vdd are alternately used as the voltage vrefnbulkb according to the control signals Ph2b and Ph2b_'. As shown in Fig. 7b, according to the control signals Ph2a and Ph2a_, the reference signal Vrefn and the power supply signal vdd are alternately used as the electric power vrefnbulka. Nonetheless, in another embodiment, the voltages vrefnbulkb and vrefnbulka may be replaced by a power signal vdd. In other words, the wells of the transistors of switches 312 and 322 receive the power signal Vdd. φ In Figure 5a, all switches have PMOS transistors implemented. Figure 5b is a simplified schematic diagram of another preferred embodiment of a multiplicative digital to analog converter in accordance with the present invention. Figure 5b is similar to Figure 5a except that all switches in Figure 5b are implemented by NMOS transistors, and the control signals for all switches in Figure 5b are the switch control signals in Figure 5a. Inverse signal. The substrate of the N-type transistor receives the ground signal gnd. In the present embodiment, since the digital signal d! provided by the sub-ADC 220 includes two states (0 and 1), the connection relationship between the switches 311 to 316 and the capacitors 331, 332 φ is as shown in FIG. 3a. . If the digital signal Di contains seven states (000 to 110), the structure of the MDAC is as shown in Fig. 6, and Fig. 6 is a schematic diagram showing another preferred embodiment of the multiplying digital to analog converter according to the present invention. The modules 610 to 680 of the MDAC 600 are lightly connected between the positive input terminal and the negative output terminal of the amplifier 691. The module 61 is identical in structure to the module 620. The modules 630 to 680 have the same structure. The transistor receiving the reference signal Vrefp or Vrefn includes a gate that receives the digital signal from the sub-ADC. For the sake of brevity, the module coupled between the negative input terminal and the positive output terminal of the amplifier 691 will not be described again. 0758-A33086TWF_MTKI-07-081 11 1376103 The connection relationship between capacitors C1 to C8 can be controlled according to the transistor. During the first period (e.g., when the control signal ph1 is at a high voltage level), capacitors C1 to C8 are connected in parallel between the input signal Vip and the voltage to sample the input signal Vip. During the second period (e.g., when the control signal is at a high voltage level), capacitors C1 and C2 are connected in parallel. The capacitors dC8 are connected in parallel and then connected in series with the capacitor C1 between the reference signal Vreprint Vrefn and the negative output terminal of the amplifier 691. By implementing a switch using a PMOS or NMOS transistor, the power consumption of the ADC 100 can be reduced and the clock of the circuit can be significantly simplified. The above-mentioned practical examples are only used to exemplify the present invention. The technique of the present invention is not limited to the material of the present invention. Those skilled in the art can easily change (4) All are within the scope of the invention claimed. The scope of the invention should be determined by the scope of the patent application. [Simple diagram of the figure] Compared to the digital converter
第1圖為根據本發明的管線式類 佳實施例簡略示意圖。 第2圖為根據本發明的變換級的較佳實施例簡略示意 至類比轉換器的較 之間的關係。 * · 至類比轉換器的另 第3a圖為根據本發明的倍增數位 佳實施例的簡略示意圖。 第3b圖顯示控制信號Phi與phle 第3c圖為根據本發明的倍增數位 0758-A33086TWF_MTKIi〇7-〇81 12 1376103 一個較佳實施例的簡略示意圖。 第4a圖〜第4d圖顯示電壓與控制信號之間的關係。 第5a圖為根據本發明倍增數位至類比轉換器的另一 個較佳實施例的簡略示意圖。 第5b圖為根據本發明的倍增數位至類比轉換器另一 個較佳實施例的簡略.示意圖。 第6圖為根據本發明的倍增數位至類比轉換器另一個 較佳實施例的簡略示意圖。 第7a圖與第7b圖為根據本發明第5a圖所示的參考電 壓較佳實施例的簡略示意圖。 【主要元件符號說明】 100 :管線式ADC ; 110 :數位校正區塊； 210、600 : MDAC ; 220 :子 ADC ; 311 〜316、321 〜326 、410、420 :切換器； 331〜334 :電容器；. 341、691 :放大器； 610〜680:模組； Τι〜Tn ··變換級； C1〜C8 :電容器。 0758-A33086TWF ΜΤΚΙ-07-Ο81 13BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a preferred embodiment of a pipeline type according to the present invention. Figure 2 is a diagram showing the relationship between the preferred embodiment of the transform stage in accordance with the present invention and the analog converter to analog converter. * Figure 3a to the analog converter is a simplified schematic diagram of a preferred embodiment of the multiplicative digital according to the present invention. Figure 3b shows control signals Phi and phle. Figure 3c is a simplified schematic diagram of a preferred embodiment of multiplier digits 0758-A33086TWF_MTKIi〇7-〇81 12 1376103 in accordance with the present invention. Figures 4a through 4d show the relationship between voltage and control signals. Figure 5a is a simplified schematic diagram of another preferred embodiment of a multiplying digital to analog converter in accordance with the present invention. Figure 5b is a simplified, schematic illustration of another preferred embodiment of a multiplicative digital to analog converter in accordance with the present invention. Figure 6 is a simplified schematic diagram of another preferred embodiment of a multiplicative digital to analog converter in accordance with the present invention. Fig. 7a and Fig. 7b are schematic diagrams showing a preferred embodiment of the reference voltage shown in Fig. 5a of the present invention. [Main component symbol description] 100: pipeline ADC; 110: digital correction block; 210, 600: MDAC; 220: sub-ADC; 311 ~ 316, 321 ~ 326, 410, 420: switch; 331~334: capacitor ; 341, 691: amplifier; 610 ~ 680: module; Τι ~ Tn · · conversion stage; C1 ~ C8: capacitor. 0758-A33086TWF ΜΤΚΙ-07-Ο81 13