CN109873644B

CN109873644B - Multiplying digital-to-analog converter of pipeline analog-to-digital converter

Info

Publication number: CN109873644B
Application number: CN201711269900.6A
Authority: CN
Inventors: 陈志龙; 吴盈澂; 黄诗雄
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2017-12-05
Filing date: 2017-12-05
Publication date: 2022-11-22
Anticipated expiration: 2037-12-05
Also published as: CN109873644A

Abstract

The invention discloses a multiplication digital-to-analog converter applied to a pipeline analog-to-digital converter. The multiplying digital-to-analog converter comprises an operational amplifier. The multiplying digital-to-analog converter samples the differential input signal in a sampling stage and performs subtraction and multiplication operations according to the first reference voltage and the second reference voltage in an amplifying stage. A common mode voltage of the first reference voltage and the second reference voltage is not substantially equal to a common mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to half of the maximum peak-to-peak value allowed for the differential input signal. One of the first reference voltage and the second reference voltage may be a ground level. The invention helps to further reduce the whole circuit area of the pipeline analog-digital converter.

Description

Multiplying digital-to-analog converter of pipeline analog-to-digital converter

Technical Field

The present invention relates to a pipeline analog-to-digital converter (also called pipeline ADC), and more particularly, to a multiplying digital-to-analog converter (hereinafter abbreviated as MDAC) of the pipeline ADC.

Background

Fig. 1 shows a conventional pipeline adc 100, which includes a plurality of serially connected operation stages 110, an end adc 120 and a digital correction circuit 130. Differential input signal V _in After multi-stage comparison, subtraction, amplification, and other operations, the calibration circuit 130 finally calibrates the output of each operation stage 110 and the output of the end adc 120 to generate a digital code D, i.e., a differential input signal V _in And (4) performing analog-digital conversion on the obtained product. The operation principle of the pipeline adc 100 is well known to those skilled in the art, and thus will not be described in detail.

Fig. 2 is a functional block diagram of one of the operation stages 110 of fig. 1. The operational stage 110 includes a sub-adc 112, a decoder 114, and a multiplying dac116. The sub analog to digital converter 112 comprises a plurality of comparators that convert the differential input signal V _in And a plurality of preset voltages V _R1 To V _Rn And comparing to obtain a digital signal b. The number of comparators and the number of preset voltages (i.e., n value) are related to the number of bits of pipeline adc 100. The decoder 114 converts the reference voltage V according to the digital signal b _REF+ Reference toVoltage V _REF- And/or voltage V _{CM_REF} And provided to the MDAC116. Voltage V _{CM_REF} Is a reference voltage V _REF+ And a reference voltage V _REF- Of the common mode voltage. MDAC116 pairs differential input signals V _in Samples are taken and the differential input signal V is coupled according to the voltage provided by the decoder 114 _in Performing subtraction and multiplication to output a differential output signal V _out . Differential output signal V _out Becomes the differential input signal for the next operational stage 110 or end adc 120.

For stable operation of pipeline ADC 100, voltage V _{CM_REF} Ideally should equal the differential input signal V _in Of the common-mode voltage V _{CM_PGA} And a reference voltage V _REF+ And a reference voltage V _REF- Is typically a differential input signal V _in Allowed maximum peak-to-peak value V _{pp_max} Half of the total. For example, assume a differential input signal V _in Is defined as between VDD and ground (i.e., V) _{pp_max} = VDD-0= VDD), then V _REF+ -V _REF- ＝0.5V _{pp_max} =0.5VDD, and V _{CM_REF} ＝V _{CM_PGA} =0.5VDD. FIG. 3 is a diagram of a conventional method for generating a reference voltage V _REF+ And a reference voltage V _REF- A circuit diagram of (a). Such circuits are well known to those skilled in the art and will not be described in detail. In order to meet the above requirements, the prior art usually adjusts the resistance values of the resistors R1 and R2 and the current of the current source Ir in fig. 3 to make V _REF+ =0.75VDD and V _REF- =0.25VDD. However, the above conditions limit the reference voltage V _REF+ And a reference voltage V _REF- The degree of freedom of design of (2). Furthermore, the unity gain buffers (unit gain buffers) 310 and 320 in fig. 3 occupy a relatively large circuit area.

Disclosure of Invention

In view of the disadvantages of the prior art, an object of the present invention is to provide a multiplying digital-to-analog converter of a pipeline analog-to-digital converter, which can improve the design freedom of the reference voltage of the multiplying digital-to-analog converter and contribute to further reducing the overall circuit area of the pipeline analog-to-digital converter.

The invention discloses a multiplication digital-to-analog converter, which is applied to a pipeline analog-to-digital converter and operated in a sampling stage or an amplifying stage, and comprises the following components: an operational amplifier and four capacitors. The first end of the first capacitor is coupled to a first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to a first input end of the operational amplifier in the amplifying stage. The second terminal of the first capacitor receives a differential input signal in the sampling stage and is coupled to a first output terminal of the operational amplifier in the amplifying stage. The first end of the second capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the first input terminal of the operational amplifier in the amplifying stage. The second end of the second capacitor receives the differential input signal in the sampling stage and is coupled to a second reference voltage in the amplifying stage. The first end of the third capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to a second input end of the operational amplifier in the amplifying stage. The second terminal of the third capacitor receives the differential input signal in the sampling stage and is coupled to a second output terminal of the operational amplifier in the amplifying stage. The first end of the fourth capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage. The second terminal of the fourth capacitor receives the differential input signal in the sampling stage and is coupled to a third reference voltage in the amplifying stage. One of the second reference voltage and the third reference voltage is substantially at ground level.

The invention also discloses a multiplication digital-to-analog converter, which is applied to a pipeline analog-to-digital converter and operated in a sampling stage or an amplifying stage and comprises an operational amplifier and four capacitors. The first end of the first capacitor is coupled to a first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to a first input end of the operational amplifier in the amplifying stage. The second terminal of the first capacitor receives a differential input signal in the sampling stage and is coupled to a first output terminal of the operational amplifier in the amplifying stage. The first end of the second capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the first input end of the operational amplifier in the amplifying stage. The second end of the second capacitor receives the differential input signal in the sampling stage and is coupled to a second reference voltage in the amplifying stage. The first end of the third capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to a second input terminal of the operational amplifier in the amplifying stage. The second terminal of the third capacitor receives the differential input signal in the sampling stage and is coupled to a second output terminal of the operational amplifier in the amplifying stage. The first end of the fourth capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage. The second terminal of the fourth capacitor receives the differential input signal in the sampling stage and is coupled to a third reference voltage in the amplifying stage. The DC voltages of the first and second input terminals of the operational amplifier in the amplifying stage are not substantially equal to the first reference voltage.

The invention also discloses a multiplication digital-to-analog converter which is applied to a pipeline analog-to-digital converter and operated in a sampling stage or an amplifying stage and comprises an operational amplifier and six capacitors. The first end of the first capacitor is coupled to a first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to a first input end of the operational amplifier in the amplifying stage. The second terminal of the first capacitor receives a differential input signal in the sampling stage and is coupled to a first output terminal of the operational amplifier in the amplifying stage. The first end of the second capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the first input end of the operational amplifier in the amplifying stage. The second end of the second capacitor receives the differential input signal in the sampling stage and is coupled to a second reference voltage in the amplifying stage. The first end of the third capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to a second input end of the operational amplifier in the amplifying stage. The second terminal of the third capacitor receives the differential input signal in the sampling stage and is coupled to a second output terminal of the operational amplifier in the amplifying stage. The first end of the fourth capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage. The second terminal of the fourth capacitor receives the differential input signal in the sampling stage and is coupled to a third reference voltage in the amplifying stage. The first terminal of the fifth capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the first input terminal of the operational amplifier in the amplifying stage. The second end of the fifth capacitor receives the differential input signal in the sampling stage and is coupled to a common mode voltage of the second reference voltage and the third reference voltage in the amplifying stage. The first terminal of the sixth capacitor is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage. The second terminal of the sixth capacitor receives the differential input signal in the sampling stage and is coupled to the common mode voltage in the amplifying stage.

The multiplying digital-to-analog converter of the pipelined analog-to-digital converter of the present invention allows reference voltage shifting and scaling without affecting the operation of the multiplying digital-to-analog converter. Compared with the prior art, the invention improves the design freedom of the reference voltage and is also beneficial to further reducing the whole circuit area of the pipeline analog-digital converter.

The features, implementations, and technical effects of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a prior art pipelined analog-to-digital converter;

FIG. 2 is a functional block diagram of one of the operational stages of FIG. 1;

FIG. 3 is a diagram of a conventional method for generating a reference voltage V _REF+ And a reference voltage V _REF- A circuit diagram of (a);

FIG. 4 is a circuit diagram of an operation stage of a 1.5-bit pipelined ADC according to an embodiment of the present invention;

FIG. 5A is a circuit diagram of the pipeline ADC of FIG. 4 operating in a sampling phase;

FIG. 5B is a circuit diagram of the pipeline ADC of FIG. 4 during an amplifying stage;

FIG. 6 is a circuit diagram of an operation stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention;

FIG. 7 is a circuit diagram of an operation stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention; and

FIG. 8 is a circuit diagram of an operation stage of a 2.5-bit pipelined ADC according to another embodiment of the present invention.

Description of reference numerals:

100. pipeline analog-to-digital converter

110. 400, 600, 700, 800 operation stage

112. 410, 610, 810 sub analog-digital converter

114. 420, 620, 820 decoder

116. 430 multiplication digital-to-analog converter

432. 632, 832 operational amplifier

Detailed Description

The technical terms used in the following description refer to the conventional terms in the field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.

The present disclosure includes a multiplying digital-to-analog converter of a pipeline analog-to-digital converter. Since some of the components included in the multiplying digital-to-analog converter of the present invention may be known components alone, the following description will omit details of known components without affecting the full disclosure and feasibility of the device invention.

FIG. 4 is a circuit diagram of an operation stage of a 1.5-bit pipeline ADC according to an embodiment of the present invention. Differential input signal V _in (including signals)

And

) It may be the output of a circuit (e.g., a Programmable Gain Amplifier (PGA)) in the previous stage of the pipeline adc, or the output of an operation stage in the previous stage of the operation stage. The operational stage 400 includes a sub analog to digital converter 410, a decoder 420, and an MDAC 430. The operation of the sub adc 410 and the decoder 420 is the same as or similar to that of the conventional sub adc 112 and decoder 114, respectively, and thus will not be described again. The MDAC 430 includes an operational amplifier 432, capacitors C0a, C1a, C0b, C1b, switches S0a S4a, and switches S0b S4b. The capacitances C0a, C1a, C0b, and C1b are substantially the same in capacitance value. The MDAC 430 alternately operates in a sampling phase and an amplifying phase. In the sampling phase, switches S0a, S1a, S2a, S0b, S1b, S2b are conductive, the remaining switches are non-conductive (fig. 5A); in the amplification phase, the switches S3a, S4a, S3B, S4B are conductive and the remaining switches are non-conductive (fig. 5B). As shown in FIG. 5B, the DC voltage at the input of the operational amplifier 432 during the amplification stage is V _X 。

One end of the capacitor C0a (or C0 b) is coupled to the reference voltage V through the switch S2a (or S2 b) in the sampling stage _{CM_OPI_S} And is not coupled to the reference voltage V in the amplifying stage _{CM_OPI_S} Coupled to an input terminal of the operational amplifier 432; the other end of the capacitor C0a (or C0 b) receives the input signal through the switch S0a (or S0 b) in the sampling stage

(or

) And is coupled to the non-inverting output (or inverting output) of the operational amplifier 432 through the switch S3a (or S3 b) during the amplification stage.

One end of the capacitor C1a (or C1 b) is coupled to the reference voltage V through the switch S2a (or S2 b) in the sampling stage _{CM_OPI_S} And is not coupled to the reference voltage V in the amplifying stage _{CM_OPI_S} Coupled to an input terminal of the operational amplifier 432; the other end of the capacitor C1a (or C1 b) receives the input signal through the switch S1a (or S1 b) in the sampling stage

(or

) And receives the output voltage of the decoder 420 through the switch S4a (or S4 b) during the amplification stage.

The decoder 420 outputs a reference voltage V according to the digital value b _REF+ Reference voltage V _REF- And/or voltage V _{CM_REF} . For example, in some amplification stage, the decoder 420 will reference the voltage V _REF+ Outputs to the capacitor C1a through the switch S4a, and provides the reference voltage V _REF- The output is output to a capacitor C1b through a switch S4 b; in another amplification stage, the decoder 420 applies a voltage V _{CM_REF} Through switch S4a to capacitor C1a and through switch S4b to capacitor C1b.

According to the principle of charge conservation, the total charge stored in the sampling stage should ideally be equal to the total charge stored in the amplification stage for all the capacitors coupled to one of the input terminals of the operational amplifier 432 (i.e., the capacitors C0a and C1a or the capacitors C0b and C1 b), so that the following equation can be obtained (note that the reference voltage V is the above-mentioned reference voltage V) _{CM_OPI_S} Corresponding voltage V _{CM_REF} Not substantially equal to voltage V _{CM_PGA} In the following, the DC voltage V is derived _X Temporarily at a voltage V _{CM_OPI} Instead of the reference voltage V _{CM_OPI_S} Voltage V of _{CM_OPI} Corresponding voltage V _{CM_REF} Is substantially equal to the voltage V _{CM_PGA} Case (2):

(V _{CM_PGA} -V _{CM_OPI} )NC＝(N-1)C(V _{CM_REF} -V _X )+(V _{CM_OPO} -V _X )C

NV _{CM_PGA} -NV _{CM_OPI} ＝(N-1)V _{CM_REF} -(N-1)V _X +V _{CM_OPO} -V _X

NV _{CM_PGA} -NV _{CM_opi} ＝(N-1)V _{CM_REF} -NV _X +V _{CM_OPO}

wherein C is the capacitance of the capacitors C0a, C1a, C0b, C1b, V _{CM_PGA} For a differential input signal V _in N is the number of capacitors coupled to one input terminal of the operational amplifier 432 (N = 2) ^P P is an integer part of the bit number of the pipeline analog-to-digital converter), V _{CM_OPO} For differentially outputting a signal V _out (including the output signal)

And

) Of the common-mode voltage.

When the reference voltage V _REF+ And a reference voltage V _REF- Is substantially equal to the differential input signal V _in When the voltage V is the same as the common mode voltage (i.e. when the voltage V is lower than the voltage V) _{CM_REF} Is substantially equal to the voltage V _{CM_PGA} ) Time, ideally upper voltage V _{CM_OPO} Is also substantially equal to V _{CM_REF} And V _{CM_PGA} And then:

from the above derivation, it can be observed that when the voltage V is _{CM_REF} Is substantially equal to the voltage V _{CM_PGA} When the input terminal of the operational amplifier 432 is at the DC voltage V of the amplifying stage _X Substantially equal toAt a reference voltage V _{CM_OPI} 。

When the voltage V is set to increase the degree of freedom in design of the MDAC 430 _{CM_REF} Not substantially equal to voltage V _{CM_PGA} Time (suppose V) _{CM_PGA} ＝ΔV _CM +V _{CM_REF} And a voltage V _{CM_OPO} Is still substantially equal to V _{CM_PGA} ) To obtain:

from the above formula, it can be observed that if the reference voltage V is set _{CM_OPI} Generating

Will make the input of the operational amplifier 432 in the amplifying stage _X Substantially free of voltage V _{CM_REF} Not substantially equal to voltage V _{CM_PGA} I.e. the direct voltage V is caused to be _X Yet substantially equal to the reference voltage V of the original design _{CM_OPI} . In other words, when the voltage V is _{CM_REF} Is substantially equal to the voltage V _{CM_PGA} When the input terminal of the operational amplifier 432 is at the DC voltage V of the amplifying stage _X Is substantially equal to the reference voltage V _{CM_OPI} (ii) a When the voltage V is _{CM_REF} Not substantially equal to voltage V _{CM_PGA} In the invention, the reference voltage V is used _{CM_OPI} Offset of

By the amount of (d), the offset reference voltage

DC voltage V that will cause the input of operational amplifier 432 to be in the amplification stage _X Still substantially equal to the original reference voltage V _{CM_OPI} . It can be seen that in the embodiment of FIG. 4, the DC voltage V at the input of the operational amplifier 432 during the amplification stage _X Not substantially equal to the reference voltage V _{CM_OPI_S} . By applying a voltage at a reference voltage V _{CM_OPI_S} And a DC voltage V _X Is offset from the manufacturing

Can effectively reduce the voltage V applied to the operational amplifier 432 _{CM_REF} Not substantially equal to voltage V _{CM_PGA} The degree of influence of (c).

The circuit of FIG. 4 makes reference voltage V _REF+ And a reference voltage V _REF- Of the common-mode voltage V _{CM_REF} Is no longer limited by having to be substantially equal to the differential input signal V _in Of the common-mode voltage V _{CM_PGA} Therefore, in some embodiments, the reference voltage V is described above _REF- May be biased to ground level. For example, reference voltage V _REF+ Common mode voltage V _{CM_REF} And a reference voltage V _REF- Can be shifted from 0.75VDD, 0.5VDD and 0.25VDD to 0.5VDD, 0.25VDD and 0, respectively, and the reference voltage V _REF+ And common mode voltage V _{CM_REF} Difference between and reference voltage V _REF- And a common mode voltage V _{CM_REF} The difference between them remains substantially unchanged (0.25 VDD). Reference voltage V _REF- The design as ground level has the following advantages: (1) A unit gain buffer is saved, and the circuit area is effectively reduced; (2) Ground levels may provide greater drive capability than non-ground levels.

FIG. 6 is a circuit diagram of an operation stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention. The operation stage 600 includes a sub analog-to-digital converter 610, a decoder 620, and an MDAC (circuits other than the sub analog-to-digital converter 610 and the decoder 620). The operation of the sub adc 610 and the decoder 620 is the same as or similar to that of the conventional sub adc 112 and decoder 114, respectively, and thus the description thereof is omitted. The MDAC includes an operational amplifier 632, capacitors C0a, C1a ', C0b, C1b', switches S0a to S4a, S1a ', S4a', and switches S0b to S4b, S1b ', S4b'. The capacitance values of the capacitor C0a and the capacitor C0b are substantially the same. The MDAC alternately operates in a sampling phase and an amplifying phase. In the sampling stage, the switches S0a, S1a ', S2a, S0b, S1b', S2b are turned on, and the remaining switches are turned off; in the amplification phase, the switches S3a, S4a ', S3b, S4b' are conductive, while the remaining switches are non-conductive.

The capacitors C0a, C0b, C1a, C1b are connected and operated similarly to the capacitors C0a, C0b, C1a, C1b of FIG. 4, respectively, with the difference that the reference voltage V is provided _{CM_OPI} Substantially equal to the DC voltage V of the input terminal of the operational amplifier 632 in the amplifying stage _X This is because in this embodiment, the voltage V _{CM_REF} Is substantially equal to the voltage V _{CM_PGA} I.e. the voltage V _{CM_REF} There is no offset.

One end of the capacitor C1a '(or C1 b') is coupled to the reference voltage V through the switch S2a (or S2 b) in the sampling stage _{CM_OPI} And is not coupled to the reference voltage V in the amplifying stage _{CM_OPI} Coupled to an input terminal of the operational amplifier 632; the other end of the capacitor C1a '(or C1 b') receives the input signal through the switch S1a '(or S1 b') in the sampling stage

(or

) And receiving the reference voltage V through the switch S4a '(or S4 b') in the amplifying stage _REF+ And a reference voltage V _REF- Of the common-mode voltage V _{CM_REF} 。

In this embodiment, the reference voltage V _REF+ And a reference voltage V _REF- Does not necessarily satisfy V _REF+ -V _REF- ＝0.5V _{pp_max} (V _{pp_max} For a differential input signal V _in Maximum allowed peak-to-peak), but with reference voltage V _REF+ And a reference voltage V _REF- Of the common-mode voltage V _{CM_REF} Is still substantially equal to the differential input signal V _in Of the common-mode voltage V _{CM_PGA} . For example, assume a differential input signal V _in Is defined as between VDD and ground (i.e., V) _{pp_max} = VDD-0= VDD), then V _REF+ And V _REF- Can be designed to be equal to V _{pp_max} = VDD (example)Such as V _REF+ ＝VDD，V _REF- = 0), and V _{CM_REF} Is still substantially equal to V _{CM_PGA} =0.5VDD. In this embodiment, since the reference voltage V _REF+ And a reference voltage V _REF- Of the common-mode voltage V _{CM_REF} Is still substantially equal to the differential input signal V _in Of the common-mode voltage V _{CM_PGA} So that the reference voltage V _{CM_OPI} Substantially equal to the DC voltage V of the input terminal of the operational amplifier 632 in the amplification stage _X 。

In response to a reference voltage V _REF+ And a reference voltage V _REF- The capacitance values of the capacitors C1a, C1a ', C1b and C1b' need to be adjusted accordingly. The sum of the capacitance values of the capacitors C1a (or C1 b) and C1a '(or C1 b') is substantially equal to the capacitance value of the capacitor C0a (or C0 b). The ratio of the capacitance values of the capacitors C1a and C1a '(or C1b and C1 b') to (V) _REF+ -V _REF- )/V _{pp_max} It is relevant. More specifically, assume that the capacitance value of the capacitor C0a (or C0 b) is C, and the capacitance value of the capacitor C1a (or C1 b) is XC (0)<X<1) The capacitance value of the capacitor C1a '(or C1 b') is YC (0)<Y<1) Then X + Y is substantially equal to 1, and X =0.5 × V _{pp_max} /(V _REF+ -V _REF- ). That is, when (V) _REF+ -V _REF- ) Is a V _{pp_max} X =1/2R. In one example, when V _{pp_max} = VDD-0= VDD, and V _REF+ = VDD and V _REF- ＝0(V _{CM_REF} ＝(VDD+0)/2＝0.5VDD＝V _{CM_PGA} ) Then, R = (VDD-0)/VDD =1, X =1/2r =0.5, y =1-X =0.5. In another example, when V _{pp_max} = VDD-0= VDD, and V _REF+ =0.9VDD and V _REF- ＝0.1VDD(V _{CM_REF} ＝(0.9VDD+0.1VDD)/2＝0.5VDD＝V _{CM_PGA} ) Then, R = (0.9 VDD-0.1 VDD)/VDD =0.8, X =1/2r =0.625, y =1-X =0.325.

The circuit of FIG. 6 enables a reference voltage V _REF+ And a reference voltage V _REF- Is no longer limited by the differential input signal V which must be substantially equal to 0.5 times _in Allowed maximum peak-to-peak value V _{pp_max} Therefore, in some embodiments, the reference voltage V is _REF- Can be contracted byPut to the ground level.

In summary, in order to provide more design freedom for the MDAC or the pipeline adc using the MDAC, the embodiments of fig. 4 and 6 are provided to shift or scale the reference voltage (V) of the MDAC respectively _REF+ And V _REF- ) The technical effect of (1). When one of the reference voltages is shifted or scaled to the ground level, the present invention can omit a unity gain buffer to effectively reduce the circuit area.

The present invention can also perform the aforementioned shifting operation and zooming operation simultaneously, and fig. 7 shows the corresponding circuits. The operation stage 700 is similar to the operation stage 600 in circuit and operation, except that the reference voltage V is coupled to the capacitor of FIG. 6 during the sampling phase _{CM_OPI} Substantially equal to the DC voltage V of the input terminal of the operational amplifier 632 in the amplifying stage _X The reference voltage V coupled to the capacitor of FIG. 7 in the sampling stage _{CM_OPI_S} Is not substantially equal to the DC voltage V of the input terminal of the operational amplifier 632 in the amplifying stage _X . Reference voltage V _{CM_OPI_S} Can be designed as

Wherein Δ V _CM ＝V _{CM_PGA} -V _{CM_REF} 。

FIG. 8 is a circuit diagram of an operation stage of a 2.5-bit pipelined ADC according to another embodiment of the present invention. The operation stage 800 includes a sub analog to digital converter 810, a decoder 820, and an MDAC (circuits other than the sub analog to digital converter 810 and the decoder 820). The operation of the sub adc 810 and the decoder 820 is the same as or similar to that of the conventional sub adc 112 and decoder 114, respectively, and thus the description thereof is omitted. The MDAC alternately operates in a sampling phase and an amplifying phase. Fig. 8 only shows a part of the circuit of the MDAC, that is, a part coupled to one of the input terminals of the operational amplifier 832, and those skilled in the art can deduce the circuit of the other parts of the MDAC of fig. 8 according to the disclosure of fig. 6 to 8. Those skilled in the art will also appreciate the details of the circuit and operation of the present invention applied to the higher bit pipelined adc according to the disclosure of fig. 6-8.

Compared to the operation stage 600 and the operation stage 700, the operation stage 800 further includes capacitors C2a, C2a ', C3a, and C3a', and capacitors C2b, C2b ', C3b, and C3b' (not shown) coupled to another input terminal of the operational amplifier 832. Capacitors C1A C3a (or C1B C3B, not shown) receive input signals through switch set S1A (or S1B, not shown)

(or

Not shown) and receives the output voltage of the decoder 820 through the switch set S4A (or S4B, not shown). Capacitors C1A 'to C3a' (or C1B 'to C3B', not shown) receive input signals through switch set S1A '(or S1B', not shown)

(or

Not shown), and is coupled to the reference voltage V via the switch set S4A '(or S4B', not shown) _REF+ And a reference voltage V _REF- Of the common-mode voltage V _{CM_REF} . The capacitors C1a C3a and C1 a-C3 a '(or C1b C3b and C1 b-C3 b', not shown) are coupled to a reference voltage V through a switch S2a _{CM_OPI_S} . The three switches in the group of switch sets S1A, S1A ', S4A' (or S1B, S1B ', S4B') are simultaneously conducting or non-conducting, the switching operations of the switch sets S1A, S1A ', S4A' (or S1B, S1B ', S4B') are the same as the switches S1A, S1A ', S4A' (or S1B, S1B ', S4B') of fig. 6 and fig. 7, respectively, and therefore, the description thereof is omitted.

Assume that the capacitance of the capacitor C0a is C and the capacitance of the capacitor C1a is XC (0)<X<1) The capacitance value of the capacitor C1a' is YC (0)<Y<1) Then X + Y is substantially equal to 1, and X =0.5 × V _{pp_max} /(V _REF+ -V _REF- ). The capacitor pairs (C2 a, C2a ') and (C3 a, C3 a') are identical. When the voltage V _{CM_REF} Is substantially equal to voltageV _{CM_PGA} When the input terminal of the operational amplifier 832 is at the DC voltage V of the amplifying stage _X Is substantially equal to the reference voltage V _{CM_OPI_S} (ii) a When the voltage V _{CM_REF} Not substantially equal to voltage V _{CM_PGA} When the input terminal of the operational amplifier 832 is at the DC voltage V of the amplifying stage _X Not substantially equal to the reference voltage V _{CM_OPI_S} I.e. that

Wherein Δ V _CM ＝V _{CM_PGA} -V _{CM_REF} N =4 (for a 2.5 bit pipelined analog-to-digital converter). In one embodiment, the reference voltage V _REF- May be substantially at ground level.

Because the details of the implementation and variations of the disclosed method invention can be understood by those skilled in the art from the disclosure of the disclosed apparatus invention, the repetitive description is omitted herein for the avoidance of redundancy without affecting the disclosed requirements and the implementability of the method invention. It should be noted that the shapes, sizes, proportions and the like of the elements in the drawings are illustrative only, and are not intended to limit the invention, which is understood by those skilled in the art. Furthermore, although the foregoing embodiments are exemplified by 1.5-bit or 2.5-bit pipeline analog-to-digital converters, the invention is not limited thereto, and those skilled in the art can appropriately apply the invention to pipeline analog-to-digital converters with other bits according to the disclosure of the invention.

Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

Claims

1. A multiplying digital-to-analog converter applied to a pipeline analog-to-digital converter and operated in a sampling stage or an amplifying stage comprises:

an operational amplifier;

a first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to a first reference voltage in the sampling stage, and coupled to a first input terminal of the operational amplifier without being coupled to the first reference voltage in the amplifying stage, wherein the second terminal receives a differential input signal in the sampling stage, and coupled to a first output terminal of the operational amplifier in the amplifying stage;

a second capacitor having a third terminal and a fourth terminal, wherein the third terminal is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the first input terminal of the operational amplifier in the amplifying stage, wherein the fourth terminal receives the differential input signal in the sampling stage, and is coupled to a second reference voltage in the amplifying stage;

a third capacitor having a fifth terminal and a sixth terminal, wherein the fifth terminal is coupled to the first reference voltage in the sampling stage, and is coupled to a second input terminal of the operational amplifier without being coupled to the first reference voltage in the amplifying stage, wherein the sixth terminal receives the differential input signal in the sampling stage, and is coupled to a second output terminal of the operational amplifier in the amplifying stage; and

a fourth capacitor having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage, wherein the eighth terminal receives the differential input signal in the sampling stage, and is coupled to a third reference voltage in the amplifying stage;

wherein one of the second reference voltage and the third reference voltage is substantially a ground level, and a dc voltage of the first input terminal and the second input terminal of the operational amplifier in the amplifying stage is not substantially equal to the first reference voltage.

2. The multiplying digital-to-analog converter of claim 1, wherein the common-mode voltage of the differential input signal is a first voltage, the common-mode voltages of the second reference voltage and the third reference voltage are a second voltage, and the difference between the first reference voltage and the dc voltages of the first input terminal and the second input terminal of the operational amplifier in the amplifying stage is substantially equal to (N-1)/N times the difference between the first voltage and the second voltage, where N is a positive integer.

3. The multiplying digital to analog converter of claim 2, wherein N =2 ^P And P is the integer part of the bit number of the pipeline analog-to-digital converter.

4. The multiplying digital-to-analog converter of claim 1, further comprising:

a fifth capacitor having a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the first input terminal of the operational amplifier in the amplifying stage, wherein the tenth terminal receives the differential input signal in the sampling stage, and is coupled to a common mode voltage of the second reference voltage and the third reference voltage in the amplifying stage; and

a sixth capacitor having a tenth terminal and a tenth terminal, wherein the tenth terminal is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage, wherein the tenth terminal receives the differential input signal in the sampling stage, and is coupled to the common mode voltage in the amplifying stage.

5. The multiplying digital-to-analog converter of claim 4, wherein the capacitance of the second capacitor is X times the capacitance of the first capacitor, the capacitance of the fifth capacitor is Y times the capacitance of the first capacitor, and the sum of X and Y is substantially 1.

6. The DAC of claim 5 wherein the difference between the second reference voltage and the third reference voltage is a first voltage difference, wherein X is equal to 1/2R, and R is positive if the first voltage difference is substantially R times the maximum peak-to-peak value allowed for the differential input signal.

7. The multiplying digital-to-analog converter of claim 4, wherein the difference between the second reference voltage and the third reference voltage is not substantially equal to half of the maximum peak-to-peak allowed for the differential input signal.

8. A multiplying digital-to-analog converter applied to a pipeline analog-to-digital converter and operated in a sampling stage or an amplifying stage comprises:

an operational amplifier;

a first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to a first reference voltage in the sampling stage, and coupled to a first input terminal of the operational amplifier in the amplifying stage without being coupled to the first reference voltage, wherein the second terminal receives a differential input signal in the sampling stage, and coupled to a first output terminal of the operational amplifier in the amplifying stage;

a fourth capacitor having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the first reference voltage during the sampling stage, and is coupled to the second input terminal of the operational amplifier without being coupled to the first reference voltage during the amplifying stage, wherein the eighth terminal receives the differential input signal during the sampling stage, and is coupled to a third reference voltage during the amplifying stage;

the first and second input terminals of the operational amplifier have a DC voltage substantially not equal to the first reference voltage in the amplifying stage.

9. A multiplying digital-to-analog converter, applied to a pipeline analog-to-digital converter and operated in a sampling stage or an amplifying stage, comprises:

an operational amplifier;

a third capacitor having a fifth terminal and a sixth terminal, wherein the fifth terminal is coupled to the first reference voltage in the sampling stage, and is coupled to a second input terminal of the operational amplifier without being coupled to the first reference voltage in the amplifying stage, wherein the sixth terminal receives the differential input signal in the sampling stage, and is coupled to a second output terminal of the operational amplifier in the amplifying stage;

a sixth capacitor having a tenth terminal and a twelfth terminal, wherein the tenth terminal is coupled to the first reference voltage in the sampling stage, and is not coupled to the first reference voltage but coupled to the second input terminal of the operational amplifier in the amplifying stage, and wherein the twelfth terminal receives the differential input signal in the sampling stage and is coupled to the common mode voltage in the amplifying stage.