TWI367487B - Flash memory programming and verification method with reduced leakage current - Google Patents

Flash memory programming and verification method with reduced leakage current

Info

Publication number
TWI367487B
TWI367487B TW096111973A TW96111973A TWI367487B TW I367487 B TWI367487 B TW I367487B TW 096111973 A TW096111973 A TW 096111973A TW 96111973 A TW96111973 A TW 96111973A TW I367487 B TWI367487 B TW I367487B
Authority
TW
Taiwan
Prior art keywords
flash memory
leakage current
verification method
reduced leakage
memory programming
Prior art date
Application number
TW096111973A
Other languages
English (en)
Other versions
TW200805380A (en
Inventor
Ashot Melik-Martirosian
Ed Runnion
Mark Randolph
Meng Ding
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc filed Critical Spansion Llc
Publication of TW200805380A publication Critical patent/TW200805380A/zh
Application granted granted Critical
Publication of TWI367487B publication Critical patent/TWI367487B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
TW096111973A 2006-04-05 2007-04-04 Flash memory programming and verification method with reduced leakage current TWI367487B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/398,415 US7630253B2 (en) 2006-04-05 2006-04-05 Flash memory programming and verification with reduced leakage current

Publications (2)

Publication Number Publication Date
TW200805380A TW200805380A (en) 2008-01-16
TWI367487B true TWI367487B (en) 2012-07-01

Family

ID=38456554

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096111973A TWI367487B (en) 2006-04-05 2007-04-04 Flash memory programming and verification method with reduced leakage current

Country Status (6)

Country Link
US (2) US7630253B2 (zh)
JP (1) JP2009532821A (zh)
KR (1) KR101428765B1 (zh)
CN (2) CN103971745A (zh)
TW (1) TWI367487B (zh)
WO (1) WO2007117617A1 (zh)

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TWI571883B (zh) * 2015-11-15 2017-02-21 華邦電子股份有限公司 非依電性記憶體裝置及其操作方法

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US7571287B2 (en) 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
US7768835B2 (en) * 2006-08-09 2010-08-03 Micron Technology, Inc. Non-volatile memory erase verify
US8131915B1 (en) 2008-04-11 2012-03-06 Marvell Intentional Ltd. Modifying or overwriting data stored in flash memory
US8683085B1 (en) 2008-05-06 2014-03-25 Marvell International Ltd. USB interface configurable for host or device mode
JP5143655B2 (ja) * 2008-07-22 2013-02-13 スパンション エルエルシー 半導体装置へのデータ書き込み方法、半導体装置
US8947929B1 (en) 2008-11-06 2015-02-03 Marvell International Ltd. Flash-based soft information generation
US8213228B1 (en) * 2008-11-06 2012-07-03 Marvell International Ltd. Flash memory read performance
US8611151B1 (en) 2008-11-06 2013-12-17 Marvell International Ltd. Flash memory read performance
US8423710B1 (en) 2009-03-23 2013-04-16 Marvell International Ltd. Sequential writes to flash memory
US8213236B1 (en) 2009-04-21 2012-07-03 Marvell International Ltd. Flash memory
JP5316299B2 (ja) * 2009-08-07 2013-10-16 富士通セミコンダクター株式会社 半導体メモリ、システムおよび半導体メモリの動作方法
CN101807433B (zh) * 2010-03-10 2012-10-24 上海宏力半导体制造有限公司 一种存储器的编程方法
US8756394B1 (en) 2010-07-07 2014-06-17 Marvell International Ltd. Multi-dimension memory timing tuner
US8482987B2 (en) 2010-09-02 2013-07-09 Macronix International Co., Ltd. Method and apparatus for the erase suspend operation
US8677225B1 (en) 2011-02-11 2014-03-18 Marvell International Ltd. Low-density parity-check decoder
US8717813B2 (en) 2011-04-13 2014-05-06 Macronix International Co., Ltd. Method and apparatus for leakage suppression in flash memory in response to external commands
CN102800362B (zh) * 2011-05-26 2016-06-29 北京兆易创新科技股份有限公司 非易失存储器的过擦除处理方法和处理系统
US9396770B2 (en) 2012-02-13 2016-07-19 Macronix International Co., Ltd. Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
US8913445B2 (en) * 2012-02-13 2014-12-16 Macronix International Co., Ltd. Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
US8760923B2 (en) * 2012-08-28 2014-06-24 Freescale Semiconductor, Inc. Non-volatile memory (NVM) that uses soft programming
CN103345934B (zh) * 2013-06-03 2016-12-28 上海华虹宏力半导体制造有限公司 控制栅极电压译码电路
US9312002B2 (en) 2014-04-04 2016-04-12 Sandisk Technologies Inc. Methods for programming ReRAM devices
US10825529B2 (en) 2014-08-08 2020-11-03 Macronix International Co., Ltd. Low latency memory erase suspend operation
US9564226B1 (en) * 2015-10-30 2017-02-07 Sandisk Technologies Llc Smart verify for programming non-volatile memory
KR102369307B1 (ko) * 2015-12-02 2022-03-03 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
CN109545259B (zh) * 2018-11-28 2021-11-16 安徽大学 采用三个灵敏放大器抵抗位线泄漏电流的电路结构
US11282567B2 (en) 2019-08-20 2022-03-22 Micron Technology, Inc. Sequential SLC read optimization
US11726869B2 (en) 2019-08-20 2023-08-15 Micron Technology, Inc. Performing error control operation on memory component for garbage collection
US11281578B2 (en) 2019-08-20 2022-03-22 Micron Technology, Inc. Garbage collection in a memory sub-system during a low battery state
US11281392B2 (en) 2019-08-28 2022-03-22 Micron Technology, Inc. Garbage collection in a memory component using an adjusted parameter

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US5487033A (en) * 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS
US5835414A (en) * 1996-06-14 1998-11-10 Macronix International Co., Ltd. Page mode program, program verify, read and erase verify for floating gate memory device with low current page buffer
JP3410036B2 (ja) * 1999-02-03 2003-05-26 シャープ株式会社 不揮発性半導体記憶装置への情報の書き込み方法
US6055190A (en) * 1999-03-15 2000-04-25 Macronix International Co., Ltd. Device and method for suppressing bit line column leakage during erase verification of a memory cell
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US6339540B1 (en) 2000-12-05 2002-01-15 Tower Semiconductor Ltd. Content-addressable memory for virtual ground flash architectures
US6456533B1 (en) 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Higher program VT and faster programming rates based on improved erase methods
US6493266B1 (en) 2001-04-09 2002-12-10 Advanced Micro Devices, Inc. Soft program and soft program verify of the core cells in flash memory array
US6469939B1 (en) * 2001-05-18 2002-10-22 Advanced Micro Devices, Inc. Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process
US6525969B1 (en) 2001-08-10 2003-02-25 Advanced Micro Devices, Inc. Decoder apparatus and methods for pre-charging bit lines
US6510082B1 (en) * 2001-10-23 2003-01-21 Advanced Micro Devices, Inc. Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold
US6529412B1 (en) * 2002-01-16 2003-03-04 Advanced Micro Devices, Inc. Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
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US6795342B1 (en) * 2002-12-02 2004-09-21 Advanced Micro Devices, Inc. System for programming a non-volatile memory cell
US6956768B2 (en) 2003-04-15 2005-10-18 Advanced Micro Devices, Inc. Method of programming dual cell memory device to store multiple data states per cell
US6868014B1 (en) 2003-05-06 2005-03-15 Advanced Micro Devices, Inc. Memory device with reduced operating voltage having dielectric stack
US6862221B1 (en) 2003-06-11 2005-03-01 Advanced Micro Devices, Inc. Memory device having a thin top dielectric and method of erasing same
US6937520B2 (en) * 2004-01-21 2005-08-30 Tsuyoshi Ono Nonvolatile semiconductor memory device
US7307888B2 (en) * 2004-09-09 2007-12-11 Macronix International Co., Ltd. Method and apparatus for operating nonvolatile memory in a parallel arrangement
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US7200045B2 (en) * 2004-12-30 2007-04-03 Macronix International Company, Ltd. Method for programming a charge-trapping nonvolatile memory cell by raised-Vs channel initialed secondary electron injection (CHISEL)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI571883B (zh) * 2015-11-15 2017-02-21 華邦電子股份有限公司 非依電性記憶體裝置及其操作方法

Also Published As

Publication number Publication date
TW200805380A (en) 2008-01-16
US7630253B2 (en) 2009-12-08
US8031528B2 (en) 2011-10-04
US20070237003A1 (en) 2007-10-11
CN103971745A (zh) 2014-08-06
US20100027350A1 (en) 2010-02-04
JP2009532821A (ja) 2009-09-10
KR101428765B1 (ko) 2014-08-08
CN101438352B (zh) 2014-06-04
WO2007117617A1 (en) 2007-10-18
CN101438352A (zh) 2009-05-20
KR20090033828A (ko) 2009-04-06

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees