TWI361433B - Operating method of memory - Google Patents

Description

1361433 P960132 2561 ltwf.doc/ρ IX. Description of the invention: [Technical field of the invention] The present invention has an operation method of _-radio erasing and the like, and particularly relates to the inverse of the type # " β heart Or just nor) Wei Yi II's operation ^. Vlrtual-ground) [prior art]

Can be erased electrically and can be used only for bribery

2 Non-volatile memory that enters, reads, or erases (4) and saves the data of the depositor after the power is turned off. It can be erased electrically and can be read in the program-only read memory. The typical one is flash, _. The charge trapped layer memory is an electrically erasable and programmable read-only memory that is nitrided to replace the typical (four) memory doped polysilicon floating gate. (4) The charge trapping layer of the charge trapping layer is usually nitrogen cut, and the nitride nitride trap layer usually has a layer of oxygen cut, and the control gate and the material of the substrate are usually multi (four) cut. Therefore, such an element is commonly known as the Shi Xi / Emulsified Shi Xi / Nitride Xi / Oxide / Shi Xi (SON 〇 s) elements. Since the electrons in the nitride trapping electron trapping layer are concentrated on the local region of the charge trapping layer, the neon towel approaching and the polar region and the region close to the source can be separately stored. One bit, therefore, such a memory cell is a memory element with two bits per memory cell. In the operation of a typical SONOS memory, a single memory cell is selected to apply a bias voltage to the word line corresponding to the control gate of the selected single-memory cell and apply it to the bit line corresponding to the drain. Bias, while the other 5 1361433 P960132 25611twf.doc/p character lines are applied with 0 volts of thunder. 4 @ H electric stems' other bit lines are applied with a voltage of 0 volts or oceanic, so that Lei; bucket, two A2 tweezer or hole injected into the tantalum nitride layer close to the pole, change the starting voltage type to carry out the stylization method is quite a kind of cell writing, when reading Wrong _ consumption 5 彡 '. Moreover, the distribution of the initial electricity (four) is smaller than that of the [invention]. The invention is to provide a short program time for the operation of the memory. /, J can make the various inventions provide the method of operation, and the distribution of the starting voltage of the material state is narrow. The invention proposes a method for operating a memory. A memory cell-shaped fibroblast _, each (four) county includes: a second sputum. The operation method includes selecting a memory cell row, and a plurality of memory cells corresponding to the memory cell row, so that a 7L of the memory cell brother reaches a predetermined stylized state. According to the embodiment of the present invention, in the method for operating the memory, when the memory cell corresponding to the memory cell row is performed, the plurality of word lines of the memory cell corresponding to the memory cell row are simultaneously applied. Pre-targeted. According to an embodiment of the invention, in the method of operating the memory, the predetermined stylized state is a plurality of different starting voltage division/distribution states. According to the embodiment of the present invention, in the above-mentioned memory operation method 1136143 P960132 25611twf.doc/p, in the memory corresponding to the selected memory cell row, when the cell is hidden, the selected memory cell of the disk The second bit of the memory cell adjacent to the memory cell and sharing the same bit line simultaneously reaches a plurality of useless states, and the memory cells of each of the useless bears and the adjacent selected memory cell row The stylized state of a ^2 is the same. According to the embodiment of the present invention, in the above method for operating a memory, the first bit is a useful bit; the second bit is a useless bit. According to the embodiment of the present invention, the method for operating the memory further includes: reading only the selected state of the first bit of the memory cell during reading, and not reading the selected one. The useless use of the memory cell is performed according to the present invention. In the above method of operating the memory, in the above-mentioned stylization, a hole is induced by inducing a one-sided bias convergence effect. Selected in the memory cells of the above memory cells. ~

According to an embodiment of the invention, the method for operating the memory further comprises inducing electrons to be injected into the above-mentioned memory by inducing a double-sided bias electron injection effect or a Fowler-Nordheim electron follow-up effect during erasing. In each memory cell of the cell array. According to the embodiment of the present invention, in the above method of operating the memory, the above-mentioned stylization is performed by inducing a unilateral bias convergence effect to cause electrons to be injected into the memory of the selected memory cell. In the cell. According to the embodiment of the present invention, the method for operating the memory includes the method of inducing a double-sided dust hole to inject a human deer, a valence band-guide band wear, and an electric brewing effect. The electron cell is injected into each of the memory cells of the above-mentioned memory cell array of P960132 25611 twf.doc/p. According to the embodiment of the present invention, the memory cell is a multi-order memory cell. According to the present invention, in the operation method of the memory described above, 'the above memory cell array is a virtual ground (virtual_gr. thyristor memory cell array. ^ Implementation of the tactile according to the present invention, ± description of the operation of the memory) In the method, the memory cell is programmed in a column-by-column manner. The invention further provides a method for operating a memory, the memory comprising a memory cell array composed of a plurality of memory cells. The operation method includes: 'The memory of the same column connected to the same bit line is broken. i. According to the implementation of the present invention, in the above-mentioned method of recording, in the process of performing various morphing, at the same time in the selected memory cell OK The plurality of word lines corresponding to the cell are applied with a plurality of predetermined bias voltages. According to the method for operating the memory device, the memory cell array is a virtual grounded anti- or memory cell array. According to the embodiment of the present invention, the method for operating the memory t' is that the memory cell is a multi-level memory cell. According to the embodiment of the present invention, in the method for operating the memory, the one selected in the memory is selected. When the memory cells of the memory cell are programmed, a plurality of predetermined bias voltages are applied to the plurality of word lines corresponding to the memory cells of the selected memory cell. According to the embodiment of the present invention, the memory is as described above. In the method of operation 1614433 P960132 25611twf.doc/p, when a memory cell of a selected memory cell is programmed, the unilateral bias convergence effect is induced to cause the hole to be injected into the selected one. In the memory cell of the above memory cell, according to the embodiment of the present invention, in the operation method of the memory device, when the memory cell of a selected memory cell is programmed, the unilateral bias is induced. Pressure a method of operating the memory of the embodiment of the present invention, which can shorten the stylization time. The above and other objects, features and advantages of the present invention will become more apparent and obvious. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment] Fig. 1 is a circuit diagram showing a memory used in the operating method of the present invention. Fig. 2 is a schematic cross-sectional view showing a structure of a conventional memory cell used in the method of operation of the present invention. Ming References 1 and 2, the clock of the invention includes a memory cell array composed of a plurality of: cryptocytes 10. The memory cell array is, for example, a virtual grounded inverse or gate type memory composed of multiple = singular memory cells (MLC). 2, two vertical lines Inmn, ^ sigma words WLn_i, WLn+1, WLn+2 ...Wait. Each memory 1361433 P960132 iseiltwldoc/p cell includes a control gate 12, an electrical, and a source/drain region 22. In this layer 16, the source/no-polar area is the source area, which means that it can be used as the source area in the direction of -, claw, and movement, or as the source of the pole / 与 = 20 and source / 汲The polar region 22 is disposed on the substrate; 4: two. ί;: the trapping layer 16 is disposed on the control gate 12 and the substrate 14

Acoustic 6 L6 is a dielectric layer, such as a nitrogen cut layer. The charge is trapped Ϊ ίί top includes a layer through the dielectric layer 18.遂 遂 曰 曰 曰 曰 曰 ί ί ί ί ί 如 如 如 如 如 如 如The control gate 12 and the charge trapping layer are 匕 Γ 1 Λ dielectric layer 15. The material of the dielectric layer 15 is, for example, oxygen which is trapped in the layer 16 as a dielectric layer, so that the injected electrons can be confined to a specific region. Therefore, when stylized, the knife can be approached. The area 30 of the source/no-polar region 20 or the region 4G close to the source/no-polar region 22 stores the data state. However, in the embodiment of the present invention, the charge trapping layer 接近6 is close to the _/secret region 2 (four) region% is the data bit actually used to store the lean material; and the region 4 接近 close to the source/drain region 22 is the useless bit. yuan. In the memory cell array, memory cells Al, a2, and a3; memory cells & B2, B3' memory cells Q, C2, c3, and memory cells, D3 are arranged in a row. Memory cells Al, Bl, Q, Di; memory cells A2, B2, G, D2; memory cells a3, b3, c3, d3 are arranged in a column. The source/drain region of each memory cell and the source/drain region of the memory cells of the same strong and adjacent memory cells and which are connected by the bit line BL 20. For example, the source/drain region 2〇 of the memory cell Ci (S > 10 1361433 P960132 25611twf.doc/p ' is shared with the source/potential region 22 of the memory cell B1, and is privately connected by the bit line. In conjunction with the memory cell C2, C; 3 source / immersion zone 20. In addition, in the memory cell array '(4), the control side of the memory cell 12 corresponds to the same - word / element line WL ' The control gates 12 of the read cells A!, c, and Di correspond to the same word line WLw. When the memory is erased, all the memory cells 10 are biased 'to make all the memory cells 10 data bit 30 and useless bit 40 Lulang reference g. When stylized, the data bits of the same row of memory cells are simultaneously programmed. When reading, 贞彳 is only The stylized state of the data bit 30 of the t-selected memory cell is read, and the unused bit 40 of the selected k cell is not read. The memory cell of the present invention can be distinguished according to the magnitude of the starting voltage. A plurality of states. Referring to FIG. 3, in an embodiment, the memory cell 10 can be divided into four states according to the size of its starting voltage distribution, from large to The small order is (〇...state, (01) state, (1〇) state, and (11) state. In one embodiment of the present invention, the (00) state with the highest starting voltage is the reference state. And reprogramming to a lower (〇1) state, a (10) sorrow or (11) state, in another embodiment of the present invention, the lowest (11) state of the starting voltage is set as The reference state is reprogrammed to the (10) state, the (01) state, or the (00) state where the starting voltage is high. For the first example, please refer to FIGS. 4A and 4B, and when erasing, it is for the memory cell. All of the memory cells 10 of the array are biased such that the data bits 30 and the unused bits 40 of all the memory cells reach the reference state of the highest starting voltage 1136143 P960132 25611 twf.doc/p (〇〇). Referring to FIG. 4A', in an embodiment, when the erasing is performed, the double-bias (Double Side Bias, DSB) electron injection effect is induced to raise the starting voltage of all the memory cells 10. The method is to apply a volt volt to the substrate 14 and apply 1 〇 to 15 volts across all of the word lines WLm 疋 WLn, WLn+1. Voltage, and applying a voltage of 5 to 7 volts across all of the bit lines BLn_2, BLn-丨, BLn, BLn_n, BLn+2 to inject and trap electrons in the charge storage layer 16, causing the data bit 30 And the useless bit 40 reaches the (〇〇) state. Referring to the figure, in another embodiment, by performing the erase, the F穿wler_N〇rdhdm electron tunneling effect is induced to make all the memory cells The starting voltage of 1〇 rises. The method of operation is to apply a voltage of 0 volts to the substrate 14, and apply a voltage of 16 to 20 volts across all of the word lines, WLn, WLn+, and at all of the bit lines BLn_2, BLw, BLn, BLn+1, BLn. +2 applies a voltage of 0 volts to cause electrons to be injected and trapped in the charge storage layer 16, so that both the tributary bit 30 and the useless bit 4 达到 reach the (〇〇) state. When stylized, the selected memory cell 10 has its source /; and the bit line corresponding to the polar region 20 has a voltage difference between its bit line and its adjacent word line. Appropriate voltage is applied, for example, -2 to 2 volts 'by inducing a single side bias (SSB) convergence effect' to program the data bits 30 of the memory cell 10 of the peer to a lower starting voltage (〇1) state, (10) state, or (11) state. The following describes the simultaneous memory cell, D2, and D3. Referring to FIG. 5, it is assumed that the predetermined stylized states of the memory cell D, the memory cell D2, and the memory cell 3 are (01) state, (10) state, and (11) 12 < S ) 1361433 P960132 25611 twf.doc /p . Status. When staging the memory cells D!, D2, D3 of the same row, a voltage of 0 volts is applied to the substrate 14 and a voltage of 4 to 8 volts is applied to the bit line BLn+1, in the adjacent bits. The lines BLn+2 and BLn apply the same voltage. For example, the voltage of 〇volts or both are floated so that BLn+1 and BLn+2 generate a voltage difference between each other and make BLn+1 and BLn They create a pressure difference between each other. The other bit lines BLn ! and Bju are floating. Further, voltages of, for example, I·2 volts, 〇.2 volts, and -1.0 volts are applied to the word lines WLn], WLn, and WLn+i, respectively. Under this operating condition, the thermoelectric holes generated by the memory cell D, the memory cell, and the source/no-polar region 20 junction of the memory cell d3 will move toward the substrate 14, and, due to the ionization effect, will generate many Electronic hole pair. The hole in the electron hole pair will be injected into the charge storage layer 16 due to the attraction of a large amount of electrons in the data bit 30 of the memory cell Di, A of the reference state, so that the data bit 3〇 The starting voltage converges from the high starting voltage to the lower starting voltage', so that the memory cell Di, the memory cell, and the data bit of the memory cell A reach the (〇1) state, the (1〇) state, and Ϊ́ι) _ 'state' as shown in Figure 6. When the memory cells D1, D2, and A of the same row are stylized, the source/drain regions 20 of the memory cells D, D2, 1 > 3 and the sources/汲 of the adjacent memory cells q, C2, and A, respectively. The polar regions 22 share and are each connected to the bit line BLn+i, and the phase bit line BLn is also applied with a voltage of volts or floating, that is, between the bit line BLn+1 and the bit line BLn. The voltage difference is the same as the difference between the bit line BLn+1 and the bit line +2 (4), therefore, the memory cell a, . The source/noodle region 22 of the cryptic cell C2 and the singular cell C3 will also generate thermoelectricity <S) 13 1361433 P960132 2561 ltwf.doc/p • The hole will move toward the substrate 14, and is ionized The role will also be produced. Many pairs of electronic holes. The holes in the electron hole pair will also be injected into the charge storage layer 16 due to the attraction of a large amount of electrons in the memory cells C of the reference state, C2, and the useless bits of the charge storage layer 16 of C3. The start voltage of the useless bit 70 40 converges from the high start voltage to the lower start voltage, and the memory cell c, the memory cell a, and the useless bit 4 of the memory cell C3 also reach the (01) state, (1〇) state and (11) state. • Using the same method, the memory cells 10 of the same line can be simultaneously processed line by line so that the data bit 30 and the useless bit 4 〇 reach the (〇1) state, the (1〇) state, or the (11) state. & 〃 Although 'in the present invention', after the stylization, the memory cell data bit 7L 3G and the useless bit 4〇 are all in a stylized state (〇1), a (1〇) state or (11) status. However, only the state stored in the data bit 3 is used as the data state; and the state stored in the unused bit 4 is the useless state. Therefore, when reading is performed, only the private state of the data bit 30 of the selected memory cell is read, and the useless state of the selected memory cell 40 is not read. Referring to FIG. 7, when reading the tributary state of the data bit 3〇1 of the selected memory cell 2, a voltage of 3 volts can be applied to the word line WLn corresponding to the control gate 12 of the memory cell. And applying a voltage of volts volts to the other word lines WLw and WLn+1, and applying a voltage of 16 volts to the bit line BLn+2 corresponding to the gate/nomogram area 22 of the memory cell, while others Bit lines BLn+1, BLn, BLw, BLn· are applied. Volt voltage. The data state of the memory cell data bit < S ) 14 1361433 P960132 25611twf.doc/p 30 is determined by the magnitude of the current read. Embodiment 2 Referring to FIG. 8A and FIG. 8B, in the erasing, all the memory cells 1G of the memory cell array are tested, so that the data bits of all the memory cells are 兀3〇 and the useless bits are reached. The reference state with the lowest starting voltage is the (11) state. Referring to Figure 8A, in one embodiment, the DSB hole injection effect is induced by erasing to cause the threshold voltage τ of all memory cells to drop. (10) Greening is to apply a Q volt voltage to the substrate 14, and apply a voltage of -10 to _15 volts across all of the word lines WLn·丨, WLn, ^\〇^+1, and at all bit lines BLn 2 , BLn", BLn, BLn+1, BLn+2 apply a voltage of 5 to 7 volts to inject the hole and sink into the charge storage layer 16, so that the data bit 3G and the useless bit 4 are both 1 ( Ii) Status. Referring to FIG. 8B, in another embodiment, the erbium is performed by inducing a BAND TO BAND HATHOLE 'BTBHH injection effect to make all the memory cells 〇 The starting voltage drops. The method of operation is to apply a voltage of volts to the substrate 14 and apply a voltage of -16 to _20 volts across all of the word lines WLw, WLn, WLn+1 and at all of the bit lines BLn.2, BLn], BLn, BLn+1, BLn+2% are applied to the voltage of the volts so that the holes are implanted and trapped in the charge storage layer 16 to bring the data bit 30 and the useless bit 40 to the (11) state. When the program is programmed, the voltage is generated between the selected cell line 1 and the bit line corresponding to the source region 20 and its adjacent bit line and simultaneously applied to all the word lines. The appropriate voltage is, for example, -2 to <-S) 15 1361433 P960132 25611twf.doc/p 2 volts' by inducing the SSB convergence effect so that the data bits 30 of the memory cell of the peer are programmed into the starting voltage. A higher (10) state, a (01) state, or a (〇〇) state. The following is a description of the simultaneous stylized memory cells D!, D2, and d3. Referring to Fig. 9, it is assumed that the predetermined stylized states of the memory cell Di, the memory cell, and the memory cell 3 are (〇〇) state, (01) state, and (11) state, respectively. When the memory cells Di, D2, d3 are programmed, 'the volts voltage is applied to the substrate 14, and a voltage of, for example, 4 to 8 volts is applied to the bit line BLn+1' at the adjacent bit lines BLn+2 and BLn. Applying the same voltage, for example, a voltage of 〇V or both, so that BLn+i and BLn+2 generate a voltage difference between each other, and cause BLn+1 and BLn to generate a voltage difference between each other. . The other bit lines BLn i, BLn_2 are floating. Further, voltages of, for example, 12 volts, 0.2 volts, and _1. volts are applied to the word lines WLlv1, WLn, WLn+, respectively. Under this operating condition, the thermoelectric holes generated by the source/drain regions 20 of the memory cells D, r > 2, D3 will move toward the substrate 14, and, due to the ionization, many electron holes will be generated. The electrons in the electron hole pair are injected into the charge storage layer 16 due to the attraction of a large number of holes in the charge storage layer i6 (four) level 3G of the memory cells A, h, d3 of the reference state, so that the data bits are Start power = low start voltage converges to a higher starting voltage, memory cell memory 匕 D2 and memory cell D3 data bit 3 状态 state and (10) state, as shown in Figure 1 。. _ age (called = memory cell Dl, D2, D3 'because of memory cell d}, A, 3 source / bungee region 20 and adjacent memory blisters q, C2, q source 1361433 P960132 25611twf .doc/p

Bii two materials are connected to the bit line BLn+1, and the adjacent bit line = 〇 volt is followed by floating, that is, the bit line Βΐ "1 ^ gate = the pressure difference between the two and the bit line BLn+1 is the same as the bit line, therefore, the memory cell Ci, the memory cell C2, and

The secret/secret region 22 of the cell c3 will also create a thermoelectric hole and will ionize the substrate 14 and 1 and will also produce many electron holes. The electrons in the pair of hair hole holes will also be injected into the charge storage layer 16 due to the attraction of a large number of holes in the useless cells 4 of the memory storage layer 16 of the reference state, C2, C3, The start voltage of the useless bit 40 is converged from the low start voltage to the higher start voltage, and the memory cell C1, the memory cell C2, and the useless bit 4G of the memory cell c3 will also reach the _ state and the (01) state, respectively. And (10) status. By means of the phase method, the memory cells of the peers can be programmed at the same time, so that the data bit 30 and the useless bit 4〇 reach (〇1), (1〇) state or (11) state. . ~

In the present invention, after the stylization, the data bit 30 and the useless bit 40 of the memory cell 1 are in the stylized state (〇1) state, the (10) state, or the (11) state. However, only the state stored by the data bit is used as the data state; and the state stored by the useless bit 40 is useless. Therefore, when reading is performed, only the stylized state of the selected memory cell bit 30 is read, and the useless state of the selected memory cell 40 is not read. Referring to Figure 7, when reading the data status in the data bit 3 of the selected memory cell 2, the P-switch can correspond to the control gate 12 of the memory cell 2. P960132 2561 ltwf.doc/p word The WLn is applied with a voltage of 3 volts and a voltage of 0 volts is applied to WLn+丨: the sub-line B corresponding to the drain region 22 of the sub-green WL-丨, the source of the memory cell D2/other The bit line force Β σ / · 6 volts of voltage, and the voltage. It is judged by the magnitude of the read current; === the state of the data in the element 30.程式 匕 之 之 本 本 本 本 本 本 本 本 本 本 本 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式When the β ϋΐΐΓ ΐ 心 , , , , , , , ϋΐΐΓ ϋΐΐΓ ϋΐΐΓ 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加The stylized definition of the short memory cell array has been disclosed in the preferred embodiment as described above. However, it is not intended to be used in the art, and the modification can be made without departing from the spirit of the invention. Qing, therefore, the protection of the present invention is subject to the definition of the gamut application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view showing the structure of a memory cell used in the operation method of the embodiment of the present invention. Fig. 3 is a diagram showing the relationship between various states 1361433 P960132 25611twf.doc/p and the starting voltage for a memory cell used in an embodiment of the present invention. FIG. 4A is a schematic circuit diagram of a memory device performing an erase operation by an electron injection method according to an embodiment of the invention. FIG. 4B is a circuit diagram of a memory device performing an erase operation by an electron injection method according to another embodiment of the invention. FIG. 5 is a circuit diagram showing a memory operation of a memory by a hole injection method according to an embodiment of the invention. FIG. 6 is a diagram showing a relationship between a starting voltage and a time for a memory operation by a cavity injection method according to an embodiment of the invention. FIG. 7 is a circuit diagram of a memory read operation according to an embodiment of the invention. FIG. 8A is a schematic circuit diagram of a memory device performing a erase operation by a hole injection method according to an embodiment of the invention. FIG. 8B is a circuit diagram of a memory device performing a erase operation by a hole injection method according to another embodiment of the invention. FIG. 9 is a circuit diagram showing a memory operation of a memory by an electronic injection method according to an embodiment of the invention. FIG. 10 is a diagram showing a relationship between a starting voltage and a time of a memory operation performed by an electronic injection method according to an embodiment of the invention. [Main component symbol description] 10: Memory cell 12: Control gate 14: Substrate 19 < S) 1361433 P960132 25611twf.doc/p 15 : Dielectric layer 16 : Charge storage layer 18 : Tunneling dielectric layers 20 , 22 : Source/Bungee Area 24: Channel Area 30: Data Bit 40: Useless Bit 20

Claims (1)

1361433 100-12-29 X. Patent application scope: 1. A memory operation method 'The memory includes a memory cell array composed of a plurality of memory cells, each memory cell including a first bit and a second bit The operation method includes: selecting a memory cell row, and simultaneously stabilizing the selected memory cells corresponding to the memory cell row, so that the first bit of each memory cell reaches a plurality of predetermined stylized Among the states, the predetermined stylized states are a plurality of stylized states having different starting voltage distributions. 2. The method of operating a memory according to the above-mentioned patent application, wherein when the memory cells corresponding to the memory cell row are programmed, the memory corresponding to the selected memory cell row is simultaneously The majority of the word lines of the cell apply a plurality of predetermined bias voltages. 3. The method of operating a memory according to the above-mentioned claim, wherein the memory of the selected memory cell is performed when the memory cells corresponding to the selected memory cell are programmed The second bit of the memory cells adjacent to each other and sharing the same bit line simultaneously reaches a plurality of useless states - each of the useless state and the first bit of the memory cell of the adjacent selected memory cell row Each of the predetermined stylized states is the same. 4. The method of operating a memory as described in claim 3, wherein the first bits are useful bits; and the second bits are useless bits. 5. The method for operating a memory as described in claim 3, further comprising reading only the stylized states of the first bits of the selected memory cell when reading, not reading The useless state of the I 21 100-12-29 bit of the selected memory cell is taken. 6. The method of fabricating a memory according to claim 1, wherein the staging is performed by inducing a one-sided bias convergence effect to cause a hole to be injected into the selected memory. The cells are in the memory cells. 7. The method of operation of the memory as described in claim 6 of the patent application, further includes the use of a double-sided electron injecting effect or a Fowler-Nordheim electron tunneling effect in the wire-feeding device to inject electrons into Each of the memory cells of the memory cell array. 8. The method of operating a memory according to claim 1, wherein when the hybridization is performed, the unilateral biasing effect is applied to cause electrons to be injected into the selected memory cell. Among the memory cells. 9' If the memory work method of the 8th item of the patent application scope is included, when it is erased, the (4) hair double (4) (4) venting effect, the material _ hole injection effect, when the electronic injection is in the ^ Each of the arrays is in the memory cell. The operating mode of the memory as described in claim 1, wherein the memory cells are multi-order memory cells. U. The operating side or the inter-memory of the memory described in the first paragraph of the patent application is as follows: the virtual Saki 1 financial, the anti-method, H, as in the operation of the memory described in the first item of the patent scope, The memory cells are programmed in a column-by-column manner. : 13. The operation method of the memory, the memory includes a plurality of memory cell arrays, each memory cell includes a --bit, and the 22 100-12-29 programmatically programs the memory cells, wherein the memory cells are connected The memory cells of the same bit line of the same N are simultaneously programmed such that the first bit of each of the memory cells reaches one of a plurality of predetermined stylized states, wherein the predetermined stylized states It is a stylized state with many different starting voltage distributions. The method of operating a memory according to claim 13, wherein, in performing each stylization, simultaneously applying a plurality of word lines corresponding to the memory cells of the selected one of the memory cells Most of the predetermined bias voltages. The method of operating a memory according to claim 13 wherein the 6-cell memory array is a virtual-ground reverse or gate type memory cell array. 16. The method of operating a memory according to claim 13, wherein the memory cells are multi-order memory cells. The method of operating a memory according to claim 14, wherein when the memory cells of a selected memory cell are programmed, the memory cells are selected at the same time. A plurality of predetermined word lines are applied to the plurality of word lines corresponding to the memory cells. 18. The method of operating a memory according to claim 13 wherein the memory cells of a selected memory cell are programmed by inducing a unilateral bias convergence effect. The holes are injected into the memory cells of the selected memory cell row. 19. The method of operating a memory as recited in claim 13 is to program the memory cells of a selected memory cell by inducing a unilateral bias convergence effect to cause electrons Injected into the memory cells of the Shai S. , twenty three