TWI631563B - Method to reduce program disturbs in non-volatile memory cells - Google Patents
Method to reduce program disturbs in non-volatile memory cells Download PDFInfo
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- TWI631563B TWI631563B TW103102918A TW103102918A TWI631563B TW I631563 B TWI631563 B TW I631563B TW 103102918 A TW103102918 A TW 103102918A TW 103102918 A TW103102918 A TW 103102918A TW I631563 B TWI631563 B TW I631563B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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Abstract
本發明提供一種非揮發記憶體以及操作其之方法,用以減少干擾。於其中一實施例中,該方法包含:耦合一第一正高電壓至一記憶體單元之陣列的一第一列中的一第一總體字元線以及耦合一第二負高電壓(VNEG)至該陣列的一第一行中的一第一位元線用以施加一偏壓至一選定記憶體單元中的一非揮發記憶體電晶體,以便程式化該選定記憶體單元;一大小小於VNEG的邊限電壓會被耦合至該陣列的一第二列中的一第二總體字元線以及一禁止電壓會被耦合至該陣列的一第二行中的一第二位元線用以降低被施加至一未被選定記憶體單元中的一非揮發記憶體電晶體的偏壓,以便減少因程式化的關係所造成之被程式化在該未被選定記憶體單元中的資料的程式干擾。 The invention provides a non-volatile memory and a method for operating the same to reduce interference. In one embodiment, the method includes coupling a first positive high voltage to a first overall word line in a first column of an array of memory cells and coupling a second negative high voltage (V NEG ). A first bit line in a first row of the array is used to apply a bias voltage to a non-volatile memory transistor in a selected memory cell in order to program the selected memory cell; a size smaller than The marginal voltage of VNEG will be coupled to a second overall word line in a second column of the array and a forbidden voltage will be coupled to a second bit line in a second row of the array for A program to reduce the bias voltage applied to a non-volatile memory transistor in an unselected memory cell, so as to reduce the program of data programmed in the unselected memory cell due to the stylized relationship. interference.
Description
本揭示內容大體上和記憶體裝置有關,且更明確地說,和減少在非揮發記憶體單元中的程式干擾的方法有關。 This disclosure relates generally to memory devices, and more specifically, to methods for reducing programmatic interference in non-volatile memory cells.
本申請案在35 U.S.C.119(e)的規範下主張2013年3月12日提申的美國臨時專利申請案序號第61/778,136號的優先權權利,本文以引用的方式將其併入。 This application claims the priority right of US Provisional Patent Application No. 61 / 778,136 filed on March 12, 2013 under the specification of 35 U.S.C.119 (e), which is incorporated herein by reference.
非揮發記憶體廣泛用於在電腦系統中儲存資料,並且通常包含一具有行列排列之大量記憶體單元的記憶體陣列。該記憶體單元中的每一者皆包含一非揮發電荷陷捕閘極場效電晶體,其會藉由在一控制閘極與基板之間施加正確極性、大小以及時間持續長度的電壓而被程式化或被抹除。一正閘極至基板電壓會導致電子從通道處隧穿至一電荷陷捕介電層,從而提升電晶體的臨界電壓(VT);一負閘極至通道電壓會導致電洞從通道處隧穿至該電荷陷捕介電層,從而降低該臨界電壓。 Non-volatile memory is widely used to store data in computer systems, and usually includes a memory array with a large number of memory cells arranged in rows and columns. Each of the memory cells contains a non-volatile charge trapping gate field effect transistor, which is applied by applying a voltage of the correct polarity, size, and duration to a control gate and the substrate. Stylized or erased. A positive gate-to-substrate voltage will cause electrons to tunnel from the channel to a charge-trapping dielectric layer, thereby increasing the critical voltage (V T ) of the transistor; a negative gate-to-channel voltage will cause holes to pass from the channel Tunneling to the charge-trapping dielectric layer reduces the threshold voltage.
非揮發記憶體有程式或位元線干擾的問題,其會在被連接至相同位元線的另一記憶體單元禁止被程式化時,非預期且不利的改變記憶 體單元VT。位元線干擾指記憶體單元的干擾,其位在和含有正在進行程式化之單元的列不同的列之中。發生在已解選列中的位元線干擾會隨著共同井部中被選定列中的抹除/程式化循環次數增加而增加。位元線干擾的大小還會在較高溫度處提高,而且因為記憶體單元維度縮小速度快過先進技術節點處的外加電壓,所以當非揮發記憶體的密度提高時,位元線干擾也會變得更差。 Non-volatile memory has a problem of program or bit line interference. When a memory unit connected to the same bit line is prohibited from being programmed, the memory unit V T is changed unexpectedly and unfavorably. Bit line interference refers to the interference of memory cells, which is located in a different row from the row containing the cells being programmed. The bit line interference that occurs in the deselected row increases with the number of erase / stylize cycles in the selected row in the common well. The size of the bit line interference will also increase at higher temperatures, and because the dimensions of the memory cell shrink faster than the applied voltage at the advanced technology node, when the density of non-volatile memory increases, the bit line interference will also increase. Getting worse.
所以,本發明的目的便係提供改良的非揮發記憶體以及程式化其之方法。 Therefore, the object of the present invention is to provide an improved non-volatile memory and a method for programming it.
本發明的一項觀點係一種方法,其包括:耦合一第一正高電壓(VPOS)至記憶體單元之一記憶體陣列的一第一列中的一第一總體字元線以及耦合一第二負高電壓(VNEG)至該記憶體陣列的一第一行中的一第一位元線用以施加一偏壓至一選定記憶體單元中的一非揮發記憶體電晶體,以便程式化該選定記憶體單元;以及耦合一大小小於VNEG的邊限電壓至該記憶體陣列的一第二列中的一第二總體字元線以及耦合一禁止電壓(VINHIB)至該記憶體陣列的一第二行中的一第二位元線用以降低被施加至一未被選定記憶體單元中的一非揮發記憶體電晶體的偏壓,以便減少因該選定記憶體單元之程式化的關係所造成之被程式化在該未被選定記憶體單元中的資料的程式干擾。 An aspect of the present invention is a method comprising: coupling a first positive high voltage (VPOS) to a first overall word line in a first column of a memory array of a memory cell; and coupling a second A negative high voltage (VNEG) to a first bit line in a first row of the memory array is used to apply a bias voltage to a non-volatile memory transistor in a selected memory cell in order to program the Selecting a memory cell; and coupling a marginal voltage smaller than VNEG to a second overall word line in a second column of the memory array and coupling a prohibition voltage (VINHIB) to a first A second bit line in the two rows is used to reduce the bias voltage applied to a non-volatile memory transistor in an unselected memory cell in order to reduce the effect of the programmed relationship of the selected memory cell. Caused by the program interference of the data programmed in the unselected memory unit.
本發明的另一項觀點係一種方法,其包括:耦合一第一高電壓(HV)至記憶體單元之一記憶體陣列的一第一列中的一第一總體字元線以及耦合一極性反向於該第一HV的第二HV至該記憶體陣列的一第一行中的 一第一位元線用以施加一偏壓至一選定記憶體單元中的一非揮發記憶體電晶體,以便程式化該選定記憶體單元;以及耦合一大小小於該第二HV的邊限電壓至該記憶體陣列的一第二列中的一第二總體字元線以及耦合一禁止電壓至該記憶體陣列的一第二行中的一第二位元線用以降低被施加至一未被選定記憶體單元中的一非揮發記憶體電晶體的偏壓,以便減少因該選定記憶體單元之程式化的關係所造成之被程式化在該未被選定記憶體單元中的資料的程式干擾。 Another aspect of the present invention is a method, comprising: coupling a first high voltage (HV) to a first overall word line in a first column of a memory array of a memory cell; and coupling a polarity A second HV opposite to the first HV to a first row in the memory array A first bit line for applying a bias voltage to a non-volatile memory transistor in a selected memory cell to program the selected memory cell; and coupling a marginal voltage smaller than the second HV A second overall word line in a second column of the memory array and a second bit line in a second row of the memory array coupled to a forbidden voltage are used to reduce the The bias of a non-volatile memory transistor in the selected memory cell in order to reduce the program of data programmed in the unselected memory cell caused by the programmed relationship of the selected memory cell interference.
本發明的另一項觀點係一種方法,其包括:耦合一第一高電壓(HV)至記憶體單元之一記憶體陣列的一第一列中的一第一總體字元線以及耦合一極性反向於該第一HV的第二HV至該記憶體陣列的一第一行中的一第一共享位元線用以施加一偏壓至一選定記憶體單元中的一非揮發記憶體電晶體,以便程式化該選定記憶體單元;耦合該第二HV至該記憶體陣列的一第二列中的一第二總體字元線維持一段時間用以施加一偏壓至該記憶體陣列的第一行和第二列中的一第一未被選定記憶體單元中的一非揮發記憶體電晶體,該記憶體陣列和該選定記憶體單元共享該第一共享位元線,以便減少該第一未被選定記憶體單元中的抹除狀態位元線干擾;以及經由一切換電路耦合一大小小於該第二HV的邊限電壓至該第二總體字元線,該切換電路被配置成用以在該第二HV與該邊限電壓之間切換該第二總體字元線,以及耦合一禁止電壓至該記憶體陣列的一第二行中的一第二位元線用以降低被施加至一第二未被選定記憶體單元中的一非揮發記憶體電晶體的偏壓,以便減少因該選定記憶體單元之程式化的關係所造成之被程式化在該第二未被選定記憶體單元中的資料的程式干擾。 Another aspect of the present invention is a method, comprising: coupling a first high voltage (HV) to a first overall word line in a first column of a memory array of a memory cell; and coupling a polarity A second HV opposite to the first HV to a first shared bit line in a first row of the memory array is used to apply a bias voltage to a non-volatile memory cell in a selected memory cell. Crystal to program the selected memory cell; coupling a second HV to a second global word line in a second column of the memory array for a period of time for applying a bias voltage to the memory array A non-volatile memory transistor in a first unselected memory cell in the first row and second column, the memory array and the selected memory cell share the first shared bit line to reduce the The first unselected memory bit line interference in the selected memory cell; and coupling a marginal voltage smaller than the second HV to the second overall word line via a switching circuit, the switching circuit is configured to Between the second HV and the threshold voltage Switching the second global word line, and coupling a forbidden voltage to a second bit line in a second row of the memory array to reduce a voltage applied to a second unselected memory cell The non-volatile memory transistor is biased in order to reduce program interference of data programmed in the second unselected memory unit caused by the programmed relationship of the selected memory unit.
100‧‧‧矽-氧化物-氮化物-氧化物-矽(SONOS)裝置/浮接閘極MOS場效電晶體(FGMOS)裝置 100‧‧‧Silicon-oxide-nitride-oxide-silicon (SONOS) device / Floating gate MOS field effect transistor (FGMOS) device
102‧‧‧閘極堆疊 102‧‧‧Gate stack
104‧‧‧基板 104‧‧‧ substrate
106‧‧‧源極/汲極區 106‧‧‧Source / Drain Region
108‧‧‧井部 108‧‧‧ Well
110‧‧‧通道區 110‧‧‧passage zone
112‧‧‧隧穿介電層 112‧‧‧ Tunneling Dielectric Layer
114‧‧‧電荷陷捕層/浮接閘極層 114‧‧‧Charge trap layer / floating gate layer
116‧‧‧頂端阻隔氧化物層/阻隔氧化物層或頂端介電層 116‧‧‧Top barrier oxide layer / barrier oxide layer or top dielectric layer
118‧‧‧控制閘極 118‧‧‧Control gate
200‧‧‧記憶體單元 200‧‧‧Memory Unit
202‧‧‧非揮發記憶體電晶體 202‧‧‧Non-volatile memory transistor
204‧‧‧傳導或選擇電晶體 204‧‧‧Conducting or selecting transistor
206‧‧‧共用基板連接 206‧‧‧Common substrate connection
208‧‧‧電荷陷捕層 208‧‧‧charge trapping layer
210‧‧‧汲極 210‧‧‧ Drain
212‧‧‧位元線 212‧‧‧bit line
214‧‧‧控制閘極 214‧‧‧Control gate
216‧‧‧字元線 216‧‧‧Character line
218‧‧‧源極 218‧‧‧Source
220‧‧‧汲極 220‧‧‧ Drain
222‧‧‧源極 222‧‧‧Source
224‧‧‧源極線 224‧‧‧Source Line
226‧‧‧閘極 226‧‧‧Gate
228‧‧‧選擇或讀取線 228‧‧‧Select or read line
300‧‧‧記憶體陣列 300‧‧‧Memory Array
301‧‧‧記憶體單元 301‧‧‧Memory Unit
302‧‧‧記憶體單元 302‧‧‧Memory Unit
303‧‧‧記憶體單元 303‧‧‧Memory Unit
304‧‧‧記憶體單元 304‧‧‧Memory Unit
402‧‧‧正第一高電壓(VPOS) 402‧‧‧Positive First High Voltage (V POS )
404‧‧‧負第二高電壓(VNEG) 404‧‧‧Negative second highest voltage (V NEG )
406‧‧‧中間邊限電壓(VMARG) 406‧‧‧Intermediate margin voltage (V MARG )
502‧‧‧選定總體字元線(VSELECTED WL) 502‧‧‧V SELECTED WL
504‧‧‧解選總體字元線(VDESELECTED GWL) 504‧‧‧V DESELECTED GWL
506‧‧‧切換時間 506‧‧‧ Switch time
600‧‧‧處理系統 600‧‧‧treatment system
602‧‧‧非揮發記憶體 602‧‧‧Non-volatile memory
604‧‧‧處理器 604‧‧‧Processor
606‧‧‧位址匯流排 606‧‧‧Address Bus
608‧‧‧資料匯流排 608‧‧‧Data Bus
610‧‧‧控制匯流排 610‧‧‧Control bus
612‧‧‧記憶體陣列 612‧‧‧Memory Array
614‧‧‧列解碼器 614‧‧‧column decoder
616‧‧‧字元線與讀取線 616‧‧‧Character lines and read lines
618‧‧‧行解碼器 618‧‧‧line decoder
620‧‧‧位元線與源極線 620‧‧‧bit line and source line
622‧‧‧感測放大器 622‧‧‧Sense Amplifier
624‧‧‧命令與控制電路系統 624‧‧‧command and control circuit system
626‧‧‧電壓控制電路系統 626‧‧‧Voltage control circuit system
628‧‧‧邊限模式DAC 628‧‧‧Boundary Mode DAC
700‧‧‧命令與控制電路系統 700‧‧‧ command and control circuit system
702‧‧‧負HV供應器或負泵 702‧‧‧ negative HV supply or negative pump
704‧‧‧數位至類比轉換器(DAC) 704‧‧‧ Digital-to-Analog Converter (DAC)
706‧‧‧切換電路 706‧‧‧switching circuit
708‧‧‧第二電荷泵 708‧‧‧Second Charge Pump
710‧‧‧分壓器 710‧‧‧Voltage Divider
802‧‧‧步驟 802‧‧‧step
804‧‧‧步驟 804‧‧‧step
806‧‧‧步驟 806‧‧‧step
808‧‧‧步驟 808‧‧‧step
810‧‧‧步驟 810‧‧‧step
812‧‧‧步驟 812‧‧‧step
814‧‧‧步驟 814‧‧‧step
從後面的詳細說明以及從隨附圖式與下面所提供的附屬的申請專利範圍中會更完整瞭解本發明,其中:圖1所示的係非揮發記憶體電晶體或裝置的剖視側面圖;圖2所示的係特別適用本揭示內容一實施例的雙電晶體(2T)記憶體單元的示意圖;圖3所示的係一記憶體陣列的一區段的示意圖,其例示根據本揭示內容的一程式化作業的實施例;圖4所示的係根據本揭示內容一實施例的正高電壓(VPOS)、負高電壓(VNEG)、以及一中間邊限電壓(VMARG)的曲線圖;圖5所示的係根據本揭示內容一實施例的程式化作業期間被施加至一選定總體字元線(VSELECTED WL)與一解選總體字元線(VDESELECTED GWL)的電壓的曲線圖;圖6所示的係根據本揭示內容一實施例之包含一記憶體裝置的處理系統的方塊圖;圖7A至7C所示的係根據本揭示內容多個實施例的一非揮發記憶體的命令與控制電路系統之細節的方塊圖;以及圖8所示的係根據本揭示內容一實施例用以減少未被選定記憶體單元中的位元線干擾的方法的流程圖。 The present invention will be more fully understood from the detailed description below and from the accompanying drawings and the scope of the attached patent application provided below, wherein: a sectional side view of a non-volatile memory transistor or device shown in FIG. 1 ; FIG. 2 is a schematic diagram of a dual electric transistor (2T) memory cell particularly suitable for an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a section of a memory array, which illustrates an example according to the present disclosure. An example of a stylized operation of the content; FIG. 4 shows the positive high voltage (V POS ), negative high voltage (V NEG ), and an intermediate margin voltage (V MARG ) according to an embodiment of the present disclosure. Graph; FIG. 5 shows the voltage applied to a selected global word line (V SELECTED WL ) and a deselected global word line (V DESELECTED GWL ) during a stylized operation according to an embodiment of the present disclosure. FIG. 6 is a block diagram of a processing system including a memory device according to an embodiment of the present disclosure shown in FIG. 6; FIG. 7A to 7C are a non-volatile according to various embodiments of the present disclosure. Command and control circuit The details of the block diagram; and system shown in FIG. 8 according to the present disclosure a flowchart for a method of reducing interference bit line memory cell is not selected in the embodiment.
本文中說明用以減少非揮發記憶體中的程式干擾的方法。該方法特別適用於操作由多個位元單元或記憶體單元組成的記憶體陣列製成 的記憶體,其包含可藉由施加正確極性、大小、以及時間持續長度的電壓而被程式化或被抹除的非揮發陷捕電荷半導體裝置。 This article describes methods to reduce program interference in non-volatile memory. The method is particularly suitable for operating a memory array made up of multiple bit units or memory units , Which contains a non-volatile trapped charge semiconductor device that can be programmed or erased by applying a voltage of the correct polarity, size, and duration of time.
於下面的說明中,為達解釋之目的,許多明確細節會被提出以便對本發明有透澈的瞭解。然而,熟習本技術的人士便會明白,沒有此些明確細節仍可實行本發明。於其它實例中,眾所熟知的結構與技術並不會被詳細顯示或者僅以方塊圖的形式來顯示,以避免不必要的混淆對本說明的瞭解。 In the following description, for the purpose of explanation, many specific details will be presented in order to have a clear understanding of the present invention. However, those skilled in the art will appreciate that the invention can be practiced without these specific details. In other examples, the well-known structures and technologies are not shown in detail or only in the form of block diagrams to avoid unnecessary confusion in understanding this description.
說明中引用到「其中一實施例」(“one embodiment”)或是「一實施例」(“an embodiment”)的意義為配合該實施例所述的特殊特點、結構、或是特徵包含在本發明的至少其中一個實施例中。出現在說明書中各個地方的「於其中一實施例中」(“in one embodiment”)一詞未必全部表示相同實施例。本文中所使用之耦合(couple)一語可以包含直接電連接二或更多個器件或元件以及經由中間器件來間接連接。 The meaning of "one embodiment" or "an embodiment" in the description is to complement the special features, structures, or characteristics described in this embodiment. In at least one of the embodiments of the invention. The appearances of the "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment. The term couple as used herein may include directly electrically connecting two or more devices or elements and indirectly connecting via intervening devices.
非揮發記憶體可以包含具有一利用矽-氧化物-氮化物-氧化物-矽(Silicon-Oxide-Nitride-Oxide-Silicon,SONOS)或是浮接閘極技術(floating gate technology)所施行的非揮發記憶體電晶體或裝置的記憶體單元。 The non-volatile memory may include a non-volatile memory using silicon-oxide-nitride-oxide-silicon (Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)) or floating gate technology. Memory unit of a volatile memory transistor or device.
於圖1中所示的其中一實施例中,該非揮發記憶體電晶體或裝置係一SONOS類型的非揮發記憶體裝置。參考圖1,一SONOS裝置100包含一閘極堆疊102,其被形成在一基板104上方。SONOS裝置100進一步包含源極/汲極區106,它們被形成在閘極堆疊102任一側的基板104中的一井部108之中,其在閘極堆疊下面定義一通道區110。閘極堆疊102包含一氧化物隧穿介電層112、一氮化物或氮氧化物電荷陷捕層114、一頂端、阻 隔氧化物層116以及一多晶矽(poly)或金屬層,用以充當控制閘極118。 In one embodiment shown in FIG. 1, the non-volatile memory transistor or device is a SONOS type non-volatile memory device. Referring to FIG. 1, a SONOS device 100 includes a gate stack 102 formed over a substrate 104. The SONOS device 100 further includes a source / drain region 106 formed in a well 108 in a substrate 104 on either side of the gate stack 102, which defines a channel region 110 under the gate stack. The gate stack 102 includes an oxide tunneling dielectric layer 112, a nitride or oxynitride charge trapping layer 114, a top end, a resistive layer The oxide barrier layer 116 and a polycrystalline silicon (poly) or metal layer are used as the control gate 118.
當控制閘極118被適當偏壓時,來自該源極/汲極區106的電子會被注入或隧穿通過隧穿介電層112並且被陷捕在電荷陷捕層114中。電荷被注入的機制可包含傅勒-諾德翰(Fowler-Nordheim,FN)隧穿以及熱載子注入。被陷捕在電荷陷捕層114中的電荷會在汲極和源極之間導致一能量屏障,從而提高用以開啟導通該SONOS裝置100所需要的臨界電壓VT,將該裝置置於「已程式化(programmed)」狀態中。該SONOS裝置100能夠藉由施加一反向偏壓於控制閘極118上而被「抹除(erased)」或者讓已陷捕的電荷被移除並且由電洞取代。 When the control gate 118 is properly biased, electrons from the source / drain region 106 are injected or tunneled through the tunneling dielectric layer 112 and trapped in the charge trapping layer 114. The mechanism of charge injection may include Fowler-Nordheim (FN) tunneling and hot carrier injection. The charge trapped in the charge trapping layer 114 will cause an energy barrier between the drain and the source, thereby increasing the threshold voltage V T required to turn on the SONOS device 100 and placing the device at ""Programmed" status. The SONOS device 100 can be "erased" or a trapped charge can be removed and replaced by a hole by applying a reverse bias to the control gate 118.
於另一實施例中,該非揮發陷捕電荷半導體裝置可能係一浮接閘極MOS場效電晶體(Floating-Gate MOS,FGMOS)或裝置。一般來說,其結構雷同於上面所述的SONOS裝置100,主要差異在於FGMOS包含一多晶矽(poly)浮接閘極,其被電容性耦合至該裝置的輸入,而不是氮化物或氮氧化物電荷陷捕。因此,該FGMOS裝置能夠參考圖1來作說明。參考圖1,一FGMOS裝置100包含一閘極堆疊102,其被形成在一基板104上方。該FGMOS裝置100進一步包含源極/汲極區106,它們被形成在閘極堆疊102任一側的基板104中的一井部108之中,其在閘極堆疊下面定義一通道區110。閘極堆疊102包含一隧穿介電層112、一浮接閘極層114、一阻隔氧化物層或頂端介電層116以及一多晶矽(poly)或金屬層,用以充當控制閘極118。 In another embodiment, the non-volatile trapped charge semiconductor device may be a floating gate MOS field effect transistor (FGMOS) or device. Generally speaking, its structure is similar to the SONOS device 100 described above. The main difference is that FGMOS contains a poly-crystalline silicon (poly) floating gate, which is capacitively coupled to the input of the device instead of nitride or oxynitride Charge trapping. Therefore, the FGMOS device can be described with reference to FIG. 1. Referring to FIG. 1, an FGMOS device 100 includes a gate stack 102 formed over a substrate 104. The FGMOS device 100 further includes a source / drain region 106 formed in a well 108 in a substrate 104 on either side of the gate stack 102, which defines a channel region 110 under the gate stack. The gate stack 102 includes a tunneling dielectric layer 112, a floating gate layer 114, a blocking oxide layer or a top dielectric layer 116, and a polycrystalline silicon (poly) or metal layer to serve as the control gate 118.
雷同於上面所述的SONOS裝置,FGMOS裝置100能夠藉由施加一適當偏壓於該控制閘極與該源極區及汲極區之間而被程式化,用以 注入電荷於該電荷陷捕層之中,提高用以開啟導通該FGMOS裝置所需要的臨界電壓VT。該FGMOS裝置能夠藉由施加一反向偏壓於該控制閘極上而被抹除或者讓已陷捕的電荷被移除。 Similar to the SONOS device described above, the FGMOS device 100 can be programmed by applying an appropriate bias between the control gate and the source and drain regions to inject charge into the charge trap. In the layer, the threshold voltage V T required to turn on the FGMOS device is increased. The FGMOS device can be erased or the trapped charge can be removed by applying a reverse bias to the control gate.
一記憶體陣列係藉由製作被排列在多列與多行中記憶體單元格柵並且藉由數條水平控制線與垂直控制線連接至周邊電路系統(例如,位址解碼器與感測放大器)來建構。每一個記憶體單元皆包含至少一非揮發陷捕電荷半導體裝置(例如,上面所述者)並且可以有單一電晶體(1T)或雙電晶體(2T)架構。 A memory array is made by arranging memory cell grids arranged in multiple columns and rows and connected to peripheral circuits (e.g., address decoders and sense amplifiers) by several horizontal control lines and vertical control lines. ) To construct. Each memory cell contains at least one non-volatile trapped charge semiconductor device (for example, the one described above) and may have a single transistor (1T) or a double transistor (2T) structure.
於圖2中所示的其中一實施例中,記憶體單元200具有2T架構,而且除了一非揮發記憶體電晶體202之外還包含一傳導或選擇電晶體204,舉例來說,和記憶體電晶體202共享一共用基板連接206的習知IGFET。參考圖2,記憶體電晶體202具有:一電荷陷捕層208;一汲極210,其被連接至選擇電晶體204的源極222並且經由該選擇電晶體被連接至一位元線212:一控制閘極214,其被連接至一字元線216;以及一源極218,其被連接至一源極線224。選擇電晶體204還包含:一汲極220,其被連接至一位元線212;以及一閘極226,其被連接至一選擇或讀取線228。 In one embodiment shown in FIG. 2, the memory unit 200 has a 2T structure and includes a non-volatile memory transistor 202 and a conductive or selective transistor 204, for example, and a memory. The transistor 202 shares a conventional IGFET with a common substrate connection 206. Referring to FIG. 2, the memory transistor 202 has a charge trapping layer 208 and a drain 210 connected to the source 222 of the selection transistor 204 and connected to a bit line 212 via the selection transistor: A control gate 214 is connected to a word line 216; and a source 218 is connected to a source line 224. The selection transistor 204 further includes a drain 220 connected to a bit line 212 and a gate 226 connected to a selection or read line 228.
在用以抹除記憶體單元200的抹除作業期間,一負高電壓(VNEG)會被施加至字元線216且一正高電壓(VPOS)被施加至該位元線與該基板連接206。一般來說,記憶體單元200係當作一大量抹除作業的一部分而被抹除,在大量抹除作業中,一記憶體陣列的一選定列中的所有記憶體單元會在進行用以程式化該記憶體單元200的程式化作業之前藉由施加該適當電壓至該列中所有記憶體單元共享的總體字元線(GWL),該基板連接以及該 記憶體陣列中的所有位元線而被立刻抹除。 During the erasing operation to erase the memory unit 200, a negative high voltage (V NEG ) is applied to the word line 216 and a positive high voltage (V POS ) is applied to the bit line and connected to the substrate. 206. Generally, the memory unit 200 is erased as part of a mass erase operation. In the mass erase operation, all the memory cells in a selected row of a memory array are being used for programming. The stylizing operation of the memory cell 200 is performed by applying the appropriate voltage to the global word line (GWL) shared by all the memory cells in the row, the substrate connection, and all the bit lines in the memory array. Was erased immediately.
在該程式化作業期間,被施加至字元線216和位元線212的電壓會被反向,VPOS被施加至該字元線且VNEG被施加至該位元線,以便施加一偏壓來程式化該記憶體電晶體202。基板連接206或是連接至其中形成該記憶體電晶體202的井部的連接會被耦合至電接地、VNEG或是被耦合至介於接地與VNEG之間的電壓。讀取或選擇線228同樣會被耦合至電接地(0V),而源極線224可以和位元線212相等電位,也就是,被耦合至VNEG或是允許浮接。 During the stylized operation, the voltages applied to the word line 216 and the bit line 212 are reversed, V POS is applied to the word line, and V NEG is applied to the bit line in order to apply a bias. To program the memory transistor 202. The substrate connection 206 or the connection to the well portion in which the memory transistor 202 is formed is coupled to the electrical ground, V NEG, or to a voltage between the ground and V NEG . The read or select line 228 is also coupled to electrical ground (0V), and the source line 224 may be at the same potential as the bit line 212, that is, coupled to V NEG or allowed to float.
在完成抹除作業或程式化作業之後,記憶體單元200的狀態會藉由下面方式而被讀取:設定記憶體電晶體202的閘極至源極電壓(VGS)為零;施加一小電壓於汲極終端210與源極終端218之間;以及感測流經該記憶體電晶體的電流。於已程式化狀態中,舉例來說,一N型SONOS記憶體電晶體將會為不導通,因為VGS會在已程式化臨界電壓VTP以下。於已抹除狀態中,該N型記憶體電晶體將會為導通,因為VGS會在已抹除臨界電壓VTE以上。依照慣例,導通狀態和邏輯「0」相關聯而不導通狀態和邏輯「1」相關聯。 After the erase operation or the programming operation is completed, the state of the memory unit 200 will be read by: setting the gate-to-source voltage (V GS ) of the memory transistor 202 to zero; applying a small The voltage is between the drain terminal 210 and the source terminal 218; and a current flowing through the memory transistor is sensed. In the programmed state, for example, an N-type SONOS memory transistor will be non-conducting because V GS will be below the programmed threshold voltage V TP . In the erased state, the N-type memory transistor will be turned on because V GS will be above the erased threshold voltage V TE . By convention, the on state is associated with logic "0" and the on state is associated with logic "1".
現在將參考圖3以及下面的表I來說明用以減少干擾的一種記憶體單元之一記憶體陣列及操作其之方法。在下面的說明中,為清楚及方便解釋起見,假設記憶體陣列中的所有電晶體皆為N型SONOS電晶體。應該明白的是,將外加電壓的極性反向即可說明P型配置且此配置落在本發明探討的實施例內,其並未喪失一般性。此外,下面說明中所使用的電壓僅係為方便解釋而選擇並且僅代表本發明的其中一示範性實施例。其它 電壓可以運用在本發明的不同實施例中。 A memory array and a method of operating one of the memory cells to reduce interference will now be described with reference to FIG. 3 and Table I below. In the following description, for clarity and ease of explanation, it is assumed that all transistors in the memory array are N-type SONOS transistors. It should be understood that reversing the polarity of the applied voltage can explain the P-type configuration, and this configuration falls within the embodiments discussed in the present invention, which does not lose its generality. In addition, the voltages used in the following description are selected only for convenience of explanation and represent only one exemplary embodiment of the present invention. other Voltage can be used in different embodiments of the invention.
圖3所示的係一記憶體陣列300的一區段的一示範性實施例,其可以為一大型記憶體單元之一記憶體陣列的一部分。在圖3中,記憶體陣列300包含四個記憶體單元301、302、303、以及304,它們被排列在兩列(列1、列2)與兩行(行1、行2)之中。該記憶體單元301至304中的每一者的結構和上面所述的記憶體單元200相同。 An exemplary embodiment of a section of a memory array 300 shown in FIG. 3 may be part of a memory array of a large memory unit. In FIG. 3, the memory array 300 includes four memory cells 301, 302, 303, and 304 which are arranged in two columns (column 1, column 2) and two rows (row 1, row 2). The structure of each of the memory cells 301 to 304 is the same as that of the memory cell 200 described above.
參考圖3,記憶體單元301為要被程式化成邏輯「1」狀態(也就是,被程式化成ON狀態)的目標單元,而已經藉由先前抹除作業而被抹除為邏輯「0」狀態的記憶體單元302則保持在邏輯「0」或OFF狀態。此兩個目標(程式化單元301以及禁止單元302)係藉由下面方式來達成:施加一第一或正高電壓(VPOS)至記憶體陣列300的第一列中的一第一總體字元線(GWL1),一第二或負高電壓(VNEG)會被施加至一第一位元線(BL1),用以加偏壓於電晶體T1為導通以程式化該選定記憶體單元301,而一禁止電壓(Vlnhib)會被施加至一第二位元線(BL2)用以偏壓電晶體T2為不導通以禁止程式化該解選記憶體單元302,以及一共同或共享電壓會被施加至所有記憶體單元301、302、303、以及304的基板節點(SUB)而讀取線(RL1與RL2)則被耦合至電性接地(0V)。源極線(SL1與SL2)可以位在和它們個別行中的位元線相等電位處,也就是,SL1被耦合至VNEG且SL2被耦合至Vlnhib或是允許為浮接。 Referring to FIG. 3, the memory unit 301 is a target unit to be programmed into a logical "1" state (that is, programmed to an ON state), and has been erased to a logical "0" state by a previous erase operation The memory unit 302 remains in a logic "0" or OFF state. This two targets (stylized prohibition unit 301 and unit 302) based achieved by the following manner: a first generally applying a first character in the first column or positive high voltage (V POS) to the memory array 300 in Line (GWL 1 ), a second or negative high voltage (V NEG ) will be applied to a first bit line (BL 1 ) to bias the transistor T1 to conduct to program the selected memory Unit 301, and a forbidden voltage (V lnhib ) is applied to a second bit line (BL 2 ) to bias transistor T2 to be non-conducting to prohibit programming of the deselected memory unit 302, and a common Or the shared voltage is applied to the substrate nodes (SUB) of all the memory cells 301, 302, 303, and 304, and the read lines (RL1 and RL2) are coupled to the electrical ground (0V). The source lines (SL1 and SL2) may be located at the same potential as the bit lines in their individual rows, that is, SL1 is coupled to V NEG and SL2 is coupled to V lnhib or allowed to float.
此外,且如下面的更詳細說明,一具電壓位準或大小小於VNEG的選定邊限電壓(VMARG)會被施加至記憶體陣列300的第二列中的一第二總體字元線(GWL2),用以減少或實質上消除因該選定記憶體單元3()1之程 式化的關係所造成之該解選記憶體單元304中的程式狀態位元線干擾。 Further, and as described in more detail below, the threshold voltage (V MARG) is generally applied to a second word line to the second row in the memory array 300 or a selected size of less than the voltage level V NEG of a side (GWL 2 ), used to reduce or substantially eliminate program state bit line interference in the deselected memory unit 304 caused by the stylized relationship of the selected memory unit 3 () 1.
表I所示的係可用於程式化一具有2T架構並且包含具有N型SONOS電晶體之記憶體單元的非揮發記憶體的示範性偏壓電壓。 The system shown in Table I can be used to program an exemplary bias voltage for a non-volatile memory with a 2T architecture and a memory cell with an N-type SONOS transistor.
因為被施加至一第二總體字元線(GWL2)的電壓的電壓位準或大小小於習知技術中被施加至解選列或單元中的VNEG,所以,跨越電晶體T4的閘極至汲極電壓(VGD)為3.8V,對照習知操作記憶體中4.8V的VGD,T4的臨界電壓VT的位元線干擾量已明顯減少。於本發明的其中一實施例中會觀察到從約60mV減少至小於約7mV。 Because the voltage level or magnitude of the voltage applied to a second global word line (GWL2) is less than the V NEG applied to the deselected column or cell in the conventional technique, the gate across transistor T4 is The drain voltage (V GD ) is 3.8V. Compared with the V GD of 4.8V in the conventional operating memory, the bit line interference of the threshold voltage V T of T4 has been significantly reduced. In one embodiment of the invention, a decrease from about 60 mV to less than about 7 mV is observed.
邊限電壓(VMARG)能夠利用記憶體中單獨用來產生VMARG的專屬電路系統(圖中並未顯示)來產生,或者,能夠利用該記憶體裝置中已包含的電路系統來產生。一般來說,邊限電壓(VMARG)和第二或VMEG高電壓具有相同極性,但是高過或大於VNEG的電壓,該電壓至少等於其程式狀態位元線干擾會減少的記憶體單元304中電晶體T4的臨界電壓(VT)。視情況,用以產生邊限電壓(VMARG)的電路系統可程式化用以設定一具有多個梯級(於其中一實施例中梯級為14mV或更小)之所希望的邊限電壓(VMARG)。 The marginal voltage (V MARG ) can be generated by a dedicated circuit system (not shown in the figure) used to generate V MARG alone in the memory, or it can be generated by the circuit system already included in the memory device. In general, the marginal voltage (V MARG ) and the second or V MEG high voltage have the same polarity, but a voltage higher than or greater than V NEG , which is at least equal to the memory cell whose program state bit line interference will be reduced. Threshold voltage (V T ) of transistor T4 in 304. Depending on the situation, the circuit system used to generate the margin voltage (V MARG ) can be programmed to set a desired margin voltage (V with a step of 14 mV or less in one embodiment). MARG ).
於其中一實施例中,用以產生邊限電壓(VMARG)的電路系統包 含一數位至類比轉換器(Digital-to-Analog-Converter,DAC),其係由記憶體中被程式化成用以產生具有所希望大小或電壓位準之邊限電壓(VMARG)的命令與控制電路系統來致能,用以在程式化作業期間被耦合至(多條)解選列的GWL。於其中一特殊的有利實施例中,該DAC係記憶體中的一邊限模式DAC,其在該記憶體的初始化期間被用來調整其中的電壓,而且在程式化作業期間其通常不會被致能。此實施例的顯著優點包含VMARG能夠利用該(MDAC)位元來修正,其不代表用於VNEG的負泵上的大型負載,而且該邊限模式DAC的一輸出緩衝器會提供一用於VMARG訊號的低阻抗驅動器。在程式化作業期間調整此邊限模式DAC來產生VMARG需要在程式化作業期間形成一電連接於記憶體陣列300的解選列的GWL,並且經由一DAC致能訊號來致能該邊限模式DAC。 In one embodiment, the circuit system for generating a margin voltage (V MARG ) includes a digital-to-analog-converter (DAC), which is programmed from the memory to be used for A command and control circuit system that generates a marginal voltage (V MARG ) of a desired magnitude or voltage level is enabled to be coupled to the (multiple) deselected rows of GWLs during programming. In one particular advantageous embodiment, the DAC is a one-edge mode DAC in the memory, which is used to adjust the voltage during the initialization of the memory, and it is not normally caused during programming. can. The significant advantages of this embodiment include that the V MARG can be corrected using this (MDAC) bit, which does not represent a large load on a negative pump for V NEG , and an output buffer of the marginal mode DAC will provide a useful Low impedance driver for V MARG signals. Adjusting this margin mode DAC to generate V MARG during the programming operation requires forming a deselected GWL electrically connected to the memory array 300 during the programming operation, and enabling the margin via a DAC enable signal Mode DAC.
於特定實施例中會希望對VMARG電路作進一步調適,以便克服VMARG在程式化期間,並非原本就設計成用來驅動大型電容性負載為有作用的事實。現在將參考圖4與5的曲線圖來說明克服此限制的其中一種方法。 In certain embodiments, it may be desirable to further adapt the V MARG circuit in order to overcome the fact that V MARG was not originally designed to drive large capacitive loads during programming. One way to overcome this limitation will now be described with reference to the graphs of FIGS. 4 and 5.
圖4所示的係根據本揭示內容一實施例的正第一高電壓(VPOS 402)、負第二高電壓(VNEG 404)以及一中間邊限電壓(VMARG 406)的曲線圖。參考圖4,應該注意的是,對照於第二高電壓(VNEG 404),用以產生邊限電壓(VMARG 406)的電路的啟動時間相對緩慢,直到80至110μs為止。在此時間期間,被施加該邊限電壓(VMARG 406)的解選總體字元線(GWL2)和被施加第二高電壓(VNEG 404)的p井部(SPW)或基板節點之間的電壓差會在20至40μs中達到1.6至1.7伏特。因此,為減少記憶體陣列的第一行與第二列中 未被選定記憶體單元(舉例來說,單元T3)中的抹除狀態位元線干擾,VNEG會被耦合至該解選列中的第二總體字元線GWL2維持高達約40μs,直到和該(些)解選字元線相關聯的電容被充分預充電且VNEG已經達到接近-2.0伏特的數值為止。該邊限電壓接著會在程式化作業的剩餘時間中,被耦合至該解選列中的該總體字元線(GWL2),用以減少因該選定記憶體單元之程式化的關係所造成之該記憶體陣列的第二行與第二列中的一第二未被選定記憶體單元中的程式狀態位元線干擾。 FIG. 4 is a graph of a positive first high voltage (V POS 402), a negative second high voltage (V NEG 404), and an intermediate margin voltage (V MARG 406) according to an embodiment of the present disclosure. Referring to FIG. 4, it should be noted that, compared to the second high voltage (V NEG 404), the startup time of the circuit used to generate the marginal voltage (V MARG 406) is relatively slow until 80 to 110 μs. During this time, the deselected overall word line (GWL 2 ) to which this marginal voltage (V MARG 406) is applied and the p-well (SPW) or substrate node of the substrate node to which the second high voltage (V NEG 404) is applied The voltage difference between them can reach 1.6 to 1.7 volts in 20 to 40 μs. Therefore, in order to reduce the interference of the erased state bit line in the unselected memory cell (for example, cell T3) in the first row and the second column of the memory array, V NEG will be coupled to the deselected column The second overall word line GWL 2 in the medium remains as high as about 40 μs until the capacitance associated with the deselected word line (s) is fully precharged and V NEG has reached a value close to -2.0 volts. The marginal voltage is then coupled to the global word line (GWL 2 ) in the deselected row for the remainder of the stylization operation to reduce the risk caused by the stylized relationship of the selected memory cell. The second row of the memory array interferes with a program status bit line in a second unselected memory cell in the second column.
圖5所示的係根據本揭示內容一實施例的程式化作業期間被施加至一選定總體字元線(VSELECTED WL 502)與一解選總體字元線(VDESELECTED GWL 504)的電壓的曲線圖。參考圖5,從解選總體字元線電壓(VDESELECTED GWL 504)的曲線圖中可注意到,在該解選總體字元線電壓之曲線圖上元件符號506所示的約15μs處,該解選列中的總體字元線(GWL2)從被耦合至第二高電壓(VNEG 404)切換為在該程式化作業的剩餘時間中被耦合至邊限電壓(VMARG 406)。 FIG. 5 illustrates the voltages applied to a selected global character line (V SELECTED WL 502) and a deselected global character line (V DESELECTED GWL 504) during a stylized operation according to an embodiment of the present disclosure. Graph. Referring to FIG. 5, from the graph of the deselected global word line voltage (V DESELECTED GWL 504), it can be noted that at about 15 μs shown by the element symbol 506 on the graph of the deselected global word line voltage, the The global word line (GWL 2 ) in the deselected column switches from being coupled to the second high voltage (V NEG 404) to being coupled to the marginal voltage (V MARG 406) for the remainder of the stylized operation.
現在將參考圖6來說明根據本揭示內容一實施例之用以減少位元線程式化干擾的處理系統600。 A processing system 600 for reducing bit threading interference according to an embodiment of the present disclosure will now be described with reference to FIG. 6.
參考圖6,處理系統600大體上包含一非揮發記憶體602,其以習知的方式透過一位址匯流排606、一資料匯流排608以及一控制匯流排610被耦合至一處理器604。熟習本技術的人士會明白,為達圖解本發明之目的,圖6的處理系統已經被簡化並且沒有完整說明的意圖。明確地說,本文中沒有詳細說明本技術中已知的處理器、列解碼器與行解碼器、感測放大器、以及命令與控制電路系統的細節。 Referring to FIG. 6, the processing system 600 generally includes a non-volatile memory 602, which is coupled to a processor 604 through a bit bus 606, a data bus 608, and a control bus 610 in a conventional manner. Those skilled in the art will understand that for the purpose of illustrating the present invention, the processing system of FIG. 6 has been simplified and has no intention of being fully explained. Specifically, details of processors, column decoders and row decoders, sense amplifiers, and command and control circuitry known in the art are not described in detail herein.
處理器604可以為某種類型的一般用途或特殊用途處理裝置。舉例來說,於其中一實施例中,該處理器會係進一步包含一非揮發記憶體的可程式化系統或控制器(例如,位於美國加州聖荷西市的Cypress Semiconductor所販售的晶片上可程式化系統或PSoCTM控制器)中的處理器。 The processor 604 may be some type of general-purpose or special-purpose processing device. For example, in one embodiment, the processor is a programmable system or controller further including a non-volatile memory (for example, a chip sold by Cypress Semiconductor in San Jose, California, USA). Programmable system or processor in a PSoC TM controller).
該非揮發記憶體602包含一記憶體陣列612,其如上面所述般被組織成多列與多行的非揮發記憶體單元(本圖中並未顯示)。記憶體陣列612如上面所述般透過多條字元線與讀取線616(該記憶體陣列的每一列至少一字元線與一讀取線)被耦合至一列解碼器614。該記憶體陣列612進一步如上面所述般透過多條位元線與源極線620(該記憶體陣列的每一行各一條位元線與源極線)被耦合至一行解碼器618。該記憶體陣列612被耦合至複數個感測放大器622,用以從該處讀取多位元字元(multi-bit words)。該非揮發記憶體602進一步包含命令與控制電路系統624,用以控制列解碼器614、行解碼器618以及感測放大器622,並且用以從感測放大器處接收讀取資料。該命令與控制電路系統624包含電壓控制電路系統626,用以產生該非揮發記憶體602之操作所需要的電壓(其包含VPOS、VNEG以及VINHIB),並且包含一邊限模式DAC 628,用以產生上面所述的VMARG,其會經由該電壓控制電路系統被繞送至列解碼器614。電壓控制電路系統626會操作用以在讀取作業、抹除作業以及程式化作業期間施加適當的電壓至該記憶體單元。 The non-volatile memory 602 includes a memory array 612, which is organized into multiple columns and rows of non-volatile memory cells (not shown in the figure) as described above. The memory array 612 is coupled to a column of decoders 614 through a plurality of word lines and read lines 616 (at least one word line and one read line in each column of the memory array) as described above. The memory array 612 is further coupled to a row of decoders 618 through a plurality of bit lines and source lines 620 (one bit line and source line for each row of the memory array) as described above. The memory array 612 is coupled to a plurality of sense amplifiers 622 for reading multi-bit words therefrom. The non-volatile memory 602 further includes a command and control circuit system 624 for controlling the column decoder 614, the row decoder 618, and the sense amplifier 622, and for receiving read data from the sense amplifier. The command and control circuit system 624 includes a voltage control circuit system 626 for generating a voltage (including V POS , V NEG and V INHIB ) required for the operation of the non-volatile memory 602, and includes a one-sided mode DAC 628. To generate the V MARG described above, it is routed to the column decoder 614 via the voltage control circuitry. The voltage control circuit system 626 is operable to apply an appropriate voltage to the memory unit during a read operation, an erase operation, and a programming operation.
命令與控制電路系統624被配置成用以控制列解碼器614,以便藉由施加一VPOS至第一列中的第一總體字元線(GWL1)在一程式化作業中選擇記憶體陣列612的第一列以及藉由施加一邊限電壓至第二列中的第二總體字元線(GWL2)來解選該記憶體陣列的第二列。於某些實施例中,命 令與控制電路系統624被配置成用以依序耦合第一VNEG至第二總體字元線維持一短暫的時間週期並且接著耦合該邊限電壓。如上面所述,於某些實施例中,對照於被耦合至一基板節點或於其中形成該記憶體電晶體的p井部(SPW)的VNEG的啟動時間,邊限電壓電路的啟動時間相對緩慢,且於此時間期間,該解選字元線(GWL2)和p井部(SPW)或基板節點之間的電壓偏壓差會在記憶體陣列的第一行與第二列中未被選定記憶體單元(舉例來說,單元T3)中導致抹除狀態位元線干擾。因此,為減少在記憶體陣列的第一行與第二列中未被選定記憶體單元(舉例來說,單元T3)中的抹除狀態位元線干擾,VNEG會被耦合至該解選列中的第二總體字元線(GWL2)維持一短暫時間,直到和該(些)解選字元線相關聯的電容被充分預充電且VNEG已經抵達接近-2.0伏特的數值為止。該邊限電壓接著會在程式化作業的剩餘時間中被耦合至該解選列中的該總體字元線(GWL2),用以減少因該選定記憶體單元之程式化的關係所造成之該記憶體陣列的第二行與第二列中的一第二未被選定記憶體單元中的程式狀態位元線干擾。 The command and control circuit system 624 is configured to control the column decoder 614 to select a memory array in a stylized operation by applying a V POS to the first global word line (GWL 1 ) in the first column. The first column of 612 and the second overall word line (GWL 2 ) in the second column are deselected by applying a one-sided voltage to the second column of the memory array. In some embodiments, the command and control circuit system 624 is configured to sequentially couple the first V NEG to the second global word line for a short period of time and then couple the threshold voltage. As described above, in some embodiments, the start-up time of the marginal voltage circuit is compared to the V NEG start-up time of a p-well (SPW) coupled to a substrate node or in which the memory transistor is formed. Relatively slow, and during this time, the voltage bias difference between the deselected word line (GWL 2 ) and p-well (SPW) or substrate node will be in the first row and the second column of the memory array Unselected memory cells (for example, cell T3) result in erased state bit line interference. Therefore, in order to reduce the interference of the erased state bit line in the unselected memory cell (for example, cell T3) in the first row and the second column of the memory array, V NEG is coupled to the deselection The second overall word line (GWL 2 ) in the column is maintained for a short time until the capacitors associated with the deselected word line (s) are fully precharged and V NEG has reached a value close to -2.0 volts. The marginal voltage is then coupled to the global word line (GWL 2 ) in the deselected column for the remainder of the stylization operation to reduce the effects caused by the stylized relationship of the selected memory cell. The second row of the memory array interferes with a program status bit line in a second unselected memory cell in the second column.
命令與控制電路系統624進一步被配置成用以控制行解碼器618,以便藉由施加一VNEG至第一行中的第一共享位元線(BL1)而選擇該第一列中的一記憶體單元(舉例來說,單元T1)來進行程式化以及藉由施加一禁止電壓至一第二行中的一第二共享位元線(BL2)來禁止該第一列中的一未被選定記憶體單元(舉例來說,單元T2)進行程式化。該行解碼器618可以進一步被配置成用以施加VNEG至第一行中的第一共享源極線(SL1)並且施加該禁止電壓於該第二行中的第二共享源極線(SL2)上。 The command and control circuit system 624 is further configured to control the row decoder 618 to select one of the first columns by applying a V NEG to the first shared bit line (BL 1 ) in the first row. memory unit (e.g., unit T1) is performed by applying a stylized and second shared bit line (BL 2) to an inhibit voltage to a second row in the first column is prohibited is not a The selected memory cell (for example, cell T2) is programmed. The row decoder 618 may be further configured to apply V NEG to the first shared source line (SL 1 ) in the first row and apply the inhibit voltage to the second shared source line (SL 1 ) in the second row. SL 2 ).
現在將參考圖7A至7C來說明根據本揭示內容各實施例的 記憶體裝置的命令與控制電路系統的細節。 Reference will now be made to FIGS. 7A to 7C to explain the effects of the embodiments of the present disclosure. Details of the command and control circuitry of the memory device.
參考圖7A,於其中一實施例中,命令與控制電路系統700包含:一負HV供應器或泵702,用以在程式化作業期間產生一被耦合至該選定單元之位元線及源極線且被耦合至該基板節點的VNEG;一數位至類比轉換器(DAC 704),其會被該命令與控制電路系統致能用以在程式化作業期間產生一要被耦合至解選列之GWL的邊限電壓;以及一切換電路706,用以在程式化作業期間於VNEG和耦合至該解選GWL的邊限電壓之間進行切換。DAC 704能夠為單獨用來產生VMARG的專屬DAC或是針對其它用途已被包含在該命令與控制電路系統700或電壓控制電路系統626中的DAC,且其通常在程式化作業期間不會被運用。如上面提及,於其中一特殊的有利實施例中,該DAC為非揮發記憶體602的命令與控制電路系統624中的一邊限模式DAC 628,其在測試期間被用來測量其中的非揮發裝置的臨界電壓且其在程式化作業期間通常不會被致能。應該明白的是,在程式化作業期間調整此邊限模式DAC來產生VMARG需要在程式化作業期間形成一電連接以連接至該切換電路706,並且經由該切換電路與該列解碼器(此圖中並未顯示)連接至該記憶體陣列的解選列的GWL。非揮發記憶體602的命令與控制電路系統624會經由一DAC致能訊號來致能DAC 704,且視情況,操作該DAC用以提供一經程式化的邊限電壓位準或大小。一般來說,該DAC 704會被操作用以提供一大小小於VNEG的電壓大小(也就是,在上面所述的N型SONOS實施例中的正值高於或大於VNEG)的邊限電壓,其小於VNEG的電壓至少等於該記憶體單元中該記憶體電晶體的臨界電壓(VT)。於其它實施例中,該DAC 704可被程式化或操作用以提供一小於VNEG的數額接近該記憶體電 晶體之VT的邊限電壓大小。舉例來說,於上面所述的其中一實施例中,該DAC 704可被程式化或操作用以提供一可調整至一或更多個小額梯級(每一個梯級約14mV)內的邊限電壓。 Referring to FIG. 7A, in one embodiment, the command and control circuit system 700 includes: a negative HV supply or pump 702 for generating a bit line and a source coupled to the selected unit during a stylized operation. V NEG that is coupled to the substrate node; a digital-to-analog converter (DAC 704) that is enabled by the command and control circuitry to generate a de-selection column to be coupled during programming The threshold voltage of the GWL; and a switching circuit 706 for switching between V NEG and the threshold voltage coupled to the deselected GWL during the programming operation. DAC 704 can be a dedicated DAC used to generate V MARG alone or a DAC that has been included in the command and control circuitry 700 or voltage control circuitry 626 for other purposes, and it is not normally used during programming use. As mentioned above, in one particular advantageous embodiment, the DAC is a one-edge mode DAC 628 in the command and control circuit system 624 of the non-volatile memory 602, which is used to measure the non-volatile therein during the test The critical voltage of the device and it is usually not enabled during programming. It should be understood that adjusting this marginal mode DAC to generate V MARG during the programming operation requires an electrical connection to be connected to the switching circuit 706 during the programming operation, and the switching circuit and the column decoder (this (Not shown) the GWL of the deselected row connected to the memory array. The command and control circuit system 624 of the non-volatile memory 602 enables the DAC 704 via a DAC enable signal, and optionally operates the DAC to provide a programmed threshold voltage level or magnitude. Generally, the DAC 704 is operated to provide a marginal voltage having a voltage smaller than V NEG (ie, a positive value higher than or greater than V NEG in the N-type SONOS embodiment described above) Its voltage less than V NEG is at least equal to the threshold voltage (V T ) of the memory transistor in the memory unit. In other embodiments, the DAC 704 may be programmed or operated to provide an amount of voltage less than V NEG close to the threshold voltage of V T of the memory transistor. For example, in one of the embodiments described above, the DAC 704 can be programmed or operated to provide a threshold voltage that can be adjusted within one or more small steps (each step is approximately 14mV). .
於圖7B中所示的另一實施例中,命令與控制電路系統700包含一第二電荷泵708,用以產生要在程式化作業期間被耦合至解選列的GWL的邊限電壓。藉由選擇該第二電荷泵708使其具有和負泵702實質上相同啟動時間與功率,用以充電與該(些)解選字元線相關聯的電容,該解選列的GWL會在整個程式化作業中被耦合至該邊限電壓,並且因而需要消除一分離的切換電路706。 In another embodiment shown in FIG. 7B, the command and control circuit system 700 includes a second charge pump 708 for generating a threshold voltage of the GWL to be coupled to the deselected row during a stylized operation. By selecting the second charge pump 708 to have substantially the same startup time and power as the negative pump 702 to charge the capacitors associated with the deselected word line (s), the GWL of the deselected column will be at This marginal voltage is coupled throughout the stylized operation, and thus a separate switching circuit 706 needs to be eliminated.
於圖7中所示的又一實施例中,命令與控制電路系統700包含一分壓器710,其被耦合至負泵702的一輸出用以產生要在程式化作業期間被耦合至解選列之GWL的邊限電壓。因為VNEG與VMARG兩者皆由負泵702來供應,所以,VNEG與VMARG之間的啟動時間沒有任何差異,而且被施加至解選字元線(GWL2)的VMARG與被施加至p井部(SPW)或基板節點的VNEG之間的電壓偏壓差異無法抵達足以在該記憶體陣列的第一行與第二列中的未被選定記憶體單元中造成抹除狀態位元線干擾的電壓位準(舉例來說,1.6至1.7伏特維持20至40μs),該解選列的GWL會在整個程式化作業中被耦合至該邊限電壓,並且因而需要消除一分離的切換電路706。 In yet another embodiment shown in FIG. 7, the command and control circuit system 700 includes a voltage divider 710 that is coupled to an output of the negative pump 702 to generate a signal to be coupled to the deselection during a stylized operation. Listed GWL threshold voltages. Because both the V NEG V MARG chosen by the negative pump 702 is supplied, so that the time between the start and V NEG V MARG no difference, and the solution is applied to the selected word line (GWL 2) and is of V MARG The voltage bias difference between the V NEG applied to the p-well (SPW) or the substrate node cannot reach enough to cause an erased state in unselected memory cells in the first and second rows of the memory array The voltage level of bit line interference (for example, 1.6 to 1.7 volts is maintained at 20 to 40 μs), the deselected GWL is coupled to the threshold voltage throughout the stylization operation, and therefore a separation needs to be eliminated的 开关 电路 706。 The switching circuit 706.
圖8所示的係在其中一實施例中用以減少程式化干擾的方法的流程圖。請注意,應該瞭解的是,下面雖然單獨說明該方法的所有步驟而暗示未必需要依序的順序,且如圖8中所示,該方法的前面五個單獨步驟係在實質上相同的時間處被實施,而至少兩個步驟則按照順序僅在稍 微延遲之後被實施。 FIG. 8 is a flowchart of a method for reducing stylized interference in one embodiment. Note that it should be understood that although all the steps of the method are explained separately below without implying that a sequential order is not necessary, and as shown in FIG. 8, the first five separate steps of the method are at substantially the same time Are implemented, while at least two steps are in order Implemented after a slight delay.
參考圖8,一第一正高電壓(VPOS)會被耦合至一記憶體單元之一記憶體陣列的一第一列中的一第一總體字元線(802)。在下一個作業中,一VNEG會被耦合至該記憶體陣列的一第一行中的一第一共享位元線用以施加一偏壓至一選定記憶體單元中的一非揮發記憶體電晶體,以便程式化該選定記憶體單元(804)。於該記憶體電晶體被形成在一基板中的井部中的實施例中,該井部可以被耦合至電接地、接地與VNEG之間的電壓、或者如所示實施例中般被耦合至VNEG(806)。視情況,VNEG可以被耦合至該記憶體陣列的一第二列中的一第二總體字元線維持一短暫時間,用以施加一偏壓至該記憶體陣列的第一行和第二列中的一第一未被選定記憶體單元中的一非揮發記憶體電晶體,該選定記憶體陣列和該選定記憶體單元共享該第一共享位元線,以便減少該第一未被選定記憶體單元中的抹除狀態位元線干擾(808)。同步地,一小於VNEG的邊限電壓會被產生(810)。在下一個作業中,僅在稍微延遲之後,該邊限電壓會耦合至該記憶體陣列的第二列中的第二總體字元線(812)。在下一個作業中,一禁止電壓會被耦合至該記憶體陣列的一第二行中的一第二共享位元線,用以施加一偏壓至該第二列與第二行中一第二未被選定記憶體單元中的一非揮發記憶體電晶體,以便減少該第二未被選定記憶體單元中的程式狀態位元線干擾(814)。 Referring to FIG. 8, a first positive high voltage (V POS ) is coupled to a first overall word line (802) in a first column of a memory array of a memory cell. In the next operation, a V NEG will be coupled to a first shared bit line in a first row of the memory array to apply a bias voltage to a non-volatile memory cell in a selected memory cell. Crystal to program the selected memory cell (804). In embodiments where the memory transistor is formed in a well portion in a substrate, the well portion may be coupled to an electrical ground, a voltage between the ground and V NEG , or may be coupled as in the illustrated embodiment. To V NEG (806). Optionally , V NEG may be coupled to a second global word line in a second column of the memory array for a short time to apply a bias to the first row and the second of the memory array. A non-volatile memory transistor in a first unselected memory cell in the column, the selected memory array and the selected memory cell share the first shared bit line to reduce the first unselected memory cell The erase status bit line interference in the memory cell (808). Simultaneously, a boundary voltage less than V NEG is generated (810). In the next operation, only after a slight delay, the marginal voltage is coupled to the second overall word line (812) in the second column of the memory array. In the next operation, a forbidden voltage is coupled to a second shared bit line in a second row of the memory array to apply a bias voltage to a second in the second column and a second in the second row. A non-volatile memory transistor in the unselected memory cell to reduce program state bit line interference in the second unselected memory cell (814).
因此,本文已經說明非揮發記憶體的實施例以及操作其之方法,用以減少干擾。本揭示內容雖然已經參考明確的示範性實施例作過說明,不過應該明白的是,可以對此些實施例進行各種修正與變更,其並沒有脫離本揭示內容的更廣精神與範疇。據此,本說明書及圖示應被視為解 釋性而沒有限制意義。 Therefore, embodiments of non-volatile memory and methods of operating it have been described herein to reduce interference. Although the present disclosure has been described with reference to specific exemplary embodiments, it should be understood that various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of the present disclosure. Accordingly, this manual and illustrations should be considered as solutions. Interpretive without limiting meaning.
本揭示內容的發明摘要符合37 C.F.R.§1.72(b)的規範,該規範要求發明摘要要讓讀者快速確定技術性揭示內容的一或更多個實施例的本質。應該瞭解的是,發明摘要並非用來詮釋或限制申請專利範圍的範疇或意義。此外,在前面的【實施方式】中可以看見,為達簡化揭示之目的,不同的特點會被集合在單一實施例中。此種揭示方法不應被詮釋為映現的意圖為本文所主張的實施例所需要之特點多過每一個專利申請項中明確敘述者。確切地說,如同下面申請專利範圍之映現,本發明的主旨不及單一已揭實施例的所有特點。因此,下面的申請專利範圍會以引用的方式被併入【實施方式】中,每一個專利申請項各自表示一不同的實施例。 The abstract of this disclosure complies with the specification of 37 C.F.R. §1.72 (b), which requires the abstract to allow the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It should be understood that the abstract is not intended to interpret or limit the scope or meaning of the scope of patent application. In addition, it can be seen in the foregoing [embodiment] that, for the purpose of simplifying the disclosure, different features will be collected in a single embodiment. Such a disclosure method should not be interpreted as reflecting more features than those explicitly stated in each patent application with the intention that the embodiments claimed herein require more features. Specifically, as reflected in the scope of the patent application below, the subject matter of the present invention is less than all the features of a single disclosed embodiment. Therefore, the following patent application scope will be incorporated into the [Embodiment] by reference, and each patent application item represents a different embodiment.
說明中引用到其中一實施例或是一實施例的意義為配合該實施例所述的特殊特點、結構、或是特徵包含在該電路或方法的至少其中一個實施例中。出現在說明書中各個地方的其中一實施例中一詞未必全部表示相同實施例。 The meaning of referring to an embodiment or an embodiment in the description is to include the special features, structures, or characteristics described in this embodiment in at least one of the embodiments of the circuit or method. The appearances of one of the embodiments in various places in the specification are not necessarily all referring to the same embodiment.
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US13/920,352 US8675405B1 (en) | 2013-03-12 | 2013-06-18 | Method to reduce program disturbs in non-volatile memory cells |
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8675405B1 (en) * | 2013-03-12 | 2014-03-18 | Cypress Semiconductor Corp. | Method to reduce program disturbs in non-volatile memory cells |
US10262747B2 (en) | 2013-03-12 | 2019-04-16 | Cypress Semiconductor Corporation | Method to reduce program disturbs in non-volatile memory cells |
US9355725B2 (en) | 2013-12-12 | 2016-05-31 | Cypress Semiconductor Corporation | Non-volatile memory and method of operating the same |
CN105810246B (en) * | 2014-12-31 | 2020-08-11 | 群联电子股份有限公司 | Memory management method, memory storage device and memory control circuit unit |
US9437319B1 (en) * | 2015-06-25 | 2016-09-06 | Macronix International Co., Ltd. | Method for programming non-volatile memory with reduced bit line interference and associated device |
US9589652B1 (en) * | 2015-09-24 | 2017-03-07 | Cypress Semiconductor Corporation | Asymmetric pass field-effect transistor for non-volatile memory |
US9589634B1 (en) | 2016-03-31 | 2017-03-07 | Intel Corporation | Techniques to mitigate bias drift for a memory device |
US9773567B1 (en) | 2017-02-22 | 2017-09-26 | Qualcomm Incorporated | Reduced silicon-oxide-nitride-oxide-silicon (SONOS) flash memory program disturb |
US10147734B1 (en) | 2017-08-30 | 2018-12-04 | Cypress Semiconductor Corporation | Memory gate driver technology for flash memory cells |
US10332599B2 (en) * | 2017-11-14 | 2019-06-25 | Longitude Flash Memory Solutions Ltd. | Bias scheme for word programming in non-volatile memory and inhibit disturb reduction |
US10910058B2 (en) * | 2018-08-17 | 2021-02-02 | Microchip Technology Incorporated | Shared source line memory architecture for flash cell byte-alterable high endurance data memory |
US10950290B2 (en) | 2019-07-05 | 2021-03-16 | Macronix International Co., Ltd. | Memory device and operating method thereof that reduce off current to reduce errors in reading and writing data which have plurality of memory cell blocks and a source voltage generator |
TWI711044B (en) * | 2019-07-05 | 2020-11-21 | 旺宏電子股份有限公司 | Memory device and operating method thereof |
CN110619910B (en) * | 2019-08-30 | 2021-08-03 | 长江存储科技有限责任公司 | Memory control method, memory control device and storage medium |
US11443819B2 (en) | 2020-07-24 | 2022-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device, integrated circuit device and method |
CN111968691B (en) * | 2020-08-23 | 2022-10-28 | 南京优存科技有限公司 | Programming method and device for memory array |
CN112562761B (en) * | 2020-11-02 | 2022-04-19 | 长江先进存储产业创新中心有限责任公司 | Control method and device of three-dimensional memory and storage medium |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6163048A (en) * | 1995-10-25 | 2000-12-19 | Cypress Semiconductor Corporation | Semiconductor non-volatile memory device having a NAND cell structure |
US20050237817A1 (en) * | 2004-04-23 | 2005-10-27 | Akira Umezawa | Semiconductor memory device with MOS transistors, each having a floating gate and a control gate, and memory card including the same |
US7433241B2 (en) * | 2006-12-29 | 2008-10-07 | Sandisk Corporation | Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data |
US7463531B2 (en) * | 2006-12-29 | 2008-12-09 | Sandisk Corporation | Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages |
US20090290420A1 (en) * | 2008-05-20 | 2009-11-26 | Hynix Semiconductor, Inc. | Program method of nonvolatile memory device |
US20100188898A1 (en) * | 2007-10-05 | 2010-07-29 | Micron Technology, Inc. | Reducing effects of program disturb in a memory device |
CN102136293A (en) * | 2010-01-22 | 2011-07-27 | 三星电子株式会社 | Method of programming non-volatile semiconductor memory device |
US20110235409A1 (en) * | 2007-09-10 | 2011-09-29 | Hee Bok Kang | Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof |
US8125835B2 (en) * | 2008-09-22 | 2012-02-28 | Cypress Semiconductor Corporation | Memory architecture having two independently controlled voltage pumps |
US8243522B2 (en) * | 2009-12-24 | 2012-08-14 | Intel Corporation | NAND memory programming method using double vinhibit ramp for improved program disturb |
US8274831B2 (en) * | 2010-05-24 | 2012-09-25 | Sandisk Technologies Inc. | Programming non-volatile storage with synchronized coupling |
US8325521B2 (en) * | 2010-10-08 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and inhibited operation of flash memory with split gate |
US20130033934A1 (en) * | 2007-08-30 | 2013-02-07 | Infineon Technologies Ag | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930608A (en) | 1992-02-21 | 1999-07-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor in which the channel region of the transistor consists of two portions of differing crystallinity |
US5663923A (en) * | 1995-04-28 | 1997-09-02 | Intel Corporation | Nonvolatile memory blocking architecture |
US5621690A (en) * | 1995-04-28 | 1997-04-15 | Intel Corporation | Nonvolatile memory blocking architecture and redundancy |
US5912837A (en) | 1996-10-28 | 1999-06-15 | Micron Technology, Inc. | Bitline disturb reduction |
US5896340A (en) * | 1997-07-07 | 1999-04-20 | Invox Technology | Multiple array architecture for analog or multi-bit-cell memory |
US5886923A (en) * | 1997-10-27 | 1999-03-23 | Integrated Silicon Solution Inc. | Local row decoder for sector-erase fowler-nordheim tunneling based flash memory |
KR100297602B1 (en) | 1997-12-31 | 2001-08-07 | 윤종용 | Method for programming a non-volatile memory device |
US6181599B1 (en) | 1999-04-13 | 2001-01-30 | Sandisk Corporation | Method for applying variable row BIAS to reduce program disturb in a flash memory storage array |
US6212099B1 (en) * | 1999-08-20 | 2001-04-03 | Intel Corporation | Preventing data corruption in a memory device using a modified memory cell conditioning methodology |
KR100381962B1 (en) * | 2000-08-07 | 2003-05-01 | 삼성전자주식회사 | Row decoder of nonvolatile memory device |
US6620682B1 (en) * | 2001-02-27 | 2003-09-16 | Aplus Flash Technology, Inc. | Set of three level concurrent word line bias conditions for a nor type flash memory array |
JP2005510889A (en) * | 2001-11-27 | 2005-04-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device having EEPROM erasable EEPROM memory |
JP4052857B2 (en) * | 2002-03-18 | 2008-02-27 | 株式会社日立製作所 | Nonvolatile semiconductor memory array and memory array read method |
US7064978B2 (en) * | 2002-07-05 | 2006-06-20 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
US7112994B2 (en) * | 2002-07-08 | 2006-09-26 | Viciciv Technology | Three dimensional integrated circuits |
US6707718B1 (en) * | 2002-07-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Generation of margining voltage on-chip during testing CAM portion of flash memory device |
DE10323244A1 (en) * | 2003-05-22 | 2004-12-16 | Infineon Technologies Ag | Integrated memory circuit arrangement, in particular UCP flash memory |
US7072215B2 (en) * | 2004-02-24 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company | Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm |
JP2005268621A (en) * | 2004-03-19 | 2005-09-29 | Toshiba Corp | Semiconductor integrated circuit device |
JP4703162B2 (en) | 2004-10-14 | 2011-06-15 | 株式会社東芝 | Nonvolatile semiconductor memory device and writing method thereof |
JP4421446B2 (en) * | 2004-11-01 | 2010-02-24 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US7046550B1 (en) * | 2005-01-18 | 2006-05-16 | International Business Machines Corporation | Cross-point memory architecture with improved selectivity |
JP2006331501A (en) * | 2005-05-24 | 2006-12-07 | Toshiba Corp | Semiconductor memory apparatus |
US7336540B2 (en) * | 2006-03-29 | 2008-02-26 | Atmel Corporation | Indirect measurement of negative margin voltages in endurance testing of EEPROM cells |
US7324387B1 (en) * | 2006-04-18 | 2008-01-29 | Maxim Integrated Products, Inc. | Low power high density random access memory flash cells and arrays |
US7817474B2 (en) * | 2006-06-01 | 2010-10-19 | Microchip Technology Incorporated | Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
US7706180B2 (en) * | 2007-09-25 | 2010-04-27 | Cypress Semiconductor Corporation | Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory |
US7848148B2 (en) * | 2007-10-18 | 2010-12-07 | Macronix International Co., Ltd. | One-transistor cell semiconductor on insulator random access memory |
CN101621005B (en) * | 2008-07-02 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | TFT MONOS or SONOS memory cell structure |
US8433241B2 (en) | 2008-08-06 | 2013-04-30 | Atc Technologies, Llc | Systems, methods and devices for overlaid operations of satellite and terrestrial wireless communications systems |
CN101763893A (en) * | 2008-12-24 | 2010-06-30 | 上海华虹Nec电子有限公司 | Single tube SONOS NOR-type memory |
US8120966B2 (en) * | 2009-02-05 | 2012-02-21 | Aplus Flash Technology, Inc. | Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory |
KR20120108977A (en) * | 2009-10-23 | 2012-10-05 | 에이플러스 플래시 테크놀러지, 인크. | Novel punch-through free program scheme for nt-string flash design |
JP2011138571A (en) | 2009-12-26 | 2011-07-14 | Elpida Memory Inc | Nonvolatile semiconductor memory and control method of the same |
US8243523B2 (en) * | 2010-03-09 | 2012-08-14 | Micron Technology, Inc. | Sensing operations in a memory device |
KR101753251B1 (en) * | 2010-07-23 | 2017-07-05 | 삼성전자주식회사 | Static random access memory device including negative voltage level shifter |
WO2012036739A2 (en) * | 2010-09-15 | 2012-03-22 | Aplus Flash Technology, Inc. | An eeprom-based, data-oriented combo nvm design |
US8472266B2 (en) | 2011-03-31 | 2013-06-25 | Sandisk Technologies Inc. | Reducing neighbor read disturb |
US8675405B1 (en) * | 2013-03-12 | 2014-03-18 | Cypress Semiconductor Corp. | Method to reduce program disturbs in non-volatile memory cells |
US9595332B2 (en) * | 2015-06-15 | 2017-03-14 | Cypress Semiconductor Corporation | High speed, high voltage tolerant circuits in flash path |
-
2013
- 2013-06-18 US US13/920,352 patent/US8675405B1/en active Active
-
2014
- 2014-01-15 EP EP14778208.0A patent/EP2973584B1/en active Active
- 2014-01-15 WO PCT/US2014/011606 patent/WO2014163725A1/en active Application Filing
- 2014-01-15 CN CN201811314135.XA patent/CN109256164B/en active Active
- 2014-01-15 CN CN201480000066.9A patent/CN104246894B/en active Active
- 2014-01-15 KR KR1020157025859A patent/KR102066831B1/en active IP Right Grant
- 2014-01-27 TW TW107114879A patent/TWI736763B/en active
- 2014-01-27 TW TW103102918A patent/TWI631563B/en active
- 2014-03-17 US US14/216,589 patent/US8988938B2/en active Active
-
2015
- 2015-03-20 US US14/664,131 patent/US9431124B2/en active Active
-
2016
- 2016-08-30 US US15/252,088 patent/US9847137B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6163048A (en) * | 1995-10-25 | 2000-12-19 | Cypress Semiconductor Corporation | Semiconductor non-volatile memory device having a NAND cell structure |
US20050237817A1 (en) * | 2004-04-23 | 2005-10-27 | Akira Umezawa | Semiconductor memory device with MOS transistors, each having a floating gate and a control gate, and memory card including the same |
US7433241B2 (en) * | 2006-12-29 | 2008-10-07 | Sandisk Corporation | Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data |
US7463531B2 (en) * | 2006-12-29 | 2008-12-09 | Sandisk Corporation | Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages |
US20130033934A1 (en) * | 2007-08-30 | 2013-02-07 | Infineon Technologies Ag | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device |
US20110235409A1 (en) * | 2007-09-10 | 2011-09-29 | Hee Bok Kang | Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof |
US20100188898A1 (en) * | 2007-10-05 | 2010-07-29 | Micron Technology, Inc. | Reducing effects of program disturb in a memory device |
US20090290420A1 (en) * | 2008-05-20 | 2009-11-26 | Hynix Semiconductor, Inc. | Program method of nonvolatile memory device |
US8125835B2 (en) * | 2008-09-22 | 2012-02-28 | Cypress Semiconductor Corporation | Memory architecture having two independently controlled voltage pumps |
US8243522B2 (en) * | 2009-12-24 | 2012-08-14 | Intel Corporation | NAND memory programming method using double vinhibit ramp for improved program disturb |
CN102136293A (en) * | 2010-01-22 | 2011-07-27 | 三星电子株式会社 | Method of programming non-volatile semiconductor memory device |
US8274831B2 (en) * | 2010-05-24 | 2012-09-25 | Sandisk Technologies Inc. | Programming non-volatile storage with synchronized coupling |
US8325521B2 (en) * | 2010-10-08 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and inhibited operation of flash memory with split gate |
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WO2014163725A1 (en) | 2014-10-09 |
TW201440056A (en) | 2014-10-16 |
KR20150128737A (en) | 2015-11-18 |
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US8675405B1 (en) | 2014-03-18 |
EP2973584A1 (en) | 2016-01-20 |
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TWI736763B (en) | 2021-08-21 |
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