TWI453759B - Operation method of flash memory - Google Patents

Description

Flash memory operation method

The present invention relates to a method of operating a memory, and more particularly to a method of operating a flash memory.

Non-volatile memory technology is currently the most important memory technology, and one of them has a charge-trapping structure such as Oxide-Nitride-Oxide (ONO) to replace traditional memory cells. Stacked memory cells, which have the advantages of easy process and high density, have been highly valued and studied by various circles, and can also be called charge trap type flash memory. In charge trapping type flash memory, charge can be stored in the ONO of each memory cell, and the stored charge affects its threshold voltage _Vth , and the threshold voltage can be sensed to represent the data.

At present, multi-level cell (MLC) memory cells can be stored to increase storage density. The "multi-order" refers to charge charging with multiple energy levels (ie, multiple voltage values). ), so that the value of multiple bits can be stored in each memory cell, as shown in Figure 1.

In FIG. 1, word lines WL0 WL WL2, bit lines BL1 BL BL2, and a plurality of memory cells 10, and each memory cell 10 corresponds to one word line and two bit lines. However, in the case of the smaller and smaller memory size, two storage bits 100a and 100b in a single memory cell 10 may interact with each other if there are four program levels, such as a storage bit. 100a effect of electric field generated by the stored charge 100b is stored bit to the other occurs when operated, resulting in the so-called second bit effect (2 ^nd bit effect) 102.

Moreover, during the operation of the stylized memory cell 10, since the program voltage is applied to all the memory cells connected to the same word line WL1, the memory bit 100a is disturbed by the stylization of the left side via the bit line BL1 ( Program disturbance) 104. In addition, in the memory that progresses below the 75 nm node, the distance between the word lines WL0 to WL2 is also shortened, and the storage bits 100a and 100b are also subjected to the upper and lower memory cells 10 The word line interference 106 of the storage bit is stored.

2 shows a voltage distribution diagram of the memory cell 100a affected by the parasitic effect described above, wherein the four program levels correspond to different threshold voltage distributions, and the critical states 200, 202, 204, and 206 have different threshold voltage distribution ranges and They are spaced apart from each other. However, as the grain size becomes smaller and smaller, the second bit effect produced by the two bits of a single memory cell causes a large threshold voltage distribution 208. Moreover, because of the stylized disturbing relationship, the threshold voltage distribution 210 is again increased. Then, in the case where the distance between the word lines is getting smaller, the threshold voltage distribution 212 is further increased due to word line interference. Eventually, the critical state 200 and the critical state 202 cannot be distinguished, and all the memory cells in the memory are changed from the original four program levels to three program levels, and can only be operated as one bit.

The present invention provides a method of operating a flash memory, the memory can be avoided by the second bit effect (2 ^nd bit effect), stylized disturb (Program disturbance) and the word line disturbance (Wordline interference) Effects and the like.

The present invention further provides a method of operating a flash memory that can increase the storage density by a factor of 1.5 compared to a conventional unit cell (SLC) or multi-level cell (MLC) memory.

The present invention provides a method for operating a flash memory, in which a storage bit of a plurality of storage bits has a program level of 2 ⁿ , and the storage bits adjacent to the storage bit are stored. The meta is set to have a program level of 2 ^n-1 ; similarly, another storage bit of the plurality of storage bits has a program number of 2 ^n-1 , and the storage bit is adjacent to each other. The storage bits are set to have a program level of 2 ⁿ , where each program level corresponds to a different threshold voltage distribution.

In an embodiment of the invention, the flash memory may be a virtual ground memory array or a NAND type memory.

In an embodiment of the invention, the flash memory includes a memory composed of a charge trap type memory cell or a memory composed of a floating gate type memory cell.

The invention further provides a method for operating a flash memory, the flash memory comprising a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and each memory cell corresponds to one word line and two One bit line. The above operation method includes setting a storage bit in a memory cell corresponding to the same word line to have a program level alternated between 2 ⁿ and 2 ^n-1 , and storing the storage bit in the memory cell corresponding to the same bit line The element is set to have a programmed level of 2 ⁿ and 2 ^n-1 , where each program level corresponds to a different threshold voltage distribution.

In another embodiment of the invention, the flash memory comprises a virtual ground memory array.

In another embodiment of the invention, the memory cell comprises a charge trapping memory cell or a floating gate memory cell.

In various embodiments of the invention, the storage bit is a multi-level cell (MLC).

In various embodiments of the invention, the storage bit comprises a multi-level cell and a unit quasi-cell (SLC).

In various embodiments of the invention, the above n is a positive integer such as 2, 3 or 4.

Based on the above, the present invention designs a storage bit having 2 ^n-1 program levels in the operation method of the flash memory, and surrounds it with 2 ⁿ program level storage bits, and has 2 ⁿ programs. The storage bits of the level are also surrounded by storage bits having 2 ^n-1 program levels, so the storage density of the unit quasi-cell or multi-level cell memory is high, and the parasitic effect can be mitigated at the same time. Keep the program level in a distinguishable state.

The above described features and advantages of the present invention will be more apparent from the following description.

3 is a top view of a flash memory in accordance with an embodiment of the present invention.

Referring to FIG. 3, the method of operating the flash memory of the present embodiment is for operating a flash memory composed of a plurality of memory cells arranged in an array. For example, the flash memory of the embodiment is composed of a plurality of word lines WL0, WL1 and WL2, a plurality of bit lines BL1 and BL2, and a plurality of charge trapping memory cells 30a to 30i, and Each memory cell corresponds to one word line and two bit lines, so the flash memory of this embodiment is a virtual ground memory array. The method of operating the flash memory of this embodiment is to set the storage bits 306b, 300a, 300b, 308a in the memory cells 30d, 30e and 30f corresponding to the same word line WL1 to have 2 ⁿ and 2 ^n-1 Alternate program levels, and the storage bits 302a, 300a, 304a in the memory cells 30b, 30e, and 30h corresponding to the same bit line BL1 are set to have a program level of 2 ⁿ and 2 ^n-1 , wherein Each program level corresponds to a different threshold voltage distribution.

Since the storage bit 300a having the program level of 2 ⁿ in the above embodiment is surrounded by the storage bits 300b, 302a, 304a and 306b having the program level of 2 ^n-1 , the parasitic effect can be reduced ( parasitic effect), to avoid the reduced level; a level 2 ⁿ number of programs is stored bit 300a, having a number 302b, 308a and 304b is surrounded by the formula 2 ^n-1 of the storage level of the bit 300b can withstand more Large parasitic effects without lowering the level. In other words, at least half of the memory cells of the entire flash memory can perform a program level of 2 ⁿ , so the above embodiment increases the storage density by 1.5 times compared to the conventional method of using the unit cell (SLC) memory cells. (storage density). In addition, the above embodiment can also increase the storage density by 1.5 times compared with a memory which itself can be used as a multi-level cell (MLC).

In the above embodiment, the value of n in the program level number may be a positive integer greater than or equal to 2, such as 2, 3 or 4. Therefore, the storage bit 300a of the memory cell 30e is a multi-level cell; and the storage bit 300b is a unit quasi-cell when n=2, and belongs to a multi-level cell when n is 3 or more.

Figure 4 shows a voltage distribution diagram of the storage bit 300a when n is 2. In Figure 4, the four program levels correspond to different threshold voltage distributions, critical states 400 (zero level), 402 (first level), 404 (second level), and 406 (third level). Each has a clear threshold voltage distribution range and is spaced apart from each other. Since the storage location 300a of a large program level (such as 4 program levels) is surrounded by a storage bit having a small number of program levels (such as 2 program levels), the second bit effect can be alleviated. (2 ^nd bit effect) threshold voltage distribution 408, threshold voltage distribution 410 due to program disturbance and threshold voltage distribution 412 due to word line interference, so that the program level (critical State 400) is maintained in a distinguishable state.

Further, the method of operating the flash memory of the present invention can also be applied to a NAND type memory.

Figure 5 is a top plan view of a flash memory in accordance with another embodiment of the present invention. Referring to FIG. 5, the method of operating the flash memory of this embodiment is for operating a flash memory composed of a plurality of memory cells arranged in an array. For example, the flash memory of this embodiment may be a NAND type flash memory, which is composed of a plurality of word lines WL1, WL2, and WL3, a plurality of active regions A1, A2, and A3, and numbers. Each memory cell is composed of 50a~50i, and each memory cell in the figure is located between a word line and an active area, wherein the memory cells 50a~50i may be charge trap type memory cells or floating gate type memory cells. The operation method of this embodiment is that when the storage bit 508 of the memory cell 50e has a program level of 2 ⁿ , the adjacent storage bits 502, 506, 510 and 514 are set to have a number of 2 ^n- The program level of ¹ is correct. Similarly, when the storage bit 502 has a program level of 2 ^n-1 , it is necessary to set the adjacent storage bits 500, 504, 508, etc. around it to have a program level of 2 ⁿ . As such, the voltage distribution of the storage bit 508 of FIG. 5 when n is 2 will also be the same as FIG.

Figure 6 is a top plan view of a flash memory in accordance with an embodiment of the present invention. The flash memory in FIG. 6 is composed of a plurality of word lines WL1 to WL4, a plurality of bit lines BL1 to BL3, and a plurality of floating gate type memory cells 60a to 60l, and each memory in the figure The cell is a memory bit, so the flash memory of this embodiment can also be regarded as a NOR-type floating gate memory array composed of a plurality of memory cells 600-622 arranged in an array.

The method of operating the flash memory of FIG. 6 is to set the storage bit 600, 602, 604 corresponding to the same word line WL1 to have a program level of 2 ⁿ and 2 ^n-1 , and will correspond to the same bit. The storage bits 600, 606, 612, 618 of the line BL1 are set to have a programmed level of 2 ⁿ and 2 ^n-1 , wherein each program level corresponds to a different threshold voltage distribution. Such an operation design can be alleviated because the storage bit 608 having a large number of program levels (2 ⁿ ) is surrounded by the storage bits 602, 606, 610 and 614 with a small number of program levels (2 ^n-1 ). The threshold voltage distribution of the stylized disturbance and the critical voltage distribution resulting from the word line interference maintain the program level in a distinguishable state.

In summary, the design concept proposed by the present invention encloses a storage bit having a program level of 2 ⁿ around a storage bit having a program level of 2 ^n-1 to avoid storing bits. The level of the yuan is reduced. Therefore, at least half of the entire memory of the flash memory can perform a program level of 2 ⁿ , compared to the traditional method of using unit cell (SLC) and multi-level cell (MLC) memory cells. Has a higher storage density. On the other hand, a large number of program level (e.g., 2 ⁿ⁾ is stored bit program level places small number (e.g., 2 ^n-1) bits surround the storage, in order to reduce parasitic effects, so that the program can be maintained at a level The state of difference.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

A1, A2, A3‧‧‧ active area

BL1, BL2, BL3‧‧‧ bit line

WL0, WL1, WL2, WL3, WL4‧‧‧ character lines

10, 30a~30i, 50a~50i, 60a~60l‧‧‧ memory cells

100a, 100b, 300a, 300b, 302a, 302b, 304a, 304b, 306b, 308a, 500~516, 600~622‧‧‧ storage bits

102‧‧‧ second bit effect

104‧‧‧Stylized disruption

106‧‧‧word line interference

200, 202, 204, 206, 400, 402, 404, 406‧‧‧ critical state

208, 210, 212, 408, 410, 412‧‧ ‧ threshold voltage distribution

1 is a top view of a conventional charge trapping type flash memory.

Figure 2 shows the voltage distribution of memory cells affected by parasitic effects.

3 is a top view of a flash memory in accordance with an embodiment of the present invention.

4 shows a voltage distribution diagram of the first memory cell when n of the storage bit of FIG. 3 is 2.

Figure 5 is a top plan view of a flash memory in accordance with another embodiment of the present invention.

6 is a top plan view of a floating gate flash memory in accordance with an embodiment of the present invention.

30a~30i. . . Memory cell

300a, 300b, 302a, 302b, 304a, 304b, 306b, 308a. . . Storage bit

BL1, BL2. . . Bit line

WL0, WL1, WL2. . . Word line

Claims (10)

A method for operating a flash memory for operating a flash memory composed of a plurality of storage bits arranged in an array, the method comprising: storing a number of the storage bits in the plurality of storage bits When the program level is 2 ⁿ , the adjacent storage bits around the storage bit are set to have a program level of 2 ^n-1 ; and the other of the plurality of storage bits The storage bit has a program number of 2 ^n-1 , and the adjacent storage bits around the other storage bit are set to have a program level of 2 ⁿ , wherein each program level corresponds to a different The critical voltage distribution. The method of operating a flash memory as described in claim 1, wherein the flash memory comprises a virtual grounded memory array or a NAND type memory. The method of operating a flash memory according to claim 1, wherein the flash memory comprises a memory composed of a plurality of charge trapping memory cells or a plurality of floating gate memory cells. Memory. A method for operating a flash memory, the flash memory comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, and each memory cell corresponds to one of the plurality of word lines and the a pair of a plurality of bit lines, the operation method comprising: setting a plurality of storage bits of the plurality of memory cells corresponding to the same word line to have a program level of 2 ⁿ and 2 ^n-1 alternating And setting a plurality of storage bits of the plurality of memory cells corresponding to the same bit line to have a program level of 2 ⁿ and 2 ^n-1 , wherein each program level corresponds to a different threshold voltage distribution . The method of operating a flash memory according to claim 1 or 4, wherein the plurality of storage bits are multi-level cells (MLC). The method of operating a flash memory according to claim 1 or 4, wherein the plurality of storage bits comprise a multi-level cell and a unit cell (SLC). The method of operating a flash memory as described in claim 1 or 4, wherein n is a positive integer greater than or equal to 2. The method of operating a flash memory as described in claim 7, wherein n is 2, 3 or 4. The method of operating a flash memory as described in claim 4, wherein the flash memory comprises a virtual grounded memory array. The method of operating a flash memory according to claim 4, wherein the plurality of memory cells comprise a charge trapping memory cell or a floating gate memory cell.