1361301 .A \ _____________________ ----——_ _____ i 【發明所屬之技術領域】 % 本發明是有關於一種顯示裝置’且特別是有關於一種具 '有覆晶結構（Flip Chip)之顯示裝置。 、 【先前技術】 在具有覆晶結構之顯示裝置中’積體電路（1C)晶片之下 表面上設有數個銲接凸塊（Bump)，以供積體電路晶片與顯 |示裝置之顯示面板電性接合。 凊參照第1圖’其係繪示傳統具有覆晶結構之顯示裝置 的局部剖面示意圖。將積體電路（1C)晶片1 〇8接合在顯示裝 置100之顯示面板102上時，通常先在顯示面板1〇2上塗— 層異方性導電膠（Anisotropic Conductive Film)104，再將積 體電路晶片108置放並壓合在異方性導電膠1 〇4上，以利用 異方性導電膠104將積體電路晶片108黏合在顯示面板1〇2 上。由於積體電路晶片108之底面設有許多連接凸塊1〇6, |因此當積體電路晶片108之底面壓合在異方性導電膠1〇4 上時’連接凸塊106與異方性導電膠1〇4内之導電粒子會因 壓合而產生接觸’積體電路晶片108本身即可經由連接凸塊 106與異方性導電膠1〇4而與顯示面板1〇2上的預設線路形 成導通。 然而’ 一般積體電路晶片上之連接凸塊的設計往往只考 慮到功此性’而忽略結構上的均勻對稱性，因此積體電路晶 片上之連接凸塊的位置大都分布不均。在連接凸塊的位置分 布不均的情況下，於接合過程中，會發生壓力不平均的現 1361301 象’而使積體電路晶片產生翹翹板現象，如此一來，會導致 連接凸塊與異方性導電膠内之導電粒子的壓合不佳。由於連 接凸塊與異方性導電膠内之導電粒子之間的壓合力道太大 •或太小都會造成訊號的導通不良，因此會導致覆晶製程的接 • 合良率下降。 【發明内容】 因此，本發明之目的就是在提供一種具有覆晶結構之顯 |不裝置’其係在積體電路晶片之連接凸塊設置的表面上，增 設一些虛設凸塊（Dummy Bump) ’如此一來，可有效提高積 體電路晶片之凸塊設置表面上的凸塊分布的均勻度，而可防 止積體電路晶片在壓設至顯示裝置上時所可能產生之壓合 不良現象，例如翹翹板現象。 本發明之另一目的是在提供一種具有覆晶結構之顯示 裝置’其積體電路晶片上額外增設有虛設凸塊，因此可大幅 改善覆晶製程之接合良率。 % 本發明之又一目的是在提供一種具有覆晶結構之顯示 裝置’其積體電路晶片上或基板上可額外增設虛設凸塊，不 僅可均衡壓合力’並可增強積體電路晶片之結構強度，更可 作為連接二連接凸塊之跑線。 根據本發明之上述目的’提出一種具有覆晶結構之顯示 裝置，至少包括：一第一基板；至少一積體電路晶片，設在 ’第一基板上’其中此積體電路晶片之一表面上設有複數個連 接凸塊’且這些連接凸塊接合在積體電路晶片與第一基板之 間，以及至少一虛設凸塊，夾設於積體電路晶片與第一基板 1361301 之間’以平衡積體電路晶片之表面上之連接凸塊的分布。 依照本發明一較佳實施例，上述之虛設凸塊為肋狀凸 塊’以提供更優異之均衡效果，並可增加積體電路晶片之機 構強度。 .根據本發明之目的，提出一種具有覆晶結構之顯示裝 置，至少包括：一第一基板；一導電膠層，塗於第一基板之 一表面上；至少一積體電路晶片，設在第一基板之塗有導電 膠層之表面之上；複數個連接凸塊，設在積體電路晶片之一 表面上，並透過導電膠層而接合在第一基板之表面上；以及 至少一虛設凸塊，夾設於積體電路晶片之表面與第一基板之 表面間，以平衡積體電路晶片貼設在第一基板之表面上時的 應力分布。 依照本發明一較佳實施例’上述之虛設凸塊也可為連接 二連接凸塊之跑線。 【實施方式】 • 本發明揭露一種具有覆晶結構之顯示裝置，可大幅改善 覆晶製程之壓合良率，並可強化積體電路晶片之結構強度。 為了使本發明之敘述更加詳盡與完備，可參照下列描述並配 合第2圖至第4B圖之圖示。 請參照第2圖，其係繪示依照本發明-較佳實施例的一 種具有覆晶結構之顯示裝置的部分裝置之剖面示意圖 .晶結構之顯示裝置2〇〇包括第一基板2〇2,其中第一基板加 上設有顯示層206,且第一基板2〇2之材質可為玻璃、或可 撓性基板。在本不範實施例中，顯示裝置1361301 .A \ _____________________ ----——_ _____ i [Technical Field of the Invention] % The present invention relates to a display device', and more particularly to a display device having a 'Flip Chip' . [Prior Art] In the display device having a flip chip structure, a plurality of solder bumps are provided on the lower surface of the integrated circuit (1C) wafer for the display panel of the integrated circuit chip and the display device Electrically bonded. Referring to Fig. 1 which is a partial cross-sectional view showing a conventional display device having a flip chip structure. When the integrated circuit (1C) wafer 1 〇 8 is bonded to the display panel 102 of the display device 100, an anisotropic conductive film 104 is usually applied to the display panel 1 〇 2, and then the integrated body is assembled. The circuit wafer 108 is placed and pressed on the anisotropic conductive paste 1 〇 4 to bond the integrated circuit wafer 108 to the display panel 1 利用 2 by the anisotropic conductive paste 104. Since the bottom surface of the integrated circuit wafer 108 is provided with a plurality of connection bumps 1〇6, the connection bumps 106 and the anisotropy are formed when the bottom surface of the integrated circuit wafer 108 is pressed against the anisotropic conductive paste 1〇4. The conductive particles in the conductive paste 1〇4 are contacted by the pressing. The integrated circuit wafer 108 itself can be preset to the display panel 1〇2 via the connection bump 106 and the anisotropic conductive paste 1〇4. The line is formed to conduct. However, the design of the connection bumps on a general integrated circuit wafer tends to take into account only the workability, and the uniform symmetry of the structure is neglected, so that the positions of the connection bumps on the integrated circuit wafer are largely unevenly distributed. In the case where the position of the connecting bumps is unevenly distributed, during the bonding process, the current unbalanced 1361301 image may occur, and the integrated circuit wafer may be warped, thereby causing the connecting bumps to be The bonding of the conductive particles in the anisotropic conductive paste is poor. Since the bonding force between the connecting bumps and the conductive particles in the anisotropic conductive paste is too large or too small, the signal conduction is poor, and the bonding yield of the flip chip process is lowered. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a display device having a flip chip structure which is provided on a surface of a connection bump of an integrated circuit chip, and a dummy dummy (Dummy Bump) is added. In this way, the uniformity of the distribution of the bumps on the bump setting surface of the integrated circuit chip can be effectively improved, and the poor bonding phenomenon which may occur when the integrated circuit wafer is pressed onto the display device can be prevented, for example, Seesaw phenomenon. Another object of the present invention is to provide a display device having a flip chip structure, in which a dummy bump is additionally added to the integrated circuit wafer, so that the bonding yield of the flip chip process can be greatly improved. Another object of the present invention is to provide a display device having a flip chip structure, in which an additional dummy bump can be added on or on the integrated circuit wafer, which not only equalizes the pressing force, but also enhances the structure of the integrated circuit wafer. The strength can be used as a running line connecting the two connecting bumps. According to the above object of the present invention, a display device having a flip chip structure includes at least: a first substrate; at least one integrated circuit wafer disposed on a surface of one of the integrated circuit wafers on the 'first substrate a plurality of connection bumps are disposed, and the connection bumps are bonded between the integrated circuit chip and the first substrate, and at least one dummy bump is sandwiched between the integrated circuit chip and the first substrate 1361301 to balance The distribution of the connection bumps on the surface of the integrated circuit chip. In accordance with a preferred embodiment of the present invention, the dummy bumps described above are rib-like bumps to provide a more superior balancing effect and to increase the mechanical strength of the integrated circuit wafer. According to an object of the present invention, a display device having a flip chip structure includes at least: a first substrate; a conductive adhesive layer coated on a surface of the first substrate; and at least one integrated circuit chip disposed at the a substrate coated with a surface of the conductive adhesive layer; a plurality of connecting bumps disposed on a surface of the integrated circuit chip and bonded to the surface of the first substrate through the conductive adhesive layer; and at least one dummy convex The block is interposed between the surface of the integrated circuit wafer and the surface of the first substrate to balance the stress distribution when the integrated circuit wafer is attached to the surface of the first substrate. In accordance with a preferred embodiment of the present invention, the dummy bumps described above may also be run lines connecting the two connection bumps. [Embodiment] The present invention discloses a display device having a flip chip structure, which can greatly improve the press-fit yield of the flip chip process and enhance the structural strength of the integrated circuit chip. In order to make the description of the present invention more detailed and complete, reference is made to the following description in conjunction with the drawings of Figures 2 through 4B. 2 is a schematic cross-sectional view showing a portion of a device having a flip-chip display device according to a preferred embodiment of the present invention. The display device 2 of the crystal structure includes a first substrate 2〇2, The first substrate is provided with a display layer 206, and the material of the first substrate 2〇2 may be glass or a flexible substrate. In the present embodiment, the display device
<S 7 1361301 基板綱覆蓋在第一基板2〇2上，其中第二基板2〇4之材質 可為玻璃、金屬、高分子化合物層、氧化物層、或由高分子 化合物層與氧化物層所堆疊而成之結構。此外，第二基板 204亦可採用封膠體。在本發明中，顯示裝置2〇〇可為有機 電激發光—極體面板或液晶顯示面板。此顯示裝置2⑼之積 體電路晶片208係透過導電膠210而黏設在第—基板202 之表面226上，而第一基板2〇2之材質雖可為玻璃或其他塑 膠材料仁般係採用玻璃，因此這樣的結構通常又稱為玻 每璃覆晶結構。其中，導電膠21〇可例如採用異方性導電膠。 在本示範實施例中，顯示裝置2〇〇可進一步包括至少一連接 介面212,其中連接介面212之一端透過連接銲墊214連接 於第一基板202之表面226上，連接介面212之另一端則連 接至一外部系統電路，以使顯示裝置2〇2與外部系統電路電 性聯繫。連接介面2 12可例如為軟性印刷電路板（FpCB)等。 請參照第3圖，其係繪示依照本發明一較佳實施例的一 種具有覆晶結構之顯示裝置的積體電路晶片之連接凸塊設 •置示忍圖。在本示範實施例中，積體電路晶片208的表面 216上設有數個連接凸塊218，這些連接凸塊218經由導電 膠210而與第一基板2〇2上之預設凸塊墊（未繪示於圖中） 電性連接’如第2圖所示。此外’積體電路晶片208之表面 216上更設有虛設凸塊22〇 ’其中虛設凸塊22〇係設置在積 體電路晶片208之表面216上連接凸塊218分布較為疏鬆的 '區域’以平衡積體電路晶片208之表面216上之連接凸塊 218的分布。同時，由於連接凸塊218與虛設凸塊22〇係央 設於積體電路晶片208之表面216與第一基板202之表面 1361301 226之間’因此將積體電路晶片2〇8壓合在第一基板2〇2之 表面226上的導電膠210時，可平衡積體電路晶片208貼設 第基板202之表面226上時的應力分布，如第2圖斑第 3圖所示。本發明之虛設凸塊220與連接凸塊218之材質可 相同亦可互不相同，其中虛設凸塊22〇與連接凸塊218之材 料可同為導電材料，例如金、銅、鋁或上述金屬之任意合金 組合；或者，連接凸塊218之材料為導電材料，而虛設凸塊 220之材料為絕緣材料。 在本發明中，積體電路晶片208之表面216上所設之虛 设凸塊220的數量、形狀與位置可根據各積體電路晶片2〇8 之表面216上之連接凸塊21 8的分布來加以調整。請參照第 4A圖，在本發明之一較佳實施例中，虛設凸塊“Μ可為肋 狀凸塊，以提供積體電路晶片2〇8多個方向性的結構補強。 另外，虛設凸塊220a更可為連接二連接凸塊218之跑線， 如第4A圖與第4B圖所示。兼做為跑線時，虛設凸塊 之材料需為導電材料’其中以虛設凸塊22〇a做為跑線時的 阻抗小於設置在第—基板漁之表面226上的跑線的阻抗。 在本發明之—實施例中，一虛設凸塊220a之厚度一 =。在本發明之其他實施例中，一虛設凸塊22如之厚=不 致此外如第2圖與第4B圖所示，虛設凸塊22〇a之 厚度224較佳係小於或等於連接凸塊218之厚纟222,亦即 虛設凸塊22Ga之厚度224較㈣不大於連接凸塊218之厚 度222，以利連接凸塊218透過導電勝則，而 202電性連接。 ”弟基板 藉由在積體電路晶片 2〇8之表面216上連接凸塊218 1361301 分布較為稀疏的區域上設置虛設凸塊220，可提高積體電路 晶片208之表面216上所設置之結構物的均勻度，而可改善 將積體電路晶片208之表面216壓合在第一基板2〇2之表面 226上凸塊墊時的壓力分布均勻度，可有效避免傳統覆晶製 程所產生之壓合不良現象，例如想魅板現象，進而可大幅提 同覆晶製程之良率。此外，虛設凸塊220的設置，亦可增強 積體電路晶片208之結構強度，有利於積體電路晶片2〇8 之壓合良率。 在上述之實施例中，虛設凸塊係預先設置在積體電路晶 片之表面上；然而，在本發明之其他實施例中，虛設凸塊亦 可預先設置在第一基板上，且虛設凸塊在第一基板上之位置 較佳係對應於積體電路晶片表面上之連接凸塊分布較為稀 疏的區域。因此’在本發明中，當積體電路晶片貼合在第一 基板後’虛設凸塊係夾設在積體電路晶片與第一基板之間， 而達到平衡積體電路晶片貼設在第一基板之表面上時的應 力分布。 由上述本發明較佳實施例可知，本發明之一優點就是因 為在本發明之具有覆晶結構之顯示裝置中，其積體電路晶片 設有連接凸塊的表面上增設有至少一虛設凸塊，因此可有效 提高積體電路晶片之凸塊設置表面上的結構物分布均勻 度，而可防止積體電路晶片在壓設至顯示裝置之顯示面板上 時所可能產生之翹翹板現象。 由上述本發明較佳實施例可知’本發明之另一優點就是 因為本發明之具有覆晶結構之顯示裝置的積體電路晶片上 額外增設有虛設凸塊，因此可大幅改善覆晶製程之接合良 1361301 率。 由上述本發明較佳實施例可知，本發明之又一優點就是 因為本發明之具有覆晶結構之顯示裝置的積體電路晶片上 可額外增設虛設凸塊，不僅可均衡壓合力，並可增強積體電 路晶片之結構強度，更可作為連接二連接凸塊之跑線。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何在此技術領域中具有通常知識者，在不脫 離本發明之精神和範圍内，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 -第1圖係繪示傳統具有覆晶結構之顯示裝置的局部 面不意圖。 第2圖係繪示依照本發明一較佳實施例的一種具有覆 晶結構之顯示裝置的部分裝置之剖面示意圖。 第3圖係繪示依照本發明一較佳實施例的一種具有覆 晶結構之顯示裝置的積體電路晶片之連接凸塊設置示意圖。 第4A圖係緣示依照本發明另—較佳實施例的—種具有 2結構之顯示裝置的㈣電路晶片之連接凸塊的上視示 意、圖。 :4 B圖係繪不依照本發明另一較佳實施例的一種具有 意；之顯示裝置的積體電路晶片之連接凸塊的側視示 【主要元件符號說明】 1361301<S 7 1361301 The substrate is covered on the first substrate 2〇2, wherein the material of the second substrate 2〇4 may be glass, metal, polymer compound layer, oxide layer, or polymer compound layer and oxide The structure in which the layers are stacked. In addition, the second substrate 204 may also be a sealant. In the present invention, the display device 2A may be an organic electroluminescence-polar panel or a liquid crystal display panel. The integrated circuit chip 208 of the display device 2 (9) is adhered to the surface 226 of the first substrate 202 through the conductive adhesive 210, and the material of the first substrate 2〇2 can be glass or other plastic material. Therefore, such a structure is often referred to as a glass-to-glass flip-chip structure. The conductive adhesive 21 can be, for example, an anisotropic conductive paste. In the exemplary embodiment, the display device 2 can further include at least one connection interface 212, wherein one end of the connection interface 212 is connected to the surface 226 of the first substrate 202 through the connection pad 214, and the other end of the connection interface 212 is Connected to an external system circuit to electrically connect display device 2〇2 to external system circuitry. The connection interface 2 12 can be, for example, a flexible printed circuit board (FpCB) or the like. Referring to FIG. 3, a connection bump of a built-in circuit chip having a flip-chip display device according to a preferred embodiment of the present invention is shown. In the exemplary embodiment, the surface 216 of the integrated circuit wafer 208 is provided with a plurality of connecting bumps 218, and the connecting bumps 218 are connected to the predetermined bump pads on the first substrate 2〇2 via the conductive paste 210 (not Shown in the figure) Electrical connection ' as shown in Figure 2. In addition, the surface 216 of the integrated circuit wafer 208 is further provided with dummy bumps 22', wherein the dummy bumps 22 are disposed on the surface 216 of the integrated circuit wafer 208, and the connection bumps 218 are loosely distributed. The distribution of the connection bumps 218 on the surface 216 of the integrated circuit wafer 208 is balanced. At the same time, since the connection bumps 218 and the dummy bumps 22 are disposed between the surface 216 of the integrated circuit wafer 208 and the surface 1361301 226 of the first substrate 202, the integrated circuit chip 2〇8 is pressed together. When the conductive paste 210 on the surface 226 of the substrate 2 is used, the stress distribution when the integrated circuit wafer 208 is attached to the surface 226 of the substrate 202 can be balanced, as shown in Fig. 3 of Fig. 2. The material of the dummy bump 220 and the connecting bump 218 of the present invention may be the same or different from each other, wherein the material of the dummy bump 22 and the connecting bump 218 may be the same as a conductive material, such as gold, copper, aluminum or the above metal. Any alloy combination; or the material of the connection bump 218 is a conductive material, and the material of the dummy bump 220 is an insulating material. In the present invention, the number, shape and position of the dummy bumps 220 provided on the surface 216 of the integrated circuit wafer 208 may be distributed according to the distribution bumps 218 on the surface 216 of each integrated circuit wafer 2〇8. To adjust it. Referring to FIG. 4A, in a preferred embodiment of the present invention, the dummy bumps “Μ may be rib-like bumps to provide structural reinforcement of the integrated circuit wafer 2〇8. directional dummy The block 220a may be a running line connecting the two connecting bumps 218, as shown in FIG. 4A and FIG. 4B. When used as a running line, the material of the dummy bumps needs to be a conductive material 'where the dummy bumps 22 〇 The impedance of a as a running line is less than the impedance of the running line disposed on the surface 226 of the first substrate. In the embodiment of the present invention, the thickness of a dummy bump 220a is one =. Other implementations of the present invention For example, if the thickness of the dummy bump 22 is not greater than or equal to the thickness 222 of the connecting bump 218, as shown in FIGS. 2 and 4B, the thickness 224 of the dummy bump 22a is preferably less than or equal to the thickness 222 of the connecting bump 218. That is, the thickness 224 of the dummy bump 22Ga is not more than (4) than the thickness 222 of the connection bump 218, so that the connection bump 218 is electrically conductive, and the electrical connection is 202. The younger substrate is formed by the integrated circuit chip 2〇8. On the surface 216, the connecting bump 218 1361301 is disposed on the sparsely distributed area, and the dummy bump 220 is disposed on the surface. The uniformity of the structure provided on the surface 216 of the integrated circuit wafer 208 improves the pressure distribution when the surface 216 of the integrated circuit wafer 208 is pressed against the bump pads on the surface 226 of the first substrate 2〇2. The uniformity can effectively avoid the poor pressing phenomenon caused by the traditional flip chip process, for example, the phenomenon of the charm plate can be greatly improved, and the yield of the flip chip process can be greatly improved. In addition, the arrangement of the dummy bumps 220 can also enhance the structural strength of the integrated circuit wafer 208, which is advantageous for the bonding yield of the integrated circuit wafers 2〇8. In the above embodiments, the dummy bumps are previously disposed on the surface of the integrated circuit chip; however, in other embodiments of the present invention, the dummy bumps may also be disposed on the first substrate in advance, and the dummy bumps are The position on the first substrate preferably corresponds to a region where the connection bumps on the surface of the integrated circuit wafer are sparsely distributed. Therefore, in the present invention, after the integrated circuit wafer is attached to the first substrate, the dummy bump is interposed between the integrated circuit chip and the first substrate, and the balanced integrated circuit is attached to the first wafer. Stress distribution on the surface of the substrate. According to the preferred embodiment of the present invention, an advantage of the present invention is that, in the display device having a flip chip structure of the present invention, at least one dummy bump is added to the surface of the integrated circuit chip provided with the connection bump. Therefore, the uniformity of the structure distribution on the bump setting surface of the integrated circuit wafer can be effectively improved, and the warping phenomenon which may occur when the integrated circuit wafer is pressed onto the display panel of the display device can be prevented. According to the preferred embodiment of the present invention described above, another advantage of the present invention is that the dummy bumps are additionally added to the integrated circuit of the display device having the flip chip structure of the present invention, so that the bonding of the flip chip process can be greatly improved. Good 13631301 rate. According to the preferred embodiment of the present invention, another advantage of the present invention is that an additional dummy bump can be added to the integrated circuit of the display device having the flip chip structure of the present invention, which not only equalizes the pressing force but also enhances The structural strength of the integrated circuit chip can be used as a running line connecting the two connecting bumps. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is intended that various modifications may be made without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS - Fig. 1 is a partial view showing a conventional display device having a flip chip structure. 2 is a cross-sectional view showing a portion of a device having a display device having a recrystallized structure in accordance with a preferred embodiment of the present invention. 3 is a schematic view showing the arrangement of connection bumps of an integrated circuit wafer of a display device having a flip-chip structure according to a preferred embodiment of the present invention. Fig. 4A is a top view and a view showing a connecting bump of a (4) circuit wafer having a display device of two structures in accordance with another preferred embodiment of the present invention. 4B is a side view showing a connecting bump of an integrated circuit chip which is not in accordance with another preferred embodiment of the present invention. [Main component symbol description] 1361301
100 ： 顯示裝置 102 ： 顯 示 面 板 104 ： 異方性導電膠 106 ： 連接 凸 塊 108 ： 積體電路晶片 200 ： 顯 示 裝 置 202 ： 第一基板 204 ： 第 二 基板 206 ： 顯示層 208 ： 積 體 電 路 210 ： 導電膠 212 ： 連接 介 面 214 ： 連接銲墊 216 ： 表 面 218 ： 連接凸塊 220 ： 虛 設 凸 塊 220a :虛設凸塊 222 ： 厚 度 224 ： 厚度 226 ： 表 面100 : display device 102 : display panel 104 : anisotropic conductive paste 106 : connection bump 108 : integrated circuit wafer 200 : display device 202 : first substrate 204 : second substrate 206 : display layer 208 : integrated circuit 210 : Conductive adhesive 212 : connection interface 214 : connection pad 216 : surface 218 : connection bump 220 : dummy bump 220a : dummy bump 222 : thickness 224 : thickness 226 : surface